Title:
DISCRETE TIME LOWPASS FILTER
Document Type and Number:
WIPO Patent Application WO/2011/020070
Kind Code:
A3
Abstract:
A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal.
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Inventors:
FAGG RUSSELL JOHN (US)
BURKE JOSEPH PATRICK (US)
BURKE JOSEPH PATRICK (US)
Application Number:
PCT/US2010/045535
Publication Date:
September 22, 2011
Filing Date:
August 13, 2010
Export Citation:
Assignee:
QUALCOMM INC (US)
FAGG RUSSELL JOHN (US)
BURKE JOSEPH PATRICK (US)
FAGG RUSSELL JOHN (US)
BURKE JOSEPH PATRICK (US)
International Classes:
H03H19/00; H03H15/02
Foreign References:
| US4653017A | 1987-03-24 | |||
| US5289059A | 1994-02-22 | |||
| US20060071707A1 | 2006-04-06 |
Other References:
DANIEL C. VON GRÜNIGEN; RAINER SIGG; MICHAEL LUDWIG; URS W. BRUGGER; GEORGE S. MOSCHYTZ ; HANS MELCHIOR: "Integrated Switched-Capacitor Low-Pass Filter with Combined Anti-Aliasing Decimation Filter for Low Frequencies", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-17, no. 6, 1 December 1982 (1982-12-01), USA, pages 1024 - 1029, XP002619996
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MOSTAFA M A I ET AL: "WCDMA receiver architecture with unique frequency plan", ASIC/SOC CONFERENCE, 2001. PROCEEDINGS. 14TH ANNUAL IEEE INTERNATIONAL SEPT. 12-15, 2001, PISCATAWAY, NJ, USA,IEEE, 12 September 2001 (2001-09-12), pages 57 - 61, XP010560756, ISBN: 978-0-7803-6741-8
RAHIM BAGHERI ET AL: "An 800-MHz-6-GHz Software-Defined Wireless Receiver in 90-nm CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 41, no. 12, 1 December 2006 (2006-12-01), pages 2860 - 2876, XP011150713, ISSN: 0018-9200, DOI: DOI:10.1109/JSSC.2006.884835
HIRATA Y ET AL: "High frequency switched capacitor IIR filters using parallel cyclic type circuits", PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. SAN DIEGO, MAY 10 - 13, 1992; [PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. (ISCAS)], NEW YORK, IEEE, US, vol. 3, 3 May 1992 (1992-05-03), pages 1199 - 1202, XP010061431, ISBN: 978-0-7803-0593-9, DOI: DOI:10.1109/ISCAS.1992.230310
YOSHINORI HIRATA ET AL: "HIGH-FREQUENCY IIR SWITCHED CAPACITOR FILTER USING PARALLEL CYCLIC-TYPE CIRCUIT WITH LOW-POWER CONSUMPTION", ELECTRONICS & COMMUNICATIONS IN JAPAN, PART III - FUNDAMENTALELECTRONIC SCIENCE, WILEY, HOBOKEN, NJ, US, vol. 76, no. 7, 1 July 1993 (1993-07-01), pages 37 - 48, XP000442080, ISSN: 1042-0967
CIOTA Z ET AL: "Analogue realisation of integrated FIR filters", IEE PROCEEDINGS: CIRCUITS DEVICES AND SYSTEMS, INSTITUTION OF ELECTRICAL ENGINEERS, STEVENAGE, GB, vol. 143, no. 5, 8 October 1996 (1996-10-08), pages 274 - 281, XP006006133, ISSN: 1350-2409, DOI: DOI:10.1049/IP-CDS:19960611
P.R. GRAY ET AL: "A low-noise chopper-stabilized differential switched-capacitor filtering technique", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 16, no. 6, 1 December 1981 (1981-12-01), pages 708 - 715, XP055002080, ISSN: 0018-9200, DOI: 10.1109/JSSC.1981.1051666
QUINN P ET AL: "Capacitor matching insensitive algorithmic ADC requiring no calibrations", INTEGRATION, THE VLSI JOURNAL, NORTH-HOLLAND PUBLISHING COMPANY. AMSTERDAM, NL, vol. 36, no. 4, 1 November 2003 (2003-11-01), pages 211 - 228, XP004476846, ISSN: 0167-9260, DOI: DOI:10.1016/J.VLSI.2003.09.004
MOSTAFA M A I ET AL: "WCDMA receiver architecture with unique frequency plan", ASIC/SOC CONFERENCE, 2001. PROCEEDINGS. 14TH ANNUAL IEEE INTERNATIONAL SEPT. 12-15, 2001, PISCATAWAY, NJ, USA,IEEE, 12 September 2001 (2001-09-12), pages 57 - 61, XP010560756, ISBN: 978-0-7803-6741-8
RAHIM BAGHERI ET AL: "An 800-MHz-6-GHz Software-Defined Wireless Receiver in 90-nm CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 41, no. 12, 1 December 2006 (2006-12-01), pages 2860 - 2876, XP011150713, ISSN: 0018-9200, DOI: DOI:10.1109/JSSC.2006.884835
HIRATA Y ET AL: "High frequency switched capacitor IIR filters using parallel cyclic type circuits", PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. SAN DIEGO, MAY 10 - 13, 1992; [PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. (ISCAS)], NEW YORK, IEEE, US, vol. 3, 3 May 1992 (1992-05-03), pages 1199 - 1202, XP010061431, ISBN: 978-0-7803-0593-9, DOI: DOI:10.1109/ISCAS.1992.230310
YOSHINORI HIRATA ET AL: "HIGH-FREQUENCY IIR SWITCHED CAPACITOR FILTER USING PARALLEL CYCLIC-TYPE CIRCUIT WITH LOW-POWER CONSUMPTION", ELECTRONICS & COMMUNICATIONS IN JAPAN, PART III - FUNDAMENTALELECTRONIC SCIENCE, WILEY, HOBOKEN, NJ, US, vol. 76, no. 7, 1 July 1993 (1993-07-01), pages 37 - 48, XP000442080, ISSN: 1042-0967
CIOTA Z ET AL: "Analogue realisation of integrated FIR filters", IEE PROCEEDINGS: CIRCUITS DEVICES AND SYSTEMS, INSTITUTION OF ELECTRICAL ENGINEERS, STEVENAGE, GB, vol. 143, no. 5, 8 October 1996 (1996-10-08), pages 274 - 281, XP006006133, ISSN: 1350-2409, DOI: DOI:10.1049/IP-CDS:19960611
P.R. GRAY ET AL: "A low-noise chopper-stabilized differential switched-capacitor filtering technique", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 16, no. 6, 1 December 1981 (1981-12-01), pages 708 - 715, XP055002080, ISSN: 0018-9200, DOI: 10.1109/JSSC.1981.1051666
Attorney, Agent or Firm:
MOBARHAN, Ramin (5775 Morehouse DriveSan Diego, Califonia, US)
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