TECHNICAL FIELD

The present disclosure relates generally to the field of ultra- wideband amplifiers for optical communication; and more specifically to a distributed amplifier circuit with a tunable peaking feature.

BACKGROUND

Generally, transmitters used for high speed optical communications are implemented by cascading a digital source, a conventional driver amplifier, and an electro-optical modulator. The conventional driver amplifier is typically used to increase a power level of an electrical signal which is generated by the digital source in order to provide an appropriate supply power to the electro-optical modulator. The electro-optical modulator is typically configured to transduce the electrical signal to an optical signal which is transferred via an optical fiber. Typically, the conventional driver amplifier is required to achieve a high frequency peaking in order to compensate high frequency losses introduced by the electro-optical modulator, package, and connection between various components of the electro-optical modulator. Each part of the electro-optical modulator is mathematically modelled, and despite of this, a final real bandwidth of the electro-optical modulator is difficult to predict. Moreover, different electro-optical modulators (or modules) oriented for different applications and transmission standards, require different peaking amplitude and frequency. As a consequence, the conventional driver amplifier with a tunable peaking function is of great interest because the tunable peaking function can be adopted to optimize frequency response with respect to different electro-optical modulators.

Currently, certain solutions have been proposed to design a conventional driver amplifier with a tunable peaking function either by using a variable resistor/capacitor (i.e. R/C) on a differential ground, or a variable resistor (R), inductor (L), and a capacitor (C) (i.e. R/L/C) on a differential output side, or a variable differential feedback, or a variable R/C on differential cascode middle node. The conventional driver amplifier with the tunable peaking function is based on a differential amplifier or a differential variable gain amplifier (VGA). As a result, the conventional driver amplifier can be used only in such cases where the conventional driver amplifier includes a differential VGA. Moreover, implementation of the tunable peaking function on the differential VGA makes the tunable peaking function sensitive to a gain level which is not preferable. Thus, there exists a technical problem of an inefficient driver amplifier that fails to exclude the differential VGA and hence, fails to eliminate the sensitivity of the tunable peaking function to the gain level.

Moreover, electro-optical modulators based on a Lithium Niobate modulator (LiNbO3) usually require that the conventional driver amplifier providing a matched output return loss in order to minimize an impact of multiple reflections which in turn reduces the electrical signal quality. To this purpose, driver amplifiers are usually based on single-ended distributed amplifier. However, solutions for tunable peaking are proposed only for differential schemes. Thus, there exists a technical problem to implement tunable peaking function to single-ended distributed amplifier.

Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional driver amplifier, and the conventional transmitter that uses the conventional driver amplifier.

SUMMARY

The present disclosure provides a driver amplifier with a tunable peaking function implied on a distributed amplifier rather than on a differential VGA. The present disclosure further provides a transmitter that uses the driver amplifier and is suitable for use in an optical communication system for high data-rate applications. The present disclosure provides a solution to the existing problem of an inefficient driver amplifier that fails to exclude a differential VGA and hence, fails to eliminate sensitivity of a tunable peaking function from a gain level. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in prior art, and provide an improved driver amplifier with the tunable peaking function implementable without a differential VGA and hence, supports elimination of sensitivity of the tunable peaking function from a gain level. The improved driver amplifier can be used as an ultra wideband amplifier in the optical communication system for high data-rate applications.

The object of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

In one aspect, the present disclosure provides a distributed amplifier circuit comprising N transistors, N is greater or equal to 1. Each transistor is connected to an input line common to all transistors, so as to allow applying a common input signal to each transistor through the input line. Each transistor is further connected to an output line common to all transistors, so as to allow delivery of an output signal through the output line depending on the output delivered by each transistor. The output line comprises one or more variable resistors.

The distributed amplifier circuit of the present disclosure manifests a tunable peaking function by virtue of comprising the one or more variable resistors in the output line. The distributed amplifier circuit manifests the tunable peaking function without requiring a differential variable gain amplifier (VGA). As a result, the distributed amplifier circuit eliminates the tunable peaking sensitivity to the gain variation. Moreover, the distributed amplifier circuit can be used for different electro-optical modulators such as lithium niobate (LiNbO3) modulator, indium phosphide (InP) mach-zehnder modulator (MZM) and silicon polymer (SiP) mach-zehnder modulator (MZM) because of the tunable peaking function.

In an implementation form, each transistor has a gate, a source and a drain. The source of each transistor is connected to a ground. The gate of each transistor is connected through a corresponding input node to the input line. The drain of each transistor is connected through a corresponding output node to the output line.

Each transistor among the N transistors enables the distributed amplifier circuit to achieve a high gain and a high bandwidth.

In a further implementation form, the output line further comprises N+l output inductors connected in series between a ground and an output. A first output inductor among the N+l output inductors is connected between the ground and the output node of a first transistor among the N transistors. A last output inductor among the N+l output inductors is connected between the output node of a last transistor among the N transistors and an output of the output line. Each of the other N-l output inductors among the N+l output inductors is connected between two output nodes of two transistors among the N transistors.

Each inductor of the N+l output inductors of the output line is used to provide a DC current and voltage to the N transistors.

In a further implementation form, the output line further comprises a resistor connected between one of the output inductors and the corresponding ground.

The resistor of the output line is used for output impedance matching in the distributed amplifier circuit.

In a further implementation form, at least one of the one or more variable resistors is connected between two ends of one output inductor among the N+l output inductors, or between a point located between two ends of a first output inductor among the N+l output inductors and a point located between two ends of a second output inductor adjacent to the first output inductor.

The one or more variable resistors are connected in parallel to the N+l output inductors to enable the tunable peaking function in the distributed amplifier circuit.

In a further implementation form, the output line comprises a plurality of variable resistors. Each of the variable resistors is connected either between two ends of one output inductor among the N+l output inductors or between a point located between two ends of a first output inductor among the N+l output inductors and a point located between two ends of a second output inductor adjacent to the first output inductor.

The plurality of variable resistors of the output line enables the tunable peaking function in the distributed amplifier circuit.

In a further implementation form, one or more of the variable resistors comprises one controllable transistor having a drain and a source connected respectively either to the two ends of the corresponding output inductor or to the point located between the two ends of the corresponding first output inductor and the point located between the two ends of the corresponding second output inductor. The controllable transistor has a gate controllable by a control voltage signal.

It is advantageous to have the one controllable transistor as the variable resistor as it is a simplest way to implement a low pass lossy filter. Further, the resistance offered by the one controllable transistor can be controlled by use of the control voltage signal.

In a further implementation form, two or more of the variable resistors each comprises one controllable transistor having a drain and a source connected respectively either to the two ends of the corresponding output inductor or to the point located between the two ends of the corresponding first output inductor and the point located between the two ends of the corresponding second output inductor. The controllable transistor having a gate controllable by a control voltage signal distinct of the control voltage signal to control the gate of one or more of the other controllable transistors.

It is advantageous to have the two or more controllable transistors as the two or more variable resistors because of simplicity. Further, the two or more controllable transistors are digitally controlled transistors. Each controllable transistor can be controlled by use of the distinct control voltage signal.

In a further implementation form, two or more of the variable resistors each comprises one controllable transistor having a drain and a source connected respectively either to the two ends of the corresponding output inductor or to the point located between the two ends of the corresponding first output inductor and the point located between the two ends of the corresponding second output inductor. The controllable transistor having a gate controllable by a control voltage, two or more of the controllable transistor having their respective gates connected together so as to be controllable by the same control voltage signal.

It is advantageous to have the two or more controllable transistors as the two or more variable resistors because of simplicity. Further, the two or more controllable transistors are digitally controlled transistors and can be controlled by use of the same control voltage signal. In a further implementation form, the input line comprises N+l input inductors connected in series between an input and a ground. A first input inductor among the N+l input inductors is connected between the input of the input line and the input node of a first transistor among the N transistors. A last input inductor among the N+l input inductors is connected between the input node of a last transistor among the N transistors and the ground. Each of the other N-l input inductors among the N+l input inductors is connected between two input nodes of two transistors among the N transistors.

In a further implementation form, the input line further comprises a resistor connected between one of the input inductors and the corresponding ground.

It is advantageous to include the resistor in the input line, to achieve an input impedance matching to the distributed amplifier circuit.

In another aspect, the present disclosure provides a transmitter for optical communication comprising a digital source, the distributed amplifier circuit and an electro-optical modulator. The digital source is connected to the distributed amplifier circuit so as to provide a digital signal to the distributed amplifier circuit. The distributed amplifier circuit is connected to the electro-optical modulator so as to amplify a received digital signal by increasing its power level and to transmit the amplified signal to the electro -optical modulator. The electro-optical modulator is configured to transduce a received amplified signal to an optical signal due to be transferred into an optical communication line.

The transmitter achieves all the advantages and effects of the distributed amplifier circuit of the present disclosure.

It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1 is a block diagram that illustrates various exemplary components of a driver amplifier, in accordance with an embodiment of the present disclosure;

FIG. 2A is a circuit diagram of a distributed amplifier circuit, in accordance with an embodiment of the present disclosure;

FIG. 2B is a circuit diagram of a distributed amplifier circuit, in accordance with another embodiment of the present disclosure; FIG. 2C is a circuit diagram of a distributed amplifier circuit, in accordance with yet another embodiment of the present disclosure;

FIG. 2D is a circuit diagram of a distributed amplifier circuit, in accordance with yet another embodiment of the present disclosure;

FIG. 3 is a circuit diagram of a T-section of the output line (or the output distributed line) of the distributed amplifier circuit, in accordance with an embodiment of the present disclosure;

FIG. 4A is a graphical representation that illustrates an insertion loss of the T-section of the output line, in accordance with an embodiment of the present disclosure;

FIG. 4B is a graphical representation that illustrates an output return loss of the T-section of the output line, in accordance with an embodiment of the present disclosure;

FIG. 5A is a graphical representation that illustrates tuning of a high peaking mode of the distributed amplifier circuit at high frequencies, in accordance with an embodiment of the present disclosure;

FIG. 5B is a graphical representation that illustrates an output return loss of the distributed amplifier circuit, in accordance with an embodiment of the present disclosure; and

FIG. 6 is a block diagram that illustrates various exemplary components of a transmitter, in accordance with an embodiment of the present disclosure.

In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the nonunderlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing. DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible.

FIG. 1 is a block diagram that illustrates various exemplary components of a driver amplifier, in accordance with an embodiment of the present disclosure. With reference to FIG. 1, there is shown a block diagram 100 of a driver amplifier 102. The driver amplifier 102 includes a variable gain amplifier (VGA) 104, and a distributed amplifier 106 with a tunable peaking function 108. The driver amplifier 102 further includes input terminals 110 and an output terminal 112.

The driver amplifier 102 can be used in cases (or applications) where the VGA 104 is not required because the tunable peaking function 108 is directly implied on the distributed amplifier (DA) 106 rather than on the VGA 104. Moreover, the driver amplifier 102 can be used even in such cases (or applications) where the VGA 104 is required without having an impact on efficiency of the driver amplifier 102. Since the tunable peaking function 108 is directly implied on the distributed amplifier (DA) 106, therefore, the driver amplifier 102 removes any sensitivity of the tunable peaking function 108 from a gain level. In this way, the driver amplifier 102 can operate with or without the VGA 104 with an adequate efficiency. An input signal (e.g. a voltage signal or a current signal) is applied to the distributed amplifier 106 through the input terminals 110 and an output is taken from the output terminal 112. A circuit architecture of the distributed amplifier 106 is described in detail, for example, in FIGs. 2A-2D.

FIG. 2A is a circuit diagram of a distributed amplifier circuit, in accordance with an embodiment of the present disclosure. FIG. 2A is described in conjunction with elements from FIG. 1. With reference to FIG. 2A, there is shown a circuit architecture of a distributed amplifier circuit 200A that includes a plurality of transistors 202. The plurality of transistors 202 includes a first transistor 202A (also represented as QI), a second transistor 202B (also represented as Q2) and upto Nth transistor 202N (also represented as Qn). The distributed amplifier circuit 200A further includes an input line 204 and an output line 206. The input line 204 includes an input signal 208 (also represented as Vin), a plurality of input inductors 210, a resistor 212 (also represented as Rg) and a ground 214. The plurality of input inductors 210 includes a first input inductor 210A (also represented as Lgl), a second input inductor 210B (also represented as Lg2), and upto N+lth input inductor 210N1 (also represented as Lg(n+1)). The output line 206 includes a ground 216, a resistor 218 (also represented as Rd), a plurality of output inductors 220, a plurality of variable resistors 222 and an output signal 224 (also represented as Vout). The plurality of output inductors 220 includes a first output inductor 220A (also represented as Ldl), a second output inductor 220B (also represented as Ld2), and upto N+lth output inductor 220N1 (also represented as Ld(n+1)). The plurality of variable resistors 222 includes a first variable resistor 222A (also represented as Rvarl), a second variable resistor 222B (also represented as Rvar2) and upto N+lth variable resistor 222N1 (also represented as Rvar(n+1)). Each of the plurality of transistors 202, the input line 204, the plurality of input inductors 210 and the resistor 212 (i.e. Rg), the output line 206, the resistor 218 (i.e. Rd), the plurality of output inductors 220 and the plurality of variable resistors 222 of the distributed amplifier circuit 200A is represented by a dashed rectangular box, which is used for illustration purpose only and does not form a part of circuitry. The distributed amplifier circuit 200A corresponds to the distributed amplifier (DA) 106 of the driver amplifier 102 (of FIG. 1).

The distributed amplifier circuit 200A comprises N transistors, N being greater or equal to 1. Each transistor is connected to the input line 204 common to all transistors so as to allow applying the input signal 208 to each transistor through the input line 204. Each transistor is further connected to the output line 206 common to all transistors, so as to allow delivery of the output signal 224 through the output line 206 depending on the output delivered by each transistor. The output line 206 comprises one or more variable resistors. The N transistors are referred to as the plurality of transistors 202. The input line 204 as well as the output line 206 is common to each transistor of the plurality of transistors 202. Therefore, the input signal 208 (i.e. Vin) is applied to each transistor of the plurality of transistors 202 through the input line 204 and the output signal 224 (i.e. Vout) is received from the plurality of transistors 202 through the output line 206. The output signal 224 (i.e. Vout) depends on the output delivered by each transistor of the plurality of transistors 202. The one or more variable resistors of the output line 206 correspond to the plurality of variable resistors 222.

In accordance with an embodiment, each transistor has a gate, a source and a drain. The source of each transistor is connected to a ground. The gate of each transistor is connected through a corresponding input node to the input line 204. The drain of each transistor is connected through a corresponding output node to the output line 206. For example, the first transistor 202A (i.e. QI) includes a gate 203A, a source 203B and a drain 203C. The gate 203A of the first transistor 202A (i.e. QI) is connected to the corresponding input node to the input line 204. The source 203B of the first transistor 202A (i.e. QI) is connected to the ground. The drain 203C of the first transistor 202A (i.e. QI) is connected to the corresponding output node to the output line 206. Similarly, the second transistor 202B (i.e. Q2) onwards up to the Nth transistor 202N (i.e. Qn) are connected to the input line 204, the ground and the output line 206 through their respective gate, source and drain terminals.

In accordance with an embodiment, the output line 206 comprises N+l output inductors (i.e. the plurality of output inductors 220) connected in series between the ground 216 and the output 224. The first output inductor 220A among the N+l output inductors 220 is connected between the ground 216 and the output node of the first transistor 202A among the N transistors (i.e. the plurality of transistors 202). The last output inductor 220N1 among the N+l output inductors 220 is connected between the output node of the last transistor 202N among the N transistors 202 and the output 224 of the output line 206. Each of the other N- 1 output inductors among the N+l output inductors 220 is connected between two output nodes of two transistors among the N transistors 202. The N+l output inductors correspond to the plurality of output inductors 220 of the output line 206. The first output inductor 220A (i.e. Ldl) is connected between the ground 216 and the output node of the first transistor 202A (i.e. QI). Similarly, the second output inductor 220B (i.e. Ld2) is connected between the output node of the first transistor 202A (i.e. QI) and the output node of the second transistor 202B (i.e. Q2). The last output inductor 220N1 (i.e. Ld(n+1)) is connected between the output node of the last transistor 202N (i.e. Qn) and the output 224 (i.e. Vout) of the output line 206. In accordance with an embodiment, the output line 206 further comprises the resistor 218 connected between one of the output inductors and the corresponding ground. For example, in this case, the resistor 218 (i.e. Rd) is connected between the ground 216 and the first output inductor 220A (i.e. Ldl) of the plurality of output inductors 220 of the output line 206.

In accordance with an embodiment, at least one of the one or more variable resistors is connected between two ends of one output inductor among the N+l output inductors 220, or between a point located between two ends of the first output inductor 220A among the N+l output inductors 220 and a point located between two ends of the second output inductor 220B adjacent to the first output inductor 220A. For example, in an implementation, at least one resistor (e.g. the first variable resistor 222A (i.e. Rvarl)) of the plurality of variable resistors 222 of the output line 206 is connected between two ends of the one output inductor, such that the first output inductor 220A (i.e. Ldl). In another implementation, the at least one resistor (e.g. the first variable resistor 222A (i.e. Rvarl)) of the plurality of variable resistors 222 of the output line 206 is connected between the point located between two ends of the first output inductor 220A (i.e. Ldl) and the point located between two ends of the second output inductor 220B (i.e. Ld2). The second output inductor 220B (i.e. Ld2) is adjacent to the first output inductor 220A (i.e. Ldl).

In accordance with an embodiment, the output line 206 comprises the plurality of variable resistors 222. Each of the plurality of variable resistors 222 is connected either between two ends of one output inductor among the N+l output inductors 220 or between a point located between two ends of the first output inductor 220A among the N+l output inductors 220 and a point located between two ends of the second output inductor 220B adjacent to the first output inductor 220A. In this implementation, the first variable resistor 222A (i.e. Rvarl) is connected between two ends of one output inductor, such that the first output inductor 220A (i.e. Ldl). The second variable resistor 222B (i.e. Rvar2) is connected between two ends of the second output inductor 220B (i.e. Ld2). Similarly, the N+lth variable resistor 222N1 (i.e. Rvar(n+1)) is connected between two ends of the N+lth output inductor 220N1 (i.e. Ld(n+1)). In another implementation, the first variable resistor 222A (i.e. Rvarl) may be connected between the point located between two ends of the first output inductor 220A (i.e. Ldl) and the point located between two ends of the second output inductor 220B (i.e. Ld2). Similar to the first variable resistor 222A (i.e. Rvarl), the second variable resistor 222B (i.e. Rvar2) may be connected between the point located between two ends of the second output inductor 220B (i.e. Ld2) and a point located between two ends of a third output inductor (e.g. Ld3). In this way, the plurality of variable resistors 222 of the output line 206 are connected in parallel to the plurality of output inductors 220 of the output line 206.

In accordance with an embodiment, the one or more of the variable resistors 222 (i.e. the plurality of variable resistors 222) comprises one controllable transistor having a drain and a source connected respectively either to the two ends of the corresponding output inductor or to the point located between the two ends of the corresponding first output inductor and the point located between the two ends of the corresponding second output inductor. The controllable transistor having a gate controllable by a control voltage signal. For example, in an implementation, the first variable resistor 222A (i.e. Rvarl) of the plurality of variable resistors 222 may be replaced by the one controllable transistor, for example, a first controllable transistor (also represented as Qvarl). The drain and the source of the one controllable transistor (i.e. Qvarl) are connected to the two ends of the corresponding output inductor, such that the first output inductor 220A (i.e. Ldl). In another implementation, the drain and the source of the one controllable transistor (i.e. Qvarl) are connected to the point located between the two ends of the corresponding first output inductor 220A (i.e. Ldl) and the point located between the two ends of the corresponding second output inductor 220B (i.e. Ld2). In both the implementations, the gate of the one controllable transistor (i.e. Qvarl) is controlled by the control voltage signal.

In accordance with an embodiment, two or more of the variable resistors each comprises one controllable transistor having a drain and a source connected respectively either to the two ends of the corresponding output inductor or to the point located between the two ends of the corresponding first output inductor and the point located between the two ends of the corresponding second output inductor. The controllable transistor having a gate controllable by a control voltage signal distinct of the control voltage signal to control the gate of one or more of the other controllable transistors. Each of the two or more resistors of the plurality of variable resistors 222 may be replaced by the one controllable transistor. For example, in an implementation, the dram and the source of the one controllable transistor are connected to the two ends of the corresponding output inductor. An example of such implementation is described in detail, for example, in FIG. 2B. In another implementation, the drain and the source of the one controllable transistor are connected to the point located between the two ends of the corresponding first output inductor and the point located between the two ends of the corresponding second output inductor. An example of such implementation is described in detail, for example, in FIG. 2C. The gate of the one controllable transistor is controlled by the control voltage signal distinct of the control voltage signal to control the gate of one or more of the other controllable transistors, described in detail, for example, in FIG. 2D.

In accordance with an embodiment, two or more of the variable resistors each comprises one controllable transistor having a drain and a source connected respectively either to the two ends of the corresponding output inductor or to the point located between the two ends of the corresponding first output inductor and the point located between the two ends of the corresponding second output inductor. The controllable transistor having a gate controllable by a control voltage, two or more of the controllable transistor having their respective gates connected together so as to be controllable by the same control voltage signal. Each of the two or more resistors of the plurality of variable resistors 222 may be replaced by the one controllable transistor. For example, in an implementation, the drain and the source of the one controllable transistor are connected to the two ends of the corresponding output inductor. An example of such implementation is described in detail, for example, in FIG. 2B. In another implementation, the drain and the source of the one controllable transistor are connected to the point located between the two ends of the corresponding first output inductor and the point located between the two ends of the corresponding second output inductor. An example of such implementation is described in detail, for example, in FIG. 2C. The gate of the one controllable transistor is controlled by the control voltage signal, and the gates of the respective two or more controllable transistors are connected together so as to be controlled by the same control voltage signal, described in detail, for example, in FIGs. 2B and 2C. In accordance with an embodiment, the input line 204 comprises N+l input inductors 210 (i.e. the plurality of input inductors 210) connected in series between the input 208 and the ground 214. The first input inductor 210A among the N+l input inductors 210 is connected between the input 208 of the input line 204 and the input node of the first transistor 202A among the N transistors 202. The last input inductor 210N1 among the N+l input inductors 210 is connected between the input node of the last transistor 202N among the N transistors 202 and the ground 214. Each of the other N-l input inductors among the N+l input inductors 210 is connected between two input nodes of two transistors among the N transistors 202. The N+l input inductors are also referred to as the plurality of input inductors 210 of the input line 204. The first input inductor 210A (i.e. Lgl) is connected between the input 208 and the input node of the first transistor 202A (i.e. QI). Similarly, the second input inductor 210B (i.e. Lg2) is connected between the input node of the first transistor 202A (i.e. QI) and the input node of the second transistor 202B (i.e. Q2). The last input inductor 210N1 (i.e. Lg(n+1)) is connected between the input node of the last transistor 202N (i.e. Qn) and ground 214.

In accordance with an embodiment, the input line 204 further comprises the resistor 212 connected between one of the input inductors and the corresponding ground. For example, in this case, the resistor 212 (i.e. Rg) is connected between the last input inductor 210N1 (i.e. Lg(n+1)) of the plurality of input inductors 210, and the ground 214.

Typically, a transistor and two inductors in an input line and two inductors in an output line is considered as a distributed amplifier. However, in the distributed amplifier circuit 200A, a cascaded distributed amplifer is used to achieve a high gain and a high bandwidth. For example, the first transistor 202A and the first input inductor 210A and the second input inductor 210B of the input line 204 and the first output inductor 220A and the second output inductor 220B of the output line 206 makes a distributed amplifer and this is repeated upto the Nth transistor 202N and the N+lth input inductor 210N1 of the input line 204 and the N+lth output inductor 220N1 of the output line 206 to obtain the cascaded distributed amplifer. Thus, the distributed amplifier circuit 200A implements the tunable peaking function 108 (of FIG. 1) because of the presence of the plurality of variable resistors 222 in the output line 206. The distributed amplifier circuit 200A enables the tunable peaking function 108 without the requirement of the VGA 104 (or the differential VGA), as a result, the distributed amplifier circuit 200A reduces the tunable peaking sensitivity to the gain variation. Moreover, the presence of the plurality of variable resistors 222 in the output line 206 does not affect other performance parameters of the distributed amplifier circuit 200A such as power consumption, bandwidth, gain, output and input return loss, linearity, design complexity, biasing methods, and the like. The distributed amplifier circuit 200A manifests a high gain and a high bandwidth suitable for high date rate optical communication. The distributed amplifier circuit 200A may be used in the driver amplifier 102 (of FIG. 1) that can be further used in different electro-optical modulators such as lithium niobate (LiNbO3) modulator, indium phosphide (InP) mach-zehnder modulator (MZM) and silicon polymer (SiP) mach-zehnder modulator (MZM).

FIG. 2B is a circuit diagram of a distributed amplifier circuit, in accordance with another embodiment of the present disclosure. FIG. 2B is described in conjunction with elements from FIGs. 1, and 2A. With reference to FIG. 2B, there is shown a circuit architecture of a distributed amplifier circuit 200B that includes a plurality of controllable transistors 226 controlled by a control voltage signal 228 (also represented as VT). The plurality of controllable transistors 226 includes a first controllable transistor 226A (also represented as Qvarl), a second controllable transistor 226B (also represented as Qvar2) and upto N+lth controllable transistor 226N1 (also represented as Qvar(n+1)). Each controllable transistor of the plurality of controllable transistors 226 is represented by a dashed rectangular box, which is used for illustration purpose only and do not form a part of circuitry.

The distributed amplifier circuit 200B corresponds to the distributed amplifier circuit 200A (of FIG. 2A) except the plurality of controllable transistors 226 and the control voltage signal 228 (i.e. VT). In the distributed amplifier circuit 200B, the plurality of variable resistors 222 of the distributed amplifier circuit 200A are realized by the plurality of controllable transistors 226. Each controllable transistor of the plurality of controllable transistors 226 is controlled by the control voltage signal 228 (i.e. VT). Each controllable transistor of the plurality of controllable transistors 226 has a drain and a source connected respectively to the two ends of the corresponding output inductor. Alternatively stated, each controllable transistor of the plurality of controllable transistors 226 has a drain and a source connected respectively to the edges of the corresponding output inductor. For example, the drain and the source of the first controllable transistor 226A (i.e. Qvarl) are connected to the two ends of the first output inductor 220A (i.e. Ldl). Similarly, the drain and the source of the second controllable transistor 226B (i.e. Qvar2) and the N+lth controllable transistor 226N1 (i.e. Qvar(n+1)) are connected to the two ends of the second output inductor 220B (i.e. Ld2) and the N+lth output inductor 220N1 (i.e. Ld(n+1)), respectively. Moreover, each controllable transistor of the plurality of controllable transistors 226 has a gate controllable by the control voltage signal 228 (i.e. VT). The gate of each controllable transistor of the plurality of controllable transistors 226 is connected together so as to be controlled by the same control voltage signal 228 (i.e. VT).

FIG. 2C is a circuit diagram of a distributed amplifier circuit, in accordance with yet another embodiment of the present disclosure. FIG. 2C is described in conjunction with elements from FIGs. 1, 2A, and 2B. With reference to FIG. 2C, there is shown a circuit architecture of a distributed amplifier circuit 200C.

The distributed amplifier circuit 200C corresponds to the distributed amplifier circuit 200B (of FIG. 2B) except the connections between the plurality of controllable transistors 226 and the plurality of output inductors 220 of the output line 206. In the distributed amplifier circuit 200C, the drain and the source of each controllable transistor of the plurality of controllable transistors 226 are connected to a point located between the two ends of the corresponding first output inductor and a point located between the two ends of the corresponding second output inductor rather to the edges of the corresponding output inductor. For example, the drain and the source of the first controllable transistor 226A (i.e. Qvarl) are connected to the point located between the two ends of the first output inductor 220A (i.e. Ldl) and the point located between the two ends of the second output inductor 220B (i.e. Ld2). Similarly, the drain and the source of the second controllable transistor 226B (i.e. Qvar2) are connected to the point located between the two ends of the second output inductor 220B (i.e. Ld2) and the point located between the two ends of the third output inductor 220C (i.e. Ld3). Similarly, the drain and the source of the N+lth controllable transistor 226N1 (i.e. Qvar(n+1)) are connected to the point located between the two ends of the Nth output inductor (e.g. Ldn) and the point located between the two ends of the N+lth output inductor 220N1 (i.e. Ld(n+1)). Moreover, the gate of each controllable transistor of the plurality of controllable transistors 226 is connected together so as to be controlled by the same control voltage signal 228 (i.e. VT).

FIG. 2D is a circuit diagram of a distributed amplifier circuit, in accordance with yet another embodiment of the present disclosure. FIG. 2D is described in conjunction with elements from FIGs. 1, 2A, 2B, and 2C. With reference to FIG. 2D, there is shown a circuit architecture of a distributed amplifier circuit 200D that includes a plurality of control voltage signals. The plurality of control voltage signals includes a first control voltage signal 230A (also represented as VT1), a second control voltage signal 230B (also represented as VT2), and upto N+lth control voltage signal 230N1 (also represented as VT(n+l)).

The distributed amplifier circuit 200D corresponds to the distributed amplifier circuit 200B (of FIG. 2B) except the plurality of control voltage signals. In the distributed amplifier circuit 200D, the drain and the source of each controllable transistor of the plurality of controllable transistors 226 are connected respectively to the two ends of the corresponding output inductor. Moreover, the gate of each controllable transistor of the plurality of controllable transistors 226 is digitally controlled using each control voltage signal of the plurality of control voltage signals. For example, the gate of the first controllable transistor 226A (i.e. Qvarl) is controlled by the first control voltage signal 230A (i.e. VT1). Similarly, the gate of the second controllable transistor 226B (i.e. Qvar2) and the N+lth controllable transistor 226N1 (i.e. Qvar(n+1)) is controlled by the second control voltage signal 230B (i.e. VT2) and the N+lth control voltage signal 230N1 (i.e VT(n+l)), respectively.

Typically, different electro-optical modulators, for example, lithum niobate modulator (LiNbO3), indium phosphide mach zehnder modulator (InP-MZM), and silicon photonic mach zehnder modulator (SiP-MZM) require different peaking level at different frequencies. The distributed amplifier circuits 200A-200D of the present disclosure simultaneously supports different electro-optical modulators by providing tunable peaking at different frequencies. The distributed amplifier circuits 200A-200D of the present disclosure also facilitate optimization of a final module frequency response owing to tunable peaking, that enables usability of the distributed amplifier circuits 200A-200D with different platforms and modules.

FIG. 3 is a circuit diagram of a T-section of the output line (or the output distributed line) of the distributed amplifier circuit, in accordance with an embodiment of the present disclosure. FIG. 3 is described in conjunction with elements from FIGs. 1, 2A, 2B, 2C, and 2D. With reference to FIG. 3, there is shown a circuit architecture of a T-section 300 of the output line 206 of the distributed amplifier circuit 200A (of FIG. 2A). The T-section 300 of the output line 206 includes a first output inductor 302A (also represented as Ld) and a second output inductor 302B (also represented as Ld). The T-section 300 of the output line 206 further includes a first variable resistor 304A (also represented as Rvar) and a second variable resistor 304B (also represented as Rvar). The T-section 300 of the output line 206 further includes a capacitor 306 and a ground 308.

In the T-section 300, the first output inductor 302A (i.e. Ld) and the second output inductor 302B (i.e. Ld) may have same value (e.g. 159 pH). Additionally, the first output inductor 302A (i.e. Ld) and the second output inductor 302B (i.e. Ld) corresponds to an inductor of the plurality of output inductors 220 of the output line 206 of the distributed amplifier circuit 200A (of FIG. 2A). Similarly, the first variable resistor 304A (i.e. Rvar) and the second variable resistor 304B (i.e. Rvar) may have the same value. Moreover, the first variable resistor 304A (i.e. Rvar) and the second variable resistor 304B (i.e. Rvar) corresponds to a variable resistor of the plurality of variable resistors 222 of the output line 206 of the distributed amplifier circuit 200A (of FIG. 2A). The capacitor 306 represents an output parasitic capacitance of the transistor among the plurality of transistors 202 of the distributed amplifier circuit 200A (of FIG. 2A). The capacitor 306 is connected to the ground 308 to maintain a reference (e.g. a reference voltage or a reference current) throughout the T-section 300 of the output line 206 of the distributed amplifier circuit 200A (of FIG. 2A).

The T-section 300 of the output line 206 of the distributed amplifier circuit 200A (of FIG. 2A) is analysed in detail, for example, in FIGs. 4A and 4B, respectively. FIG. 4A is a graphical representation that illustrates an insertion loss of the T-section of the output line, in accordance with an embodiment of the present disclosure. FIG. 4A is described in conjunction with elements from FIGs. 1, 2A-2D, and 3. With reference to FIG. 4A, there is shown a graphical representation 400A that illustrates a simulated insertion loss of the T-section 300 of the output line 206 of the distributed amplifier circuit 200A (of FIG. 2A) for different values of the variable resistor (i.e. Rvar) of the T-section 300. The graphical representation 400A includes an X-axis 402A that represents frequency in gigahertz (GHz) and a Y-axis 402B that represents the simulated insertion loss in decibels (also represented as dB(S(2, 1 ))) of the T-section 300 (of FIG. 3).

In the graphical representation 400A, a first line 404A represents a variation of the simulated insertion loss in dB with respect to a variation in the frequency from 0GHz-70GHz and with the variable resistor (i.e. Rvar) of value 1.000E7 ohms (or 10 Megaohms (MO)). A second line 404B represents a variation of the simulated insertion loss in dB with respect to a variation in the frequency from 0GHz-70GHz and with the variable resistor (i.e. Rvar) of value 800 Q. A third line 404C represents a variation of the simulated insertion loss in dB with respect to a variation in the frequency from 0GHz-70GHz and with the variable resistor (i.e. Rvar) of value 400 Q. A fourth line 404D represents a variation of the simulated insertion loss in dB with respect to a variation in the frequency from 0GHz-70GHz and with the variable resistor (i.e. Rvar) of value 200 Q. A fifth line 404E represents a variation of the simulated insertion loss in dB with respect to a variation in the frequency from 0GHz- 70GHz and with the variable resistor (i.e. Rvar) of value 100 Q. A sixth line 406 represents that at a frequency of 50GHz, the simulated insertion loss of the T-section 300 of the output line 206 increases (e.g. from -3.436dB to -O.OOOdB) as the value of the variable resistor (i.e. Rvar) decreases (e.g. from 10MQ to 100 Q), hence realizing the tunable peaking function 108 in the distributed amplifier 106 (of FIG. 1) and the distributed amplifier circuits 200A- 200D (of FIGs. 2A-2D).

FIG. 4B is a graphical representation that illustrates an output return loss of the T-section of the output line, in accordance with an embodiment of the present disclosure. FIG. 4B is described in conjunction with elements from FIGs. 1, 2A-2D, 3, and 4A. With reference to FIG. 4B, there is shown a graphical representation 400B that illustrates a simulated output return loss (or characteristic impedance) of the T-section 300 of the output line 206 of the distributed amplifier circuit 200A (of FIG. 2A) for different values of the variable resistor (i.e. Rvar) of the T-section 300. The graphical representation 400B includes an X-axis 408A that represents frequency in gigahertz (GHz) and a Y-axis 408B that represents the simulated output return loss in decibels (also represented as dB(S(l,l))) of the T-section 300 (of FIG. 3).

In the graphical representation 400B, a first line 410A represents the simulated output return loss in dB at the variable resistor (i.e. Rvar) of value 10 MQ. A second line 410B represents the simulated output return loss in dB at the variable resistor (i.e. Rvar) of value 800 Q. A third line 410C represents the simulated output return loss in dB at the variable resistor (i.e. Rvar) of value 400 Q. A fourth line 410D represents the simulated output return loss in dB at the variable resistor (i.e. Rvar) of value 200 Q. A fifth line 410E represents the simulated output return loss in dB at the variable resistor (i.e. Rvar) of value 100 Q. The graphical representation 400B illustrates that the simulated output return loss of the T-section 300 of the output line 206 is not affected (or degraded) by changing the value of the variable resistor (i.e. Rvar) which indicates a capability of the T-section 300 to maintain a matched output return loss whatever peaking level is required. This means that the distributed amplifier 106 (of FIG. 1) and the distributed amplifier circuits 200A-200D (of FIGs. 2A-2D) manifest the capability of maintaining the matched output return loss in different applications where different peaking level is required.

FIG. 5A is a graphical representation that illustrates tuning of a high peaking mode of the distributed amplifier circuit at high frequencies, in accordance with an embodiment of the present disclosure. FIG. 5A is described in conjunction with elements from FIGs. 1, 2A-2D, 3, 4A, and 4B. With reference to FIG. 5 A, there is shown a graphical representation 500A that illustrates tuning of the high peaking mode of the distributed amplifier circuits 200A- 200D (of FIGs. 2A-2D) at high frequencies. The graphical representation 500A includes an X-axis 502A that represents frequency in gigahertz (GHz) and a Y-axis 502B that represents a normalized insertion loss in decibels (i.e. dB(S(2, 1))) of the distributed amplifier circuits 200A-200D (of FIGs. 2A-2D). In the graphical representation 500A, a first line 504A represents a high peaking mode of the distributed amplifier circuits 200A-200D. A second line 504B represents a low peaking mode of the distributed amplifier circuits 200A-200D. The graphical representation 500A illustrates that the high peaking mode of the distributed amplifier circuits 200A-200D is tuned with the low peaking mode at high frequencies.

FIG. 5B is a graphical representation that illustrates an output return loss of the distributed amplifier circuit, in accordance with an embodiment of the present disclosure. FIG. 5B is described in conjunction with elements from FIGs. 1, 2A-2D, 3, 4A, 4B, and 5A. With reference to FIG. 5B, there is shown a graphical representation 500B that illustrates an output return loss of the distributed amplifier circuits 200A-200D (of FIGs. 2A-2D). The graphical representation 500B includes an X-axis 506A that represents frequency in gigahertz (GHz) and a Y-axis 506B that represents the output return loss in decibels of the distributed amplifier circuits 200A-200D (of FIGs. 2A-2D).

In the graphical representation 500B, a first line 508A represents an output return loss of the distributed amplifier circuits 200A-200D in the high peaking mode. A second line 508B represents an output return loss of the distributed amplifier circuits 200A-200D in the low peaking mode. The graphical representation 500B illustrates that the output return loss of the distributed amplifier circuits 200A-200D in the high peaking mode is approximately similar to the output return loss in the low peaking mode. Moreover, the graphical representations 500A and 500B collectively illustrate that the high peaking mode of the distributed amplifier circuits 200A-200D is tuned without affecting the output return loss of the distributed amplifier circuits 200A-200D.

FIG. 6 is a block diagram that illustrates various exemplary components of a transmitter, in accordance with an embodiment of the present disclosure. FIG. 6 is described in conjunction with elements from FIGs. 1, and 2A-2D. With reference to FIG. 6, there is shown a block diagram of a transmitter 600 that includes a digital source 602, a driver amplifier 604, and an electro-optical modulator 606. There is further shown a digital signal 608, an amplified digital signal 610 and a direct current (DC) voltage source 612. The transmitter 600 includes suitable logic, circuitry, and/or interfaces that is configured to have a transmit path comprising the driver amplifier 604. The driver amplifier 604 corresponds to the driver amplifier 102 (of FIG. 1) that is configured to compose either the distributed amplifier 106 with the tunable peaking function 108 (of FIG. 1) or one of the distributed amplifier circuits 200A-200D (of FIGs. 2A-2D). Thus, all the operations executed by the driver amplifier 604 are part of the operations executed by the transmitter 600. The transmitter 600 may also be referred to as a transmitting device or a transmitter circuit. Examples of the transmitter 600 includes, but is not limited to, a 64G optical transmitter, a broad band monolithic integrated circuit, a broad band driver amplifier, a customized hardware for the high data rate optical communication system, or any other portable or non-portable optical device.

The digital source 602 includes suitable logic, circuitry, and/or interfaces that is configured for signal generation. The digital source 602 is used to generate the digital signal 608. Examples of the digital source 602 includes, but is not limited to, an arbitrary waveform generator, a digitizer, a digital waveform generator and the like.

The driver amplifier 604 includes suitable logic, circuitry, and/or interfaces that is configured to amplify the received digital signal 608 and to generate the amplified digital signal 610 by increasing power level of the received digital signal 608. The driver amplifier 604 is further configured to transmit the amplified digital signal 610 to the electro-optical modulator 606 in order to drive the electro-optical modulator 606. The driver amplifier 604 is configured to support a 64G optical transmitter based on a lithium niobate (LiNbO3) electro-optical modulator.

The electro-optical modulator 606 includes suitable logic, circuitry, and/or interfaces that is configured to transduce the amplified digital signal 610 to an optical signal to be transferred through an optical communication line (or an optical fiber). Examples of the electro-optical modulator 606 includes, but is not limited to an amplitude modulator, phase modulator, polarization modulator, spatial light modulator, lithium niobate modulator (LiNbO3), indium phosphide mach zehnder modulator (InP-MZM ), and silicon photonic mach zehnder (SiP-MZM) modulator and many alike. In the transmit path of the transmitter 600, the driver amplifier 604 acts as an ultra wideband amplifier. The driver amplifier 604 operates in collaboration with the digital source 602 and provides a collective amplification gain that is required to drive the electro-optical modulator 606. The driver amplifier 604 includes one of the distributed amplifier circuits 200A-200D (of FIGs. 2A-2D) that manifests the tunable peaking function 108 (of FIG. 1). Therefore, the driver amplifier 604 can be tuned to different electro -optic al modulators on requirement basis.

Thus, the transmitter 600 provides a high bandwidth and a high amplification gain required for a high data rate optical communication system by use of the driver amplifier 604. The requirement of wide bandwidth is fulfilled by the driver amplifier 604 in the transmitter 600. The transmitter 600 has a high amplification gain that is required to drive the electro-optical modulator 606 because of the driver amplifier 604.

Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the present disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.