RUTH, Robert Scott (6202 Old Harbor Lane, Austin, TX, 78739, US)
FREESCALE SEMICONDUCTOR, INC. (6501 William Cannon Drive West, Austin, 78735, US)
ZECRI, Michel (27 Impasse Dumurier, Bevenais, Bevenais, F-38690, FR)
RUTH, Robert Scott (6202 Old Harbor Lane, Austin, TX, 78739, US)
| CLAIMS:
1. Electronic device (400) having integrated circuitry, the integrated circuitry comprising: a first conductive path (GND), a second conductive path (GNDE), - protection circuitry coupled between the first and the second conductive path to prevent excess voltage or excess current on the first and the second conductive path, the protection circuitry comprising:
- a plurality of diode elements (8, 9), the diode elements (8, 9) being arranged at least partially along the first and the second conductive paths (GND, GNDE) in a continuous distributed manner.
2. Electronic device according to claim 1, wherein the diode elements (8, 9) are implemented in a region outside of the pad cells (20), between the pad cells (20, 21) and a sealing (100) of the electronic device (400).
3. Electronic device according to claim 2, wherein the second conductive path (GNDE) is at least partially implemented by a layer of the sealing (100).
4. Electronic device according to claim 3, wherein the second conductive path (GNDE) is adapted to serve as an internal ESD rail being not connected to substrate.
5. Electronic device according to claim 3, wherein the diode elements (8, 9) are disposed in a separate Nwell or Pwell.
6. Electronic device according to claim 1, wherein the diode elements (8, 9) are distributed in a specific relation to a possible entry point of an ESD event, such that an impedance of the entry point of the ESD event is reduced.
7. Method of designing an electronic device comprising the steps of: providing a first conductive path (GND), providing a second conductive path (GND) providing a plurality of diode elements (8, 9) at least partially along the first and the second conductive path (GND, GNDE) in a continuous distributed manner, and coupling the diode elements (8, 9) to the first and second conductive path in order to prevent excess voltage or excess current on the first and the second conductive path.
8. Data processing system comprising an electronic device according to one of claims 1 to 6. |
FIELD OF THE INVENTION
The present invention relates to protection circuitry for electronic devices, more specifically to distributed electrostatic discharge protection.
BACKGROUND OF THE INVENTION
It is generally known in the art that integrated devices, as for example integrated transistors, risk to be destroyed by Electrostatic Discharge (ESD). An integrated circuit may be subject to ESD during manufacturing, assembly or in the final application. This is due to the extremely small dimensions of the integrated structures, where even small charges generate strong electrical fields. For example, the gate oxides of the metal oxide silicon transistors field effect transistors (MOSFET) may not withstand such electrical fields. Therefore, it is necessary to provide ESD protection circuits for the integrated semiconductor devices on a semiconductor die in order to protect the internal devices from damage. Typically, the die consists of a core containing the integrated electronic components and input/output pads (I/O-pads), power supply pads, and ground pads. The pads are coupled via bonding wires to the lead frame, the pins of which are connected to a printed circuit board or the like. The pads are arranged close to the edges of the die, thereby surrounding the core. Along with the pads there are power rails (also known as power or supply rings) routed at least partially around the periphery of the integrated circuit, consisting of large paths of conductive material and providing supply voltages and ground voltages for the pads and for the active devices on the core. The ESD protection circuits are provided in the pads between I/O signals, ground rails and supply rails. The typical means to avoid excess voltages induced by ESD is a diode to provide an electrically conductive path between a positive and a negative potential on the rails if an excess voltage is reached, thereby allowing to discharge the electrical wires.
Usually, there are a number of different types of pads, each of which provides a particular functionality that is typically needed for integrated circuits. The pads include for example buffers, or drivers, and the necessary protective structures and components. Since an a single pad is usually coupled to only one external pin, the protection circuitry included in
the pad is conceived to meet the requirements of a single specific pin. Usually, the power ring includes more than one ground rail and more than one supply rail. Two ground rails can be beneficial for system on chip devices (SOC), as these devices include a large amount of digital circuitry, in particular digital I/O buffers, which create a considerable amount of noise (voltages and currents) on the associated power rails. Different rails are connected by protective back-to-back diodes in order to allow ESD currents to flow in both directions between two rails.
The discharging currents have to propagate from their point of origin to the diodes over the rails. Since the rails, as all conductive paths in an integrated circuit, provide a specific electrical sheet resistance, the ESD currents propagating through the ground rails can produce significant voltages at their point of origin. The voltage level experienced at certain locations on the supply rails depends on the distance from the ESD protection diodes, the electrical sheet resistance of the rails, and the amount of charge that is produced at the entry point. A typical value can be in the order of 5 volts at 3.8 ampere peak current (according to 200 V MM = ESD discharge machine model). Accordingly, conventional solutions still exhibit to much excess voltage on the respective conductive paths.
Another drawback of the conventional solution relates to the area consumed by the protective diodes. In order to cope with the considerable high currents due to summing effects of a large amount of digital I/O pads, the back-to-back diodes must provide sufficient area to handle these currents. The back-to-back diodes can consume about 5 to 10 % of the layout area of a cell.
Still another drawback of the prior art solutions relates to the susceptibility of the diodes to couple noise to the substrate. Although the back-to-back diodes are usually suitable to efficiently blocking the noise that propagates into the substrate for low frequencies and low amplitudes, the capacitances of the diode junctions provide good coupling for high frequency noise signals. If the common ground rail is connected to the substrate, and each other ground rail is connected to the common ground rail by the protective ESD diodes, the substrate will be the final recipient of the overall noise of the design.
Some conventional ESD protection schemes provide of a plurality of MOSFET transistors serving as shunting devices in almost all I/O pads. Along with the I/O pads, the MOSFET transistors are distributed around the semiconductor device and connected to the respective rails to be ESD protected. The MOSFETs are opened in response to a trigger signal that indicates an ESD event on the rails. However, this concept needs
complex additional circuitry and wiring and provides only a protection of the supply rails with respect to the ground rails.
SUMMARY OF THE INVENTION It is an object of the invention to provide an electronic device having ESD protective circuitry that overcomes the drawbacks of the conventional solutions. The object is solved by subject-matter of the independent claim 1. Accordingly, an electronic device is presented that includes a first conductive path for a first supply voltage or a first ground and a second conductive path for a second supply voltage or a second ground. Between the two conductive paths, there is a protective circuitry. The protective circuitry is coupled between the first and the second path in order to prevent excess voltage or excess currents, i.e. the circuitry protects the conductive paths against ESD events in the first and the second paths. The protection circuitry comprises diode elements, which are arranged at least partially along the first and the second path in a continuous and distributed manner. The conductive paths are preferably the ground or power rails of an integrated electronic circuit. They usually consist of a metal, like aluminium. During manufacturing or during normal operation of these devices, there are numerous situations where protection against excess voltage or excess current on these conductive rails is necessary. Conventional solutions do not provide sufficient and effective ESD protection, as back-to-back diodes are lumped together and located in only some of the I/O pads or power pads. The diode elements according to the present invention have the functionality of diodes and provide a conductive path in one direction. The active areas may be dimensioned and arranged in any manner, as long as a diode like electrical behaviour between the two conductive paths is established. The diode elements are arranged and coupled to the conductive paths such that they provide a specific low impedance for a noise voltage or a noise current (ESD event) propagating on one of the two conductive paths with respect to the other. A back-to-back configuration of the diode elements is one preferred arrangement. In the context of the present invention, the distributed and continuous manner of arranging the diode elements means that, numerous of the diode elements are located side by side close to each other or at least in a specific small distance from each other. The diode elements are coupled in parallel to the conductive paths such that their common impedance is reduced. However, the distance between two adjacent diode elements may vary, as far as the required small impedance with respect to the entry points of ESD events on the conductive paths is preserved. As a result of the distributed and continuous manner of arranging diode elements along the conductive path (e.g. the ground
rails), it is possible to provide a more efficient protection along the length of a power or ground rail. The present invention is particularly suitable to protect the numerous ground rails of an integrated circuit with respect to each other. Some of the conventional protection circuits were only conceived to protect power rails and ground rails with respect to each other. However, the present invention particularly aims to protect against over voltage on plural ground rails. Further, the present invention uses only diode elements, that need no trigger to provide a conductive path. The implementation of diode elements is often simpler than realizing transistors. Further diodes are more robust than transistors. This reduces complexity and improves reliability of the protection circuits with respect to conventional transistor based circuits.
According to an embodiment of the present invention, the diode elements are implemented in the region outside of the pad ring, between the pad ring and the sealing of a chip. Accordingly, the diode elements are implemented in an area that is usually not used for active electronic components. Further, as the diode elements have a greater distance to the active components on the core of the ship, the noise coupled through the diodes into the substrate propagating from the diode elements to the active elements on the core, will be reduced.
According to another embodiment of the present invention, the second path is at least partially implemented in the area of the seal ring. The seal ring seals the chip against humidity and other external influences. The seal ring is typically a wide path composed of a large number of all available layers of the respective technology used for chip manufacturing. According to this aspect of the invention, the seal ring or at least parts of it, as for example a specific layer or portions of a specific layer can be used as a common ground rail. If this ground rail is directly contacted to the lead frame, the noise coupled to the substrate can be considerably reduced. The contact between the lead frame and the seal ring can be established without additional bonding wires, but by conductive adhesives or the like. Usually, the several conductive layers of the seal ring are connected to each other. Therefore, it is a special aspect of the present invention to decouple at least one metal layer of the seal ring, and to use this particular layer as a common ground rail for the present invention. If the diode elements are coupled to a so decoupled conductive layer of the seal ring, this will provide an efficient means to avoid the noise propagating into the substrate.
According to another embodiment of the invention, the diode elements are implemented in a separate Pwell or Nwell. Most technologies provide typically isolated Pwells. The possibilities for providing separate Nwells or Pwells depend on the technology.
Some chip manufacturing processes provide buried layers like for example deep Nwell. If a deep Nwell is located below a Pwell such that it encloses the Pwell, the Pwell is to a certain extent electrically isolated from the P substrate. Such a measure provides additional noise reduction regarding substrate noise. However, dependent on the processes used to manufacture a semiconductor device there might be additional layers or means to effectively decouple the diodes from the substrate.
It should be mentioned that the above aspects of the invention each make their own individual contribution to the invention and should therefore be considered to solve the object individually. Further, any combination of the above aspects of the invention lies within the scope of the present application. Accordingly, it is beneficial to arrange the diode elements in a distributed manner along the power or ground rails of an integrated circuit, it is also advantageous to use the seal ring or parts of it as a separate independent common ground rail. Accordingly, implementing the diode elements in the area between the ground rails and the seal ring and decoupling these elements by additional buried layers or other kinds of isolation have their own merits for the present invention.
In an embodiment of the invention the active areas of the diode elements are oriented such that the diodes are oriented along the power and ground rails. Accordingly, the anode and cathode areas of each diode of the back-to-back diode pairs can substantially be on the same line that is parallel to the ground or power rails to be protected by the diode elements. According to this arrangement, an efficient coupling of the diode elements by metal paths protruding from the power or ground rails in the active diode areas is possible.
In another embodiment of the invention the diode elements are implemented in an alternating manner along the ground or power rails. In order to simplify the design, it is practical to provide one diode element that allows a current from the first ground rail to the second ground rail and next to the first diode element a second diode element that provides a current from the second ground rail to the first ground rail. Such a systematic approach simplifies the applicability and allows uncomplicated extension of the diode element areas.
In a further embodiment of the present invention the diode elements are distributed in a specific relation to a possible entry point of an ESD event, such that an impedance of the entry point of the ESD event is reduced. So, according to the present invention, the number, dimensions and locations of the diode elements is defined upon the respective impedance that is needed on a potential entry point for an ESD event.
The object is also solved by a method of designing an integrated circuit. Accordingly, the method includes several steps of providing a first conductive path, and a
second conductive path for the design of an integrated circuit. Further, in the design procedure, diode elements are arranged along the two conductive paths in a distributed and continuous manner. The diode elements are connected to the first and the second conductive path, respectively, in order to protect the two paths against over current or over voltage during a manufacturing step or during operation. It is particularly useful to provide the diode elements between two ground rails of the integrated design. One of the ground rails may be implemented in the seal ring of an integrated circuit as described above. It is therefore also an aspect of the invention to provide connections between the diode elements and the seal ring, such that the seal ring can be used as a common ground rail for the whole integrated circuit or at least for parts of it.
The object is further solved by a data processing system including an electronic according to the present invention having the properties as set out here above.
BRIEF DESCRIPTION OF THE DRAWINGS These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. In the following drawings:
Fig. 1 shows a simplified schematic of a typical I/O pad and power supply pad arrangement according to an embodiment of the prior art,
Fig. 2 shows a simplified schematic of a typical I/O pad and power supply pad arrangement according to an embodiment of the present invention,
Fig. 3 shows a simplified layout of a pad cell according to the prior art, Fig. 4 shows a simplified top view on a layout of an integrated circuit according to an embodiment of the present invention, Fig. 5 shows a section of Fig. 3 in more detail, Fig. 6 shows a section of Fig. 4 in more detail,
Fig. 7 shows a cross sectional view along the line A-A' of Fig. 5,
Fig. 8 shows a cross sectional view along the line B-B' of Fig. 5,
Fig. 9 shows a simplified schematic illustrating the distributed impedances according to the present invention compared to a prior art configuration, and Fig. 10 shows simulated curves of a comparison between distributed and prior art impedances.
DETAILED DESCRIPTION OF EMBODIMENTS
Fig. 1 is a simplified representation that takes account of aspects relating to a schematic, and also aspects relating to the physical layout of the pads. Although represented by their schematic symbols, the components in the pads are rather arranged following the layout. Fig. 1 shows I/O pad cells 20 for providing input and output signals to an integrated circuit and a power supply pad cell 21 used for supplying the supply voltage to an integrated circuit. The respective input and output signals are coupled to pads 7 (e.g. by bonding wires), and the supply voltage VDDE is supposed to be coupled to pad 6 of pad cell 21 during operation. However, the circuitry shown in Fig.1 serves to protect the devices coupled to VDDE also in the case when no supply voltage is applied to pad 6. The pads are connected to a boost line 31, a trigger line 32 and the power rail at the supply voltage VDDE. The boost line 31 is coupled to transient detection circuit 35 which can be an RC element, consisting of a resistor and a capacitor. Further, there are several diodes 4 in the pads or pad cells 20, 21. Also contained in the pad cells are the MOSFETs 5. The gates of these transistors are coupled the trigger line 32. Each of the MOSFETs 5 provides a direct current path between VDDE and GNDE in response to a trigger signal on the trigger line. The arrangement shown in Fig.l aims to protect the devices coupled to VDDE from ESD events coupled to any of the pads 7. If pad 7 experiences a positive 3.8 A peak current ESD event with respect to GNDE, the voltage at pad 7 may temporarily raise to about 8 V or more. This corresponds to a short pulse according to the 200 V Machine Model being an ESD discharge model known by the skilled artisan. According to this model there is a 4 A peak current of 40 ns duration applied to the pad. One of the diodes 4 permits the current to propagate onto the power rail VDDE and then along VDDE in both directions to the other pad cells 20, 21. Another diode 4 permits the voltage to propagate to boost wire 31 and via boost wire 31 to transient detector circuit 35. The boost wire 31 and the power rail VDDE are dimensioned such that the voltage drop across the boost wire (or boost bus) 31 is much smaller than the voltage drop along the power rail VDDE. The transient detection circuit 35 will then provide a trigger signal over the trigger line 32 in order to activate MOSFETs 5. The clamp MOSFETS 5 provide a current path between VDDE and GNDE in response to the trigger signal, thereby suppressing the ESD event. However, the prior art configuration explained here before with respect to Fig.
1 fails to provide suitable means to avoid excess voltage on the GNDE rail. When the clamp MOSFETs are triggered certain noise signal is introduced on ground rail GNDE. The pad cell 21 provides back-to-back diodes 1 and 2 as an electrical path to discharge the GNDE and the GND power rails with respect to each other. The power rails GNDE and GND are further
represented by incremental sheet resistors 3 of the ground rails GND and GNDE. Due to the resistors 3 in the path of the currents propagating over the ground rails GNDE and GND, the voltage the entry points of the ESD event can be substantially higher than at the back-to-back diodes 1 and 2. A typical value for temporary voltage on GNDE can amount to over 5 V at 3.8 A. The ground rails are separated to prevent noise from propagating from portions of a higher noise level to portions having a lower noise level of the circuit. These rails remain separated until the assembly process where they will eventually be connected together and therefore at the same potential. Until this point, there is an ESD risk due to the separation of these two rails. However, the bonding wires or similar connections to the lead frame provide high impedances at high frequencies, such that the noise may not propagate over these wires being connected to the other pads 7.
Fig. 2 shows a similar schematic as the one shown Fig. 1, where the same components have the same reference numbers. However, the circuitry of Fig. 2 provides additionally the back-to-back diode elements 8,9 in a configuration according to an aspect of the present invention. Accordingly, the diode elements 8 and 9 are provided in a continuously distributed manner along the rails GND and GNDE. As more diode elements are provided the size of each diode element 8, 9 can be reduced. According to this arrangement, the ESD events on a specific pad 7 will be reduced more efficiently and closer to the point of origin. Fig. 3 shows the typical layout of a back-to-back diode configuration according to the prior art. The size and the location in the layout of a power supply pad cell 21 are indicated by the black box 130 in Fig. 3. Accordingly, the area consumed by the back- to-back diodes in the pad cell 21 is considerable. Further, the location and the layout of the back-to-back diodes is not optimal according to the prior art configuration shown in Fig. 3. Fig. 4 shows a simplified layout of a typical semiconductor device 400 according to an aspect of the present invention that suits to overcome the drawbacks of the prior art. Numerous power and ground rails are routed around the core 500 of the chip, which is indicated by reference number 201. Further, there are numerous pad cells 20, 21 close to the edges of the semiconductor die, each providing a contact pad for the bonding wires (not shown). Bonding is often used to contact the semiconductor die to a lead frame (not shown). The lead frame is part of the package (housing of the die) and provides the pins to be soldered to a circuit board. The semiconductor die 400 is completed by a seal ring 100. The presence of the layers provides efficient sealing. Accordingly, the seal ring provides also a conductive metal layer (MET). According to an aspect of the present invention, there is path of protective diode elements 200 provided between the seal ring 100 and the ground and
power rails 201. The diode elements are distributed continuously along the ground rails 201. Instead of providing only some lumped back-to-back diodes 1, 2 as shown in Fig. 1, the present invention suggest to continuously distribute the diodes around the chip. As will be explained below with respect to Figures 4 to 7, the ring of diode elements 200, comprises back-to-back diode elements which are coupled to the respective ground rails GND and GNDE. According to a second aspect, the diode elements are located between the pad cells 21, 20 and the seal ring 100. The area between the seal ring 100 and the rails 201 or the pad cells 21, 20 is usually not used. Accordingly, the diode elements are moved outside the I/O pad cells and the power pad cells. The connection to the diode elements is more efficient in this area.
Fig. 5 shows a section of the layout of the integrated circuit of Fig. 4 in more detail. On the left side, there are the power and ground rails 201 and the pad cells 20 and 21. The various ground rails and power rails 201 are usually formed in a metal layer (MET), which can be one of multiple metal layers dependent on the technology. On the right side of Fig. 5, another large metal rectangle is shown that is part of the seal ring 100. Between the seal ring 100 and the ground ring 201, there is the path 200, wherein the diode elements 8,9 are implemented. The path 200 includes multiple paths of Nwell 71, 72, 73 and multiple areas of P+ 61, 62, 63, 64. According to the present invention, the back-to-back diode elements 8, 9 according to the present invention are implemented between the two P+ areas 61, 62 and 63, 64 respectively. Just as one example, in order to illustrate the electrical properties of the layout, two rectangular N+ and P+ areas are extracted and shown again in the box on the right corner of Fig. 5. As indicated by the diode symbol aside the rectangular areas, each diode element consists of one N+ area as anode and one P+ area as cathode. The layout shown in Fig. 5 is only a small part of the whole layout and serves to illustrate the basic principle. However, the same structure can be extended throughout the whole circumference of semiconductor device 400 as indicated by the reference number 200 in Fig. 4.
Fig. 6 shows the same section as Fig. 5 but additionally including the metal layers (MET) used for contacting the back-to-back diodes. The Nwell areas 71, 71, 73 of Fig. 5 are now represented by the N+ areas. The metal paths 110 and 120 are arranged above an N+ and a P+ area, respectively. In order to visualize the P+ and N+ areas, the other metal paths 130 to 160 are transparent and represented only by dashed lines although they are similar to the metal paths 110 and 120. The metal paths 110 tol60 contact the back-to-back diodes to the respective ground rails 100 and 201 of Fig. 5, which are not shown in Fig. 6.
Fig. 7 shows a cross sectional view of the back-to-back diode configuration according to the present invention as indicated by line A-A'. The active diode areas N+ and P+ are separated by a shallow transistor isolation (STI). The metal paths 110-160 are coupled to the N+ and P+ areas by contacts (e.g. VIAs). A P well is arranged below the P+ and N+ areas being located a deep Nwell (DNW) indicated by the bold dashed line. According to this arrangement, there is almost complete isolation of the diodes (diode areas P+ and N+) from the substrate. Accordingly, the noise coupling to the substrate is substantially reduced.
Fig. 8 is a cross sectional view along the line B-B' of Fig. 6. The metal path 110 is connected to P+ areas and N+ areas via a number of small contacts (CONTACT). Below the active P+ and N+ areas, there are two Pwell regions separated from each other by Nwells. Below the Pwell and Nwell areas, there is a deep Nwell area decoupling the Pwell areas from the substrate. As already explained with respect to Fig. 7, this configuration decouples the diodes from the substrate and prevents noise from propagating via the diode elements 8, 9 into the substrate. The noise coupling to the substrate can additionally be reduced if the seal ring
100, in particular the metal layer provided on the seal ring, is not connected to substrate but used to provide an additional ground (internal ESD rail) that is directly coupled to the lead frame. This can be realized by conductive adhesive or the like used to couple the semiconductor die to the lead frame. If the upper layers, i.e. metal layers of the seal ring are directly coupled to external circuitry, the noise propagating from the pad cells 20 can be deduced without any propagation through the substrate. This serves to reduce noise in the substrate.
Fig. 9 shows the impedance Zl between two ground rails 201 and 100 (GND and GNDE) according to the present invention in arrangement like the one shown in Fig. 4. The sections of each rail 201 and 100 provide an impedance value Zb designated by reference number 50 dependent on the technology and the respective metal sheets used. The back-to- back diodes 8,9 provide an impedance Z m designated by reference number 51. Accordingly, the overall impedance Zl for N repeating sections for an arrangement shown in Fig. 9 will amount to:
Zl = Z b (l + [l + 2 (Z b / Z m )f 2 ).
Assumed that N is sufficiently large and that the impedance 50 has a value Zb and the impedance 51 a value Z m . Below, there is the impedance according to the prior art,
where the overall impedance is lumped in the back-to-back diodes of the power supply pad 21 as shown in Fig. 1. The respective formula for Z2 is
Z2 = 2 N Z b + Z m / N.
Fig. 10 shows the evaluation of the two formulas for different relations of Z m to Zb for different values of N. Accordingly, the ratio of the distributed to the lumped effective impedance Z1/Z2 shows that the distributed network according to the present invention is less resistive. However, the exact values depend on the ratio of the parallel (Z m ) to the series (Zb) impedances. Typical values for the ration of Z m /Zb are in the area 302, that is between 1 and 10. Accordingly, the distributed effective impedance Zl amounts to approximately 1/3 to 1/10 of the impedance of the conventional solutions.
By distributing the diode elements in a previously unused region between the pads and the seal rings, the effective impedance can be reduced by 70 to 90 %. If the diode rings are coupled to an internal ESD common rail, e.g. the seal ring, this can considerably reduce the substrate noise injection from the ground rail.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.
In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single diode element or conductive path or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.
A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.
Any reference signs in the claims should not be construed as limiting the scope.
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