Title:
DIVIDE-BY-TWO DIVIDER CIRCUIT HAVING BRANCHES WITH STATIC CURRENT BLOCKING CIRCUITS
Document Type and Number:
WIPO Patent Application WO/2014/120416
Kind Code:
A3
Abstract:
A divide-by-two divider circuit receives a differential input signal and outputs four rail-to-rail, twenty-five percent duty cycle signals, where the frequency of the output signals is half of the frequency of the input signal. Each latch can output its output signals into loads of at least 15fF at a frequency of at least 3GHz so that each output signal has a phase noise of better than 160dBc/Hz, while the latch consumes less than 0.7mW over PVT from a supply voltage less than 1.0 volt. Each latch has a cross-coupled pair of P-channel transistors and two output signal generating branches. A static current blocking circuit in each branch prevents current flow in the branch during times when the branch is not switching its output signal. The input node of the latch is capacitively coupled to a signal source, and the DC voltage on the node is set by a bias circuit.
Inventors:
KHALILI ALIREZA (US)
Application Number:
PCT/US2014/011181
Publication Date:
October 23, 2014
Filing Date:
January 11, 2014
Export Citation:
Assignee:
QUALCOMM INC (US)
International Classes:
H01L29/423; H03K3/03; H03K3/354; H03K3/3562
Foreign References:
| US20080001645A1 | 2008-01-03 | |||
| US20120081156A1 | 2012-04-05 |
Other References:
RAZAVI B ET AL: "DESIGN OF HIGH-SPEED, LOW-POWER FREQUENCY DIVIDERS AND PHASE-LOCKED LOOPS IN DEEP SUBMICRON CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 30, no. 2, 1 February 1995 (1995-02-01), pages 101 - 109, XP000496300, ISSN: 0018-9200, DOI: 10.1109/4.341736
Attorney, Agent or Firm:
BINDSEIL, James J. et al. (LLP1717 K Street, N.W, Washington District of Columbia, US)
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