DIVIDER CIRCUIT, DEMULTIPLEXER CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT

Title:

DIVIDER CIRCUIT, DEMULTIPLEXER CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT

Document Type and Number:

WIPO Patent Application WO/2017/154191

Kind Code:

A1

Abstract:

A divider circuit includes: a first divider circuit unit (10) that generates a first divided clock signal by dividing a first clock signal; a second divider circuit unit (20) that generates a second divided clock signal by dividing a second clock signal having a first phase difference at the same frequency as the first clock signal; a detection circuit (30) that detects a phase relationship between the first divided clock signal and the second divided clock signal; and a selection circuit (50) that selects and outputs one of the second divided clock signal generated by the second divider circuit unit and an inverted signal of the second divided clock signal. The selection circuit selects and outputs, on the basis of the phase relationship between the first divided clock signal and the second divided clock signal detected by the detection circuit, one of the second divided clock signal and the inverted signal of the second divided clock signal, thereby making it possible to generate and output a divided clock signal that retains a desired phase relationship with respect to the first divided clock signal and that is based on the second clock signal.

Inventors:

SAKAE TATSUYA (JP)
KANO HIDEKI (JP)

Application Number:

PCT/JP2016/057719

Publication Date:

September 14, 2017

Filing Date:

March 11, 2016

Export Citation:

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Assignee:

SOCIONEXT INC (JP)

International Classes:

H03K23/00

Foreign References:

JP2012060319A	2012-03-22
JP2007243617A	2007-09-20
JPS63306732A	1988-12-14
JPH04127617A	1992-04-28

Other References: