Field

The present invention relates to a divider synchronization device, and a method of operating thereof.

Background

In recent years, Multiple-Input Multiple-Output (MIMO) beam-forming techniques have been gaining rapid popularity, due to being able to enable faster data transmission rates at higher efficiencies. This consequently drives a need to synchronize multiple (power) dividers that are used to generate the associated RF signals. When using multiple dividers, each divider starts with a random phase and conventionally, the dividers typically do not provide a way of synchronizing their outputs. While trigger-based synchronization techniques may be used to align multiple channels in measurement equipment, the challenge however is to synchronize the dividers when the timing of a triggering synchronization (SYNC) signal is unknown. In MIMO systems, when the dividers are disabled or enabled due to phase ambiguity of the start-up of the dividers, they will need to be calibrated for phase. Whenever the dividers are enabled and disabled, the phase sync is lost and if the SYNC signal occurs close to the clock edge, the dividers may be triggered with different phases. So to avoid this, the dividers have to be kept switched on, but at the expense of unnecessary power consumption. Even within a same chip, with increasing chip size being used to accommodate circuitries for facilitating multiple transmission channels, it is not possible to control an absolute time of the SYNC signal with respect to the clock signal, due to process, voltage and thermal variations.

One object of the present invention is therefore to address at least one of the problems of the prior art and/or to provide a choice that is useful in the art.

Summary

According to a 1 ^st aspect of the invention, there is provided a divider synchronization device comprising: at least first and second circuit portions configured to generate respective radio signals for multichannel transmission, each circuit portion having a processor module electrically coupled to a switch and a frequency divider, the switch electrically opearable to selectively couple the frequency divider to a local-oscillator, the processor module arranged to receive a clock signal generated by the local-oscillator and a synchronization signal that has been re-timed with reference to the clock signal. The device is configured to operatively perform the following steps: (i) configuring the respective frequency dividers to a common initial state, which are arranged to be switched off; (ii) configuring each processor module to compare the received synchronization signal with the clock signal to enable selection of a first edge or a second edge of a clock cycle of the clock signal, the selected edge arranged to be used as a temporal indicator at when the clock signal is to be provided to the associated frequency divider, the comparison performed by determining whether the positive edge of the synchronization signal is within a predefined time window of the first edge, in which the first edge is selected if the positive edge is outside the time window and the second edge is selected if the positive edge is within the time window; (iii) transmitting respective first signals by the respective processor modules to switch on the respective frequency dividers; and (iv) detecting occurrence of the respective selected edges on the clock signal by the respective processor modules and in response, transmitting respective second signals by the respective processor modules to the respective switches to couple the respective frequency dividers to the local-oscillator in order for the clock signal to be provided to the respective frequency dividers to generate corresponding outputs.

Advantageously, the proposed device enables synchronization of the output phase of multiple frequency dividers using a trigger based synchronization method.

Preferably, the first and second edges may respectively be a positive edge and a negative edge, or the first and second edges may respectively be a negative edge and a positive edge.

Preferably, the first circuit portion may further include a first initialization module configured to receive the clock signal and an unprocessed synchronization signal for processing to generate the re-timed synchronization signal, and wherein the first initialization module is configured to transmit the re-timed synchronization signal to the respective processor modules.

Preferably, the second circuit portion may further include a second initialization module configured identically as the first initialization module, and arranged to be operable in replacement of the first initialization module, if the first circuit portion is electrically disabled.

Preferably, the local-oscillator may be arranged to be part of the device.

Preferably, each processor module may include an edge detector module and an edge selector module, the edge detector module configured to compare the synchronization signal with the clock signal to enable the selection of the first edge or the second edge of the clock cycle of the clock signal; and the edge selector module configured to use information associated with the selected edge for generating and transmitting the first and second signals respectively to the associated frequency divider and switch.

Preferably, the common initial state may be selected from the group of divider states consisting of: 00, 10, 1 1 and 01.

According to a 2 ^nd aspect of the invention, there is provided a multichannel transceiver apparatus comprising the device of the 1 ^st aspect. According to a 3 ^rd aspect of the invention, there is provided a method of operating a divider synchronization device, the device includes at least first and second circuit portions configured to generate respective radio signals for multichannel transmission, each circuit portion having a processor module electrically coupled to a switch and a frequency divider, the switch electrically opearable to selectively couple the frequency divider to a local-oscillator, the processor module arranged to receive a clock signal generated by the local- oscillator and a synchronization signal that has been re-timed with reference to the clock signal. The method comprises: (i) configuring the respective frequency dividers to a common initial state, which are arranged to be switched off; (ii) configuring each processor module to compare the received synchronization signal with the clock signal to enable selection of a first edge or a second edge of a clock cycle of the clock signal, the selected edge arranged to be used as a temporal indicator at when the clock signal is to be provided to the associated frequency divider, the comparison performed by determining whether the positive edge of the synchronization signal is within a predefined time window of the first edge, in which the first edge is selected if the positive edge is outside the time window and the second edge is selected if the positive edge is within the time window; (iii) transmitting respective first signals by the respective processor modules to switch on the respective frequency dividers; and (iv) detecting occurrence of the respective selected edges on the clock signal by the respective processor modules and in response, transmitting respective second signals by the respective processor modules to the respective switches to couple the respective frequency dividers to the local-oscillator in order for the clock signal to be provided to the respective frequency dividers to generate corresponding outputs.

Preferably, the first and second edges may respectively be a positive edge and a negative edge, or the first and second edges may respectively be a negative edge and a positive edge.

It should be apparent that features relating to one aspect of the invention may also be applicable to the other aspects of the invention.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

Brief Description of the Drawings

Embodiments of the invention are disclosed hereinafter with reference to the accompanying drawings, in which:

FIG. 1 shows schematics of a divider synchronization device, according to an embodiment.

FIG. 2 is a flow diagram of a method of operating the device of FIG. 1 .

FIG. 3 shows schematics of an initialization module.

FIG. 4 shows schematics of a processor module of the device of FIG. 1 . FIG. 5 shows schematics of a switch and a frequency divider of an associated circuit portion of the device of FIG. 1.

FIG. 6 shows various states of a state machine configured for the frequency dividers of the device of FIG. 1 .

FIG. 7 shows respective timing diagrams of signals processed by the device of FIG. 1 , when operated in calibration mode and normal mode.

FIG. 8 shows schematics of a variant processor module for the device of FIG. 1.

Detailed Description of Preferred Embodiments

FIG. 1 discloses schematics of a divider synchronization device 100 (hereinafter “device”), according to an embodiment. The device 100 is implemented as a circuit chip. Broadly, the device 100 comprises at least first and second circuit portions 102, 104 configured to generate respective radio signals for multichannel transmission. More specifically, the first and second circuit portions 102, 104 respectively generate first and second transmission (radio) channels. Each circuit portion 102, 104 includes a processor module 106, 108 electrically coupled to a switch 1 10, 1 12 and a frequency divider 1 14, 1 16. The switch 1 10, 1 12 is electrically opearable to selectively couple the frequency divider 1 14, 1 16 to a local-oscillator (LO) 1 18. In this case, the LO 1 18 is arranged as part of the device 100, but need not be so in variant embodiments. The processor module 106, 108 is arranged to receive a (differential) clock signal generated by the LO 1 18 and a synchronization signal that has been re timed with reference to the clock signal . The clock signal is labelled as“CLKP, NT in FIG. 1.

The first circuit portion 102 further includes a first initialization module 120 configured to receive the clock signal and an unprocessed synchronization signal (i.e. labelled as“SYNC" in FIG. 1) for processing to generate the re-timed synchronization signal (i.e. termed “SYNC _re-ti meci" to prevent confusion with “SYNC”) , and wherein the first initialization module 120 is configured to transmit the “SYNC re- _ti me _d ” signal to the respective processor modules 106, 108. Similarly, the second circuit portion 104 further includes a second initialization module 122 configured identically as the first initialization module 120, and specifically arranged to be operable in replacement of the first initialization module 120, but only in event that the first circuit portion 102 is electrically disabled (e.g. due to circuit failure). It is to be appreciated that the second initialization module 122 is arranged to receive another unprocessed synchronization signal (i.e. labelled as “SYNC.2” in FIG. 1). For MIMO applications that require synchronization of the frequency dividers 1 14, 1 16, the second initialization module 122 is bypassed and not used operationally. Both the first and second initialization modules 120, 122 are implemented using a plurality of flip-flops in a series configuration - see FIG. 3.

With reference to FIG. 2, which depicts a method 200 of operating the device 100, the device 100 is arranged to operatively perform the following steps: at step 202, configuring the respective frequency dividers 1 14, 1 16 to a common initial state, and the frequency dividers 1 14 are also switched off at this step; at step 204, configuring each processor module 106, 108 to compare the received synchronization signal with the clock signal to enable selection of a first edge or a second edge of a clock cycle of the clock signal, the selected edge arranged to be used as a temporal indicator at when the clock signal is to be provided to the associated frequency divider 1 14, 1 16, the comparison performed by determining whether the positive edge of the synchronization signal is within a predefined time window of the first edge, in which the first edge is selected if the positive edge is outside the time window and the second edge is selected if the positive edge is within the time window; at step 206, transmitting respective first signals by the respective processor modules 106, 108 to switch on the respective frequency dividers 1 14, 1 16; and at step 208, detecting occurrence of the respective selected edges on the clock signal by the respective processor modules 106, 108 and in response, transmitting respective second signals by the respective processor modules 106, 108 to the respective switches 1 10, 1 12 to couple the respective frequency dividers 1 14, 1 16 to the LO 1 18 in order for the clock signal to be provided to the respective frequency dividers 1 14, 1 16 to generate corresponding outputs. In this manner, the device 100 is beneficially configured to synchronize the output phase of the two frequency dividers 1 14, 1 16.

The first and second edges (of a clock cycle of the clock signal) may respectively be a positive edge and a negative edge, or that the first and second edges may respectively be a negative edge and a positive edge. The common initial state may be selected from the group of divider states consisting of:“00”, “10”, “1 1” and“01”. Then, each processor module 106, 108 includes an edge detector module 400, 402 and an edge selector module 404, 406. The edge detector module 400, 402 is configured to compare the synchronization signal with the clock signal to enable the selection of the first edge or the second edge of the clock cycle of the clock signal, whereas the edge selector module 404, 406 is configured to use information associated with the selected edge for generating and transmitting the first and second signals respectively to the associated frequency divider 1 14, 1 16 and switch 1 10, 1 12.

Further, it is to be appreciated that the two frequency dividers 1 14, 1 16 are located substantially far apart on the device 100, in this case. It is to be appreciated that while the clock signal generated by a same LO 1 18 guarantees same absolute phase difference, this however still cannot ensure maintenance of the phase-relationship between the frequency dividers 1 14, 1 16. This is due to the ambiguous phase relationship introduced by the frequency dividers 1 14, 1 16. So to address the problem, an external trigger signal (i.e. in the form of the unprocessed synchronization signal) is used to synchronize the phase of the two frequency dividers 1 14, 1 16, such that the frequency dividers 1 14, 1 16 are able to maintain the same relative phase. The synchronization is done via a calibration mode and a normal mode of the device 100, which are described below.

In the calibration mode, the“SYNC" signal is provided by setting a bit in the command register (CR) and the “SYNC" signal is transmitted to the first initialization module 120. The“SYNC" signal is randomly generated with respect to the clock signal, i.e. the positive edge of the “SYNC" signal is not synchronized and aligned with the clock signal. The first initialization module 120 then samples the“SYNC" signal and re-times the“SYNC" signal with respect to a clock edge of the clock signal to generate the “ SYNC _re-timed ” signal. The SYNC _re-tjmeci signal is provided to both the processor modules 106, 108 of the first and second circuit portions 102, 104. While the SYNC _re-t , _med ” signal to the processor module 106 of the first circuit portion 102 has been re-timed with respect to the clock signal received by said processor module 106, the positive edge of the“ SYNC _re-timed ” signal may however still drift with respect to the clock edge of the clock signal received by the processor module 108 of the second circuit portion 102, 104, due to the physical circuit distance separating the first and second circuit portions 102, 104 on the device 100, and also because of clock skew.

As depicted in FIG. 4, the“ SYNC _re-timed ” signal is received by the edge detector module 400, 402. If the edge detector module 400, 402 does not detect a rising edge, it means that the“ SYNC _re-timed ” signal has not yet been received and the edge detector module 400, 402 is configured to wait in a hold state (e.g.“00”), as well as hold the associated frequency divider 1 14, 1 16 in the initial state (i.e. refer to step 202). It is to be appreciated that this concept is applicable for any number of frequency dividers (arranged in the device 100) as long as there is an initialization module to hold the frequency dividers in their common initial states. Once the “SYNC _re-timed ” signal is received, the edge detector module 400, 402 establishes the position of the“SYNC _re-timed ” signal (relative to the clock signal) with help of a time window detector (not shown) to determine if the positive edge of the “SYNCre-timed” signal is closer to a first edge or a second edge of a clock cycle of the clock signal. By this, a comparison is performed to determine whether the positive edge of the “ SYNC _re-t , _med ” signal is within a predefined time window of the first edge, in which the first edge is selected if the positive edge is outside the time window (i.e. the positive edge is determined to have a sufficient margin from the first edge, as defined by the time window), or the second edge is selected if the positive edge is within the time window (i.e. the positive edge is determined to have insufficient margin from the first edge, as defined by the time window).

Based on results of the comparison, the edge detector module 400, 402 recommends selection of the first/second edge with a higher margin to be used for initializing the frequency divider 1 14, 1 16. In other words, the selected edge acts as a temporal indicator at when the clock signal is to be provided to the respective frequency dividers 1 14, 1 16. As an example to illustrate, for a 5 GHz signal having a period of 200 ps, the window detector uses a time window of 25 ps defined around the first edge (i.e. a time window of 12.5 ps on each side of the first edge). If the positive edge of the “ SYNC _re-t , _med ” signal falls outside this 25 ps time window, the edge detector module 400, 402 selects the first edge to trigger the frequency divider 1 14, 1 16; else the edge detector module 400, 402 selects the second edge. In this embodiment, information associated with the selected edge is output as an “EDGE_DETECT signal, and provided as a separate“EDGE_SELECT signal to the edge selector module 404, 406 (in the normal mode to be elaborated below).

In the normal mode (i.e. see FIG. 5), the information associated with the selected edge is provided to the edge selector module 404, 406, which is arranged to first switch on the frequency divider 1 14, 1 16 from its initial state by transmitting the first signal (i.e. labelled as “ DIV_ENABLE” in FIG. 4), and next provide the clock signal to the said frequency divider 1 14, 1 16 (on detection of occurrence of the selected edge on the clock signal) by transmitting the second signal (i.e. labelled as “ SWITCH _EN ABLE” in FIG. 4). More specifically, the second signal is transmitted to the switch 1 10, 1 12 of the associated circuit portion 102, 104, so that the switch 1 10, 1 12 is enabled to couple the frequency divider 1 14, 1 16 to the LO 1 18 in order for the clock signal to be provided to the said frequency divider 1 14, 1 16. It is to be appreciated that a typical frequency divider starts operation with the rising edge of a clock signal. With a continuous clock signal, the frequency divider may start in any random phase.

So, the comparison result obtained by the edge detector module 400, 402 is used in the normal mode to do the edge selection and the edge selector module 404, 406 is configured to subsequently switch on the frequency divider 1 14, 116 using the first signal (i.e. labelled as“DIV_ENABLE” in FIG. 4). As the position of the“ SYNCre-timed” signal with respect to the first edge or the second edge of the clock cycle of the clock signal has already been established by the edge detector module 400, 402, the“SYNC _re-timeci " signal thus always has sufficient margin to said selected clock edge, thereby avoiding ambiguity in start-up of the frequency dividers 1 14, 1 16. In this manner, the frequency dividers 1 14, 1 16 are triggered by a clock edge having a good margin, and therefore able to maintain the same relative phase to one another.

To reiterate, the frequency dividers 1 14, 1 16 are arranged with the first and second initialization modules 120, 122. As will be appreciated, the switches 23, 27 are configured to hold the clock signal from being provided to the frequency dividers 1 14, 1 16, until the switches 23, 27 are activated. As a result, the first and second initialization modules 120, 122 of the frequency dividers 1 14, 116 maintain the frequency dividers 1 14, 1 16 first at the common initial state (e.g. “00”) - see a state machine 6 in FIG. 6 as devised in this case. Once a suitable edge of the clock signal has been selected by the edge selector modules 404, 406, the information pertaining to the selected edge (for each circuit portion 102, 104) is stored in an external register (not shown). The information is then used by the edge selector module 404, 406, which generates the second signal to close the associated switch 1 10, 1 12 to provide the clock signal to the associated frequency divider 1 14, 1 16, subsequent to the first signal being transmitted to release the frequency divider 1 14, 1 16 from the initial state. Since the“ SYNC _re-t , _med ” signal has sufficient margin with respect to the selected edge of the clock signal in both frequency dividers 1 14, 1 16, and that the frequency dividers 1 14, 116 are configured to start with the same initial state, the frequency dividers 1 14, 1 16 are therefore able to maintain a fixed relative phase with respect to each other. This fixed relative phase can be determined in the device 100 and calibrated out of the device 100, if necessary depending on applications. FIG.7 illustrates first and second timing diagrams 700, 750 of the respective signals (processed by the device 100) during the calibration and normal modes. In this case, although provision of the information associated with the selected edge from the edge detector module 400, 402 to the edge selector module 404, 406 is off-chip, it is however also possible to implement the feedback as on-chip (i.e. the“EDGE_DETECT signal is directly furnished as the“ EDGE_SELECT signal) in a variant embodiment - see FIG. 8. Further, while the second timing diagram 750 shows output of the two frequency dividers 1 14, 1 16 as in-phase, it need not be so, since FIG. 7 is just an example illustration, and is not to be construed as limiting. Indeed, the frequency dividers 1 14, 1 16 may have a different phase (from that shown in FIG. 7), depending on the delay and clock skew between the circuit portions 102, 104. The proposed device 100 ensures that even if the frequency dividers 1 14, 1 16 have a different phase, they 1 14, 1 16 are able to still retain a fixed phase relation between each other. To summarise, the proposed device 100 is devised to enable synchronization of a plurality of frequency dividers 1 14, 1 16 using a trigger based synchronization concept that utilizes the edge detector and selector modules 400, 402, 404, 406 (which are collectively termed as the processor module 106, 108) to synchronize the output phase of the frequency dividers 114, 1 16. Specifically, the edge detector module 400, 402 establishes a position of the “SYNC" signal with respect to the clock edge. The edge selector module 404, 406 is configured to generate the same fixed output phase relation between the frequency dividers 1 14, 1 16, irrespective of possible process, voltage and thermal (PVT) variations. Particularly, the disclosed concept makes use of the relative timing of the “SYNC” signal to synchronize the frequency dividers, thereby alleviating the effects of PVT variations.

Hence, the device 100 provides a solution to enable faster divider synchronization using a low-speed trigger to synchronize the start-up of two or more frequency dividers in a multi-channel transceiver with help of the processor modules 106, 108 and the frequency dividers 1 14, 1 16 coupled with associated switches 1 10, 1 12. It is to be appreciated that the disclosed concept is also applicable to synchronize a plurality of frequency dividers by daisy-chaining multiple“SYNC” signals.

Accordingly, the device 100 is purposefully devised to have the following advantages:

1. In MIMO systems when frequency dividers are disabled or enabled due to phase ambiguity of the start-up of the frequency dividers, they consequently need to repeatedly be re-calibrated for phase synchronization. Each time the frequency dividers are disabled and enabled, the phase synchronization is lost. So to get around the issue, the frequency dividers typically have to be kept switched on, but however at the expense of incurring power (which is inefficient). The proposed device 100 advantageously addresses this issue, by allowing the frequency dividers to be enabled or disabled at different times, but yet still able to maintain phase synchronization between the frequency dividers.

2. The disclosed device 100 uses a low-speed trigger signal to synchronize (high speed) frequency dividers to prevent the hassle of routing the clock signal generated by the LO 1 18 (which is a high speed signal) from one circuit portion (i.e. a channel) to another circuit portion (i.e. another channel) to synchronize the outputs of the frequency dividers that may be separated by a substantial distance on the device 100.

3. The device 100 is useful for MIMO applications to establish a fixed phase relationship between multiple frequency dividers, and beneficially, the synchronization between the frequency dividers may be achieved at a very fast speed.

4. The disclosed method 200 is based on the time domain comparison to locate the best clock edge of the clock signal that may be utilized to trigger the frequency dividers, in order that the frequency dividers maintain the same relative phase each time the frequency dividers are triggered, despite PVT variations.

While the invention has been illustrated and described in detail i n the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary, and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed invention.

For example, the device 100 may comprise more than two circuit portions 102, 104, i.e. a plurality of circuit portions, if it is desired that the device 100 has more than two transmission channels (e.g. in MIMO applications) . While the proposed device 100 is arranged to be incorporated as part of a multichannel transceiver apparatus (e.g. a MIMO transceiver), but it is not limited as such. Indeed, the proposed device 100 may also find usages in suitable alternative applications, and/or communication systems (that may similarly require synchronization of the output phase of frequency dividers).