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Patent Searching and Data


Title:
DLL CIRCUIT, TEMPORAL DIFFERENCE AMPLIFYING CIRCUIT, AND RANGING/IMAGING DEVICE
Document Type and Number:
WIPO Patent Application WO/2020/129947
Kind Code:
A1
Abstract:
A DLL circuit (10) is provided with: a temporal difference amplifying circuit (11) which, with respect to a first signal and a second signal that have been input, performs a process for amplifying a temporal difference between an edge that is a point of change in logic level included in the first signal and an edge that is a point of change in logic level included in the second signal, and which outputs a resultant first amplified signal and second amplified signal; a phase comparison circuit (12) which calculates a phase difference between the first amplified signal and the second amplified signal output from the temporal difference amplifying circuit (11), and outputs a phase difference signal indicating the calculated phase difference; and a variable delay circuit (13) which causes the second signal to be delayed by a delay amount that depends on the phase difference indicated by the phase difference signal output from the comparison circuit (12), and outputs the second signal as a delayed signal.

Inventors:
KATO TAKUMI
MATSUKAWA KAZUO
OZEKI TOSHIAKI
Application Number:
PCT/JP2019/049308
Publication Date:
June 25, 2020
Filing Date:
December 17, 2019
Export Citation:
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Assignee:
PANASONIC SEMICONDUCTOR SOLUTIONS CO LTD (JP)
International Classes:
G01C3/06; G01S17/89; H03L7/081; H04N5/376
Domestic Patent References:
WO2012120569A12012-09-13
Foreign References:
US20150177701A12015-06-25
JP2009236657A2009-10-15
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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