Background and Summary of the Invention DC-DC converters have long been utilized in a variety of electronic devices. Such DC-DC converters often utilize isolation transformers coupled with a controlled converter primary switching circuit for supplying alternating pulses through the isolation transformer and a converter rectification and filtering secondary circuit.

A variety of transformer isolated D. C.-D. C. converters employ diodes to perform signal rectification. In lower voltage applicationsSchottky diodes are commonly utilized for signal rectification in the converter secondary circuitry. This is because Schottky diodes have a relatively low forward conduction voltage drop of about. 3 volts. D. C.-D. C. converters employing diode rectification in the secondary circuit are well known and are well described in the literature. However, the forward voltage threshold of approximately. 3 volts in Schottkey diodes still results in substantial losses in power conversion efficiency, particularly in power supplies having a desired output voltage of about 3.3 volts.

D. C.-D. C. converters are commonly utilized to power integrated circuit electronics. Such integrated circuit electronics typically require a drive voltage of either 3.3 or 5 volts. In order to enhance converter efficiency the voltage drop present in Schottky diodes is desirably avoided in such low voltage DC to DC converters. One proposal for avoidance of the use of Schottky diodes is presented in a publication entitled"The Performance Of The Current Doubler Rectifier With Synchronous Rectification"byLaszlo Balogh, HFPC, May 1995 Proceeding, pg. 216. This publication proposes the use of a current doubler rectifier secondary in D. C.-D. C. converters in place

of known push-pull, half bridge, and bridge topologies. The publication further proposes to use synchronous rectification to increase converter efficiency in low voltage, current doubler converters by replacing the Schottky diodes with control driven MOS-FETs'. These transistors, according to the publication should be switched on before the conduction of the MOS-FETs body diodes, while avoiding a short circuit across the secondary winding which may be caused by two simultaneously conducting synchronous switches. Thus, the above-mentioned publication proposes to utilize control-driven MOS-FETs in a D. C.-D. C. converter having a current doubler rectifier secondary.

It is clear that the current doubler rectifier employed in the Balogh publication is intended to employ a common input and output ground in order to avoid complex gate drives schemes. Thus, the converter proposed in the Balogh reference cannot provide complete transfer isolation without a complex gate drive scheme. This is primarily due to the reference's avoidance of a center tap in the transformer employed with the current doubler circuitry in order to avoid the complication of a split secondary transformer.

Because of the lack of such a center tap, the voltage output from the transformer secondary in the current doubler circuit proposed by the Balogh reference is too high to feed the gating circuitry used to gate the rectifying MOS FETs. While the secondary transformer voltage may be voltage divided to the desired voltage level, this results in power loss, deteriorating the efficiency of the current doubler rectifier of the Balogh publication. In the circuitry contemplated by the Balogh publication, transistor gating circuit power is likely obtained from the circuit primary since, in the Balogh circuit, a common input and output ground is utilized to avoid such complex gate drive schemes. Thus, the Balogh publication utilizes a driving technique having substantial disadvantages if full isolation between converter primary and secondary circuits is to be achieved.

Half bridge rectifiers such as illustrated in Prior Art Figure 1 of the present application have also been known. Figures 1 (a)- (c) of the present application illustrate a Prior Art isolated DC-DC converter which employs a half bridge or push pull primary circuit and a full wave secondary circuit employing Schottky diodes Dl, D2. Converters of this type utilize the first and second rectifying diodes Dl, D2 not only as rectification diodes, but as fly-back diodes as well. This is best understood by an examination of the operation of the Figure 1 circuitry.

The circuit of Figure 1 operates in three primary modes illustrated in Figures 1 (a)-1 (c), respectively. A first primary transistor Ql which, in the preferred embodiment is an MOS-FET is turned on in a manner that is well known. When the first primary transistor Ql conducts, current flows between the positive and negative (+,-) terminals of the input supply voltage VIN through the conductive first primary transistor Ql, a primary winding TRiP of isolation transformer TRi, and second ripple filtering capacitor C2. This current is transferred across the core of the transformer TRi to a first isolation transformer secondary winding TRIS1 where it is supplied to a load RL through the first rectifying and fly-back diode Di and a low-pass filter including filtering or smoothing inductor Li and secondary filtering capacitor C3. Thus, power is supplied to the load.

When the first primary transistor Qi is switched off, the first rectifying and fly-back diode Di continues to conduct due to the free- wheeling action of the filtering or smoothing inductor Li. At this time, when both of the first and second primary transistors Qi, Q2 are turned off, the second rectifying and fly-back diode D2 also begins to conduct as illustrated in Figure 1 (b). At this time, both diodes Di and D2 are operating as fly-back diodes, supplying the residual energy stored in the filtering or smoothing inductor Li to the load. Thus, the diodes Dl, D2 operate in conjunction with the filtering or smoothing inductor Li to form

a free-wheeling or fly-back path through which the current within the inductor Li can"free-wheel".

Subsequently, the second primary transistor Q2 is switched on, conducting current from the input supply voltage Vin through capacitor Cl, the isolation transformer primary TR1P, and the second primary transistor Q2. This induces current along a loop including the second isolation transformer secondary TRiS2, through the center tap CT of the secondary, the load RL, the filtering or smoothing inductor Li, and the second rectifying and fly-back diode D2. Once again, the filtering or smoothing inductor Li and secondary filtering capacitor C3 function to low-pass filter this output voltage, smoothing it into a more nearly constant voltage Vo. When transistor Q2 again becomes non-conductive, diodes Di and D2 operate as fly-back diodes transferring the current from the filtering or smoothing inductor Li to the load RL.

The converter of Figure 1 exhibits the known efficiency problems of converters utilizing Schottky diodes for signal rectification in the secondary side of the converter, as mentioned above.

Applicants of the present application have discovered that DC-DC converters employing full wave secondary rectifying circuits are substantially advantageous over current doubler secondary circuits of the type disclosed in the Balogh publication when both high efficiency and full isolation is desirable. This is because such full-wave rectification secondary circuits employing a split secondary winding transformer exhibit intermediate voltages at the transformer secondary both accessible and of a level desirable for gate circuit drive, which voltages are not present in the current doubler circuitry of the aforementioned Balogh publication.

While the use of a current doubler secondary circuit of the type proposed by the Balogh publication produces efficient D. C. to D. C. conversion, the Balogh secondary may not be easily and efficiently gated by circuitry powered by the converter secondary circuit which is fully isolated from the converter primary circuit. However, Balogh considers the use of a

full wave secondary to be distinctly inferior to use of a current doubler rectifier.

In a DC to DC converter having a full wave secondary and split transformer secondary windings designed to drive the electronic circuitry at a normal drive voltage of, for example, 3.3 or 5 volts, the output of either secondary winding of the transformer is of the voltage level desirable for supplying power to electronic circuitry. However, at low voltages, the forward voltage drop of the rectification diodes is undesirable. It is therefore desirable to employ synchronous gating in a D. C.-D. C. converter having a full wave secondary, as such a D. C.-D. C. converter can more easily obtain the desired drive circuitry supply voltages from the converter secondary circuit. For this reason, such a converter is preferable, particularly in applications which require complete isolation between the converter primary circuit and the secondary circuit and load. Thus, although the isolated full wave DC to DC converter of the present invention requires a transformer with a split secondary, a gating circuitry drive voltage of a desired level may be readily obtained across either of the secondary coils without substantial efficiency loss, while maintaining full primary/secondary isolation.

Summary of the Invention Thus, applicant has designed a DC-DC converter using a transformer with a split secondary coupled to a full-wave rectifying secondary circuit. In this secondary circuit, synchronous switches are used and are driven by a switch conduction control controlling the conduction of the primary power supply switches and further controlling conduction of the first and second rectifying switches.

According to the further teachings of the present application, the switch conduction control includes a primary switch control controlling conduction of the primary controlled conduction switches, a secondary switch control controlling conduction of the first and second rectifying

switches, and a secondary control current isolator isolating said secondary switch control from said primary switch control.

According to the further teachings of the present application, the secondary switch control receives drive current directly from the secondary circuit of the DC to DC converter, thereby providing complete isolation between the primary and secondary circuits of the DC to DC converter.

From the foregoing, it is apparent that it is an object of the present invention to provide a low voltage D. C. to D. C. converter of high efficiency, which may be inexpensively manufactured.

It is another object of the present invention to produce a D. C. to D. C. converter having a fully isolated secondary circuit and load and which utilizes synchronous rectification in the converter secondary circuitry.

It is still another object of the present invention to employ a D. C. to D. C. converter having full isolation and synchronous rectification in the secondary circuitry of the converter, where the drive voltages for gating the synchronous rectifiers in the secondary circuit are obtained from the secondary circuit, thereby maintaining full current isolation of the secondary circuit and the load.

It is still further an object of the present invention to perform the above-mentioned objectives with a circuit that may be inexpensively manufactured.

It is still another object of the present invention to obtain the drive voltages for the aforementioned gating circuitry of the rectifying switches in the full-wave rectification secondary circuitry of the D. C. to D. C. converter by tapping the output voltage of a split secondary coil of a primary isolation.

Brief Description of the Drawings The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention.

Figures 1 (a)-1 (c) collectively illustrates a Prior Art double ended D. C.-D. C. converter having a push-pull or half bridge primary circuit transformer coupled to a full wave secondary circuit employing diode rectification as well as the operation of this circuit.

Figure 2 illustrates a double ended D. C.-D. C converter having a push-pull or half bridge primary circuit and a full wave fully isolated secondary circuit utilizing active control transistor switch rectification.

Figure 3 is a timing chart illustrating as exemplary switching of transistors Qi-Q4 in the embodiment of Figure 2.

Figure 4 illustrates one embodiment of a switching circuit SC used to switch the transistors Ql-Q4 of Figure 3.

Figure 5 is a timing chart illustrating the voltages developed in the circuit of Figure 4 to develop the timing signals used to control transistors Qi-Q4 in the embodiment of Figure 2.

Figure 6 illustrates a double ended full bridge converter embodiment having a full bridge primary circuit and applying the principles of the present application.

Detailed Description of Preferred Embodiments Figure 2 illustrates a double ended D. C.-D. C converter having a push-pull or half bridge primary circuit and a full wave secondary circuit utilizing active control transistor switch rectification. The circuit of Figure 2 is similar to the circuit of Prior Art Figure 1 but replaces the first and second rectifying diodes DI. D2 of Figure 1 with controlled first and second rectifying transistors Q3, Q4.

The circuit illustrated in Figure 2 converts an input voltage Vil, into an output voltage Vo, so long as the output voltage Vo is less than the input voltage Vin. The input voltage Vu, has a positive (+) terminal connected to a first terminal or drain of a first transistor Ql. The second terminal or source of the first transistor Ql is connected to a first terminal or source of a second primary transistor Q2. The second terminal or <BR> <BR> <BR> <BR> source of the second primary transistor Q2 is connected to the negative (-) terminal of the input supply voltage Vin.

An isolation transformer Tri is provided between the primary circuit portion (generally indicated as P) and including first and second primary transistors Ql, Q2, and the secondary circuit portion (generally indicated as S) of the double ended converter of Figure 2. Consequently, an isolation transformer primary winding TriP is connected to the primary circuit portion P of the half bridge converter of Figure 2. A first terminal of the isolation transformer primary winding TRiP is connected between the second terminal of the first primary transistor Ql and the first terminal of the second primary transistor Q2. The second terminal of the isolation transformer primary winding TRIP is commonly connected to first and second ripple filtering capacitors Ci, C2 which are, in turn, connected to the positive and negative terminals (-, +) of the input voltage Vin.

The secondary circuit portion S of the double ended converter of Figure 2 utilizes, in the preferred embodiment, a split isolation transformer secondary including a first isolation transformer secondary winding TriSi and second isolation transformer secondary winding TrlS2.

The center tap CT between the first and second isolation transformer secondary winding TriSi, TrlS2 is connected to a first terminal of a smoothing or filtering inductor Li The remaining terminal of the first isolation transformer secondary winding TrIS1 is connected to a first terminal of a first rectifying transistor

Q3. Similarly, the remaining terminal of the second isolation transformer secondary winding TriS2 is connected to a first terminal of a second rectifying transistor Q4. The second terminals of the first and second rectifying transistors Q3, Q4 are commonly connected to provide a secondary referenced ground A. A second terminal of the filtering or smoothing inductor Li is connected to a first terminal of a load RL supplied an output voltage Vo at the output of the secondary circuit portion S. A second terminal of the load Ri is connected to the secondary referenced ground A. A secondary filtering capacitor C3 is connected in parallel to the load RL. Filtering or smoothing inductor Li and secondary filtering capacitor C3 collectively form a low pass filter.

The first and second rectifying transistors Q3, Q4 are switched by a switch control SC under control of a control circuit CC. In one preferred embodiment, the control circuit CC outputs first and second switch gate signals GQ1, GQ2, the switch control SC timing the gating of the first and second rectifying switch gate signals GQ3, GQ4 therefrom. These signals are supplied to the first and second primary transistors Q1, Q2 and the first and second rectifying transistors Q3, Q4.

In the embodiment shown in Fig. 2, the control circuit CC may provide a signal. representative of desired duty cycle to the switch control SC. Of course, the control circuit CC can also supply primary gating signals A, B to the switch control SC as explained below with reference to Fig. 4 of the present application. However, one of the control circuit CC or switch control SC, depending on which develops the first and second switch gate signals GQ 1, GQ2 varies the duty cycle (on time) of the primary gate pulses GQ1, GQ2, as known in the art, and consequently the conduction periods of the secondary gate signals GQ3, GQ4 as well.

As will be explained in greater detail with respect to Figure 4, the control circuit CC and the switch control SC are biased by a primary

control supply voltage Vp. The control supply voltage Vp in accordance with the teachings of the present application may be derived from any suitable source such as the primary circuit portion P of the D. C.-D. C. converter of the present application. However, if full isolation of the secondary circuit portion S from the primary circuit portion P is desired, the gating circuitry for gating the first and second rectifying transistors Q3, Q4 must be fully isolated from the primary circuit portion P. This is accomplished by supplying the secondary switch gating portions (SG of Figure 4) of the switch control SC, which gate the first and second rectifying transistors Q3, Q4, with a secondary control supply voltage Vs.

The use of this secondary supply voltage Vs to supply the secondary switch gating portions SG maintains full isolation of the secondary circuit portion S. However, the secondary control supply voltage Vs must then be derived from the secondary circuit portion S.

In the embodiment of Fig. 2, the secondary control supply voltage Vs is obtained at a point A located between the commonly connected second terminals of the first and second rectifying transistors Q3, Q4 and the first terminal of the filtering or smoothing inductor Li. The anode of a bias current collection diode D7 is connected to this point A and supplies current to a first terminal of the bias voltage capacitor C4. The second terminal of a bias voltage capacitor C4 is connected to the center tap CT provided between the first and second isolation transformer secondary windings TrlSl, TrlS2. Thus the secondary control supply voltage Vs is derived across one or both of the first and second transformer secondary windings TrlSl, TrlS2.

Figure 3 illustrates the gate signals produced by the switch control SC of Figure 2. Such gate signals could easily be developed by suitable logic as would occur to one of ordinary skill in the art, with knowledge of the attached timing chart of Figure 3. Under control of the switch control

SC, and beginning immediately before time Ti of Figure 3, the switches are actuated by the switch control SC as follows: Immediately before time Ti, the gating signals GQ3, GQ4 applied to transistors Q3 and Q4 are present, and these transistors are conductive.

At time Ti, the gate signal GQ4 applied to transistor Q4 is turned off to render this transistor Q4 non-conductive. Substantially simultaneously, the gate signal GQ1 supplied to transistor Qi is turned on to render this transistor conductive. At time T2, the gating signal GQ1 to transistor Q 1 is turned off and substantially simultaneously, the gating signal GQ4 applied to transistor Q4 is turned on.

At time Ts, the gating signal GQ3 applied to transistor Q3 is turned off while the gating signal GQ2 applied to transistor Q2 is turned on. At time T4, the gating signal GQ2 applied to transistor Q2 is turned off and the gating signal GQ3 applied to transistor Q3 is turned on. At time Ts, the gating signal GQ4 applied to transistor Q4 is turned off and the gating signal GQ1 applied to transistor Tl is turned on. Thus, at time Ts, the same changes to the gating signals are created as performed at time Ti.

Accordingly, the transitions occurring at times Ti-T4 are repeated for times T5-T8, times Tg-Tl2, and subsequent equivalent time periods. In this manner, transistor Qi and transistor Q2 are never simultaneously gated; transistor Q l and transistor Q4 are not simultaneously gated; and transistor Q2 and transistor Q3 are not simultaneously gated. However, one of transistors Qi and Q4 are conductive at substantially all times.

Similarly, one of transistors Q2 and Q3 are conductive at substantially all times.

Figure 4 illustrates one embodiment of the switch control SC of the present invention. In Figure 4, signals A and B are pulse signals generated by control circuit CC of Figure 2. The control circuit CC of Figure 2 monitors the load or output voltage Vo across the load impedance RL and controls this output voltage to a desired voltage level by varying

the pulse width of pulse signals A, B, which in one preferred embodiment generally correspond to the transistor gate signals GQi, GQ2 of Figure 3.

In the Figure 4 embodiment, however, the pulse signals A and B obtained from the control circuit CC of Figure 2 are further processed by the switch control SC which is illustrated in further detail in Figure 4. The pulse signals A, B of the control circuit CC of Figure 2 are processed by the Figure 4 switch control to produce first and second primary transistor gating signals A", B". In the circuit of Figure 4, each of the input pulse signals A, B from the control circuit CC is supplied to a first delay circuit Dli including a resistor Ri and diode D3 in the case of the input signal A, and a second delay circuit D12 formed of a resistor R2 and diode D4 is connected to the input signal B from the control circuit CC. The outputs of these first and second delay circuits Dll, D12 are illustrated as delayed signals A'and B'of Figure 5. These delayed signals A', B'are supplied to a primary side drive buffer DB including first and second non-inverting buffer amplifiers Al, A2 to produce output signals A", B" which have the input thereof delayed a predetermined delay tdl, td3, respectively. Thus, the leading edges of the first and second primary transistor gating signals A", B" (also known as GQ1, GQ2) are delayed a time delay from the gating signals provided by the control circuit CC. The inputs A, B to the switch control SC are also provided to a primary coil Tr2P of a small signal transformer Tr2.

The small signal transformer Tr2 is provided with a primary coil Tr2p and split secondary coils Tr2Si, Tr2S2 including small signal transformer center tap CT2 which is connected to the local ground of the secondary circuit, GND2. The first and second small signal transformer secondary coils Tr2S1 and Tr2S2 output the pulse signals C, D which correspond to pulse signals A, B but which are fully isolated from the primary circuit portion P and the input voltage VIN. The pulse signal C is passed through a third delay circuit D13 including a third delay circuit

resistor R3 and third delay circuit diode Ds to produce an output signal C' having its trailing edge delayed.

The first and second delay circuits DLi and DL2 have the cathode of their respective diodes D3, D4 connected to the input signals A, B so that the leading edge of the pulses A, B will be delayed. In contrast, the third delay circuit DL3 utilizes the diode Ds with its anode connected to the first small signal transformer secondary of the small signal transformer TR2 so that the trailing edge of the pulse signal C will be delayed to form delay signal C', which is supplied to an inverting drive buffer IDB. Similarly, the second small signal transformer secondary coil TR2S2 produces a pulse signal D which is isolated from but otherwise identical to pulse signal B.

Because of the operation of a forth circuit delay DL4 with its delay resistor R4 and delay diode D6, the trailing edge of pulse signal D is delayed to produce delayed signal D'which is supplied to the inverting drive buffer IDB.

The inverting drive buffer IDB includes respective inverting buffer amplifiers lAi, IA2 which sharpen the delay edge and invert the delayed signals C', D' received thereby. Thus, signal C"and D", used to drive the first and second rectifying transistors Q3, Q4, have their leading edge delayed a predetermined time delay td2, td4, a delay standard from the trailing edge of control signals A, B. Since output signals A"and B"used to drive the first and second primary transistors Ql and Q2 also have their leading edges delayed a time delay tdl, tds, respectively, the output signal A"utilized to drive the first primary transistor Ql and the output signal C" utilized to drive the second rectifying transistor Q4 have conductive periods separated by the delay time tdl or td3, to prevent cross- conduction when Ql turns on and Q4 turns off, and when Q4 turns on and Ql turns off. Similarly, a delay is present between the output B"used to control the second primary transistor Q2, and the first rectifying transistor Q3, separating the conduction periods of these respective transistors by dead times td2 and td4.

The primary transistor gating signal generation circuitry including <BR> <BR> <BR> <BR> the first and second delays DL1, DL2 and the drive buffer DB are, in the embodiment of Figure 4 preferably driven by a voltage Vp derived from the primary circuit portion P of Figure 2. In order to fully isolate the secondary circuit portion, the third and fourth delays DL3 and DL4 as well as the inverted drive buffer IDB are driven by a voltage Vs derived from the secondary circuit portion S of the circuit of Figure 2 as already explained. Since the gating signals are derived from signals C, D supplied through the small signal transformer TR2, full isolation is thereby obtained.

Figure 6 illustrates an alternative embodiment of the present invention where a full wave bridge primary circuit portion P is utilized in a double ended converter employing the techniques of the present application.

The circuitry of Figure 6 differs from that of Figure 2 in two primary respects. Firstly, the primary circuit portion P of the circuit of Figure 6 employs a full-wave bridge primary circuit. In such a full-wave bridge primary circuit, the voltage VIN is connected across a primary circuit filtering capacitor C5. The voltage VIN is further applied across a pair of serially connected switches Q2A, Qls and further connected across a pair of serially connected switches QlA, Q2B. The primary coil TRip of the primary isolation transformer TRi is connected, at one terminal thereof, to the <BR> <BR> <BR> <BR> interconnection between transistor QIA and Q2B, and at another terminal thereof, to the point at which transistor Q2A and transistor QiB are connected. In the circuit of Figure 6, the signal GQ1 of Figure 3 or the <BR> <BR> <BR> <BR> signal A"of Figure 5 may be connected to QiA and Q1B while the signal GQ2 or the signal B"of Figures 3 and 5 respectfully may be connected to transistors Q2A, Q2B. In this fashion, current through the isolation transformer TRi may be alternatingly generated through the conduction of <BR> <BR> <BR> <BR> the QiA, QiB transistor pair, and the subsequent conduction of the Q2A, Q2B transistor pair.

Figure 6 also illustrates an alternative methodology for generating the secondary control supply voltage Vs, which in this embodiment is obtained between the center tap CT and either the first secondary coil of the isolation transformer TRiSi or the second secondary coil TRiS2 of the isolation transformer TRi through either of the bias current collection diodes D7-1, D7-2 to derive the secondary control voltage Vs across the bias voltage capacitor C4. Figure 6 illustrates the secondary control supply voltage Vs being obtained from the output of both of the secondary coils TRiSi, TRiS2 as this ensures that the secondary circuit of the DC-DC converter of the present application remains balanced. However, it is possible to derive the secondary control supply voltage Vs from either of the secondary coils TR1S1, TR1S2 of the isolation transformer TRi.

Description of Operation In relatively low voltage DC-DC down converters, it is highly preferable to utilize synchronously gated switches Q3, Q4 of Figure 2 in place of rectifying and fly-back diodes. Such transistors Q3, Q4 may be constructed in any suitable fashion. In the preferred embodiment, MOS- FETs are utilized. Such transistors exhibit a forward voltage drop of about . 1 volt when conductive and thus, when gated in accordance with the signals of Figure 3 or Figure 5 of the present application, provide a DC-DC converter having improved power transfer efficiency.

While the use of such synchronously switched rectification is known in circuits with a voltage doubler secondary, such a voltage doubler secondary could not easily provide full current isolation between the primary circuit portion P and the secondary circuit portion S.

However, the use of full-wave rectification in the secondary circuit portion S as illustrated in Figure 2, in conjunction with the use of the split isolation transformer secondary including first isolation transformer secondary coil TRiSi and second isolation transformer secondary coil TRi S2 provides a voltage in the secondary circuit portion of a level needed

to drive the secondary gating portions SG of the switch control SC. Thus, obtaining a secondary control supply voltage Vs to drive the secondary gating portions SG is more easily accomplished in such a full-wave conversion secondary where a split secondary coil of the isolation transformer TRi including transformer secondary coils TRiSi and TRlS2.

Consequently, the employment of a full-wave secondary circuit of Figure 2 is desirable when using control gated switches to rectify the output of the isolation transformer TRi in the secondary circuit portion S.

Figure 2 is an example of such a circuit employing a full wave rectified secondary in a D. C.-D. C. down converter with a fully isolated secondary. By replacement of the first and second rectifying and fly-back diodes Di, D2 of Figure 1 with the first and second rectifying transistors Q3, Q4 of Figure 2, substantially improved power transfer efficiency is exhibited through elimination of the forward voltage drop of approximately . 3 volts inherent in the Schottky diodes.

The first and second rectifying transistors Q3, Q4 are controlled by the switch control SC which is also used to control the transistors Ql, Q2.

Basically, transistors Qs, Q4 are controlled to be on at those times at which the first and second rectifying and fly-back diodes Dl, D2 would be forward biased. Thus, the switch control produces gate signals GQi, GQ2 to be supplied to the first and second primary transistors Qi, Q2 to render them conductive at substantially the same times that diodes Dl, D2 conduct in the Figure 1 circuit.

The switch control SC of Figure 2 produces gate signals for the first and second rectifying transistors Q3, Q4 which gate signals GQ3, GQ4 are also illustrated in the timing diagram of Figure 3. Thus, transistor Q3 is turned on by the gate signal GQs at times in which the transistor Ql is gated by the gate signal GQi. Similarly, the transistor Q4 is gated on by gate signal GQ4 at the same time that transistor GQa is gated by gate signal GQ2. At times when neither transistor Ql or Q2 is conductive, both transistors Q3 and Q4 are conductive to produce a fly-back phenomenon,

transferring the energy from the filtering or smoothing inductor Li to the load RL. Note that it is important that transistor Q4 never conduct while <BR> <BR> <BR> <BR> transistor Q1 is conducting and transistor Q3 never conduct when transistor Q2 is conducting. This is because such simultaneous conduction will cause cross-conduction between the primary and secondary via the power transformer thereby causing output current to flow via the body-drain diodes of the secondary switches, causing a significant increase in power loss. Accordingly, it is important to ensure that transistor Q3 is not conductive at the same time as transistor Q2 and that transistor Q1 is not conductive at the same time as transistor Q4.

The circuit of Figure 2 additionally schematically discloses a control circuit CC which monitors the output supply voltage Vo and changes the <BR> <BR> <BR> <BR> duty cycle or conduction period of transistors Qi, Q2 in order to maintain the output supply voltage Vo at a desired voltage. While this technique is well known in the art, the duty cycle or conduction period of transistors <BR> <BR> <BR> <BR> Qi, Q2 is increased to increase the output supply voltage Vo, and decreased to decrease the output supply voltage Vo.

Desirably, according to the teachings of the present application, small delays should be inserted between the conduction periods of the primary and secondary transistors. Figure 4 of the present application illustrates an exemplary switch control SC employing such delays, while Figure 5 illustrates the timing within the switch control SC of Figure 4. In the switch control embodiment of Figure 4, the leading edges of the <BR> <BR> <BR> <BR> conduction periods of both the first and second primary transistors Qi, Q2 and the first and second rectifying transistors Q3, Q4 are delayed a small amount (the dead time TD1-TD4) to ensure"brake before make"action <BR> <BR> <BR> <BR> within the control of the first and second primary transistors Q1, Q2 and first and second rectifying transistors Q3, Q4. This"brake before make" action prevents cross-conduction between the primary and secondary across the power transformer. These delays should be either calculated or determined empirically to ensure sufficient"brake before make"action

without substantially decreasing converter efficiency due to body-drain conduction in the secondary switches. In other words, the delay between the turn-off of the first and second primary transistors Ql, Q2 and the turn-on of the first and second rectifying transistors Q3, Q4 should be sufficiently small to prevent the inherent body-drain diode in the MOS- FETs from conducting.

In the circuit of Figure 4, pulse width primary gating signals (pulse signals) A, B are supplied by the control circuit CC in a manner which is well known in the art. Such pulse signals A, B are pulse width modulated to produce the desired output supply voltage Vo out of the converter.

Delay circuits DLl, DL2 respectively delay the leading edges of gating signals A, B to produce delayed signals A', B' with ramped leading edges.

The drive buffer DB employs a pair of drive buffer amplifiers Al, A2 which produce a drive signal once a predetermined threshold is exceeded. Since the leading edge of signals A', B' is ramped, the gating signals A", B" (GQl, GQ2) applied to the first and second primary transistors Ql, Q2 have leading edges which are time delayed a valued tdl, tds as illustrated in Figure 5.

The primary gating signals A, B developed under control of the control circuit CC are also supplied to a small transformer TR2, and in particular, to the primary winding TR2P thereof. The split secondary windings TR2Sl, TR2S2 of the small signal transformer TR2 produce isolated pulse signals C, D which are substantially identical to A, B. Each of these pulse signals C, D is trailing edge delayed by third and fourth delay circuits DL3, DL4 to produce delayed signals C', D'. The ramp edge of the trailing edge delayed signals C', D', insures that the threshold of the inverted drive buffer IDB and its amplifiers IAi, IA2 will delay the trailing edge of the respective inverted signals C', D', thereby producing first and second secondary rectifying transistor drive signals C", D" (GQ4, GQ3) which are in turn supplied to the first and second rectifying transistors

Q3, Q4. Thus, the exemplary circuit of Figure 4 adds dead times tdi-td4 to the gating signals, to produce a"brake before make"action preventing undesired cross-conduction between the primary and secondary via the power or isolation transformer TRi.

Figure 2 of the present application further illustrates a control circuit CC which produces the control signals A, B in response to the monitored output voltage Vo. As is apparent to one of ordinary skill in the art, the control signals A, B increase in pulse width as an increase is desired in the output voltage Vo. Preferably, the control circuit CC is supplied power Vp from the primary circuit portion P.

The outputs A, B may be generated in accordance with Figure 3 to provide desired gating signals to the first and second primary transistors Q1, Q2 and the first and second rectifying transistors Q3, Q4. Desirably, however, signals GQl-GQ4 are produced by utilizing the circuit of Figure 4 in conjunction with the timing diagrams of Figure 5. In the circuit of Figure 4, the first and second delays DLl, DLa delay the leading edge of the control signals A, B, to delay the beginning thereof. These signals are then amplified by the first and second amplifiers Al, A2 which are powered by the primary circuit supply voltage Vp.

One important objective is to fully isolate the secondary circuit portions of the D. C.-D. C. converter from the primary voltage supply. To accomplish this, the small signal transformer TR2 isolates the control signals A, B, from the secondary switch gating portions SG. The inverting drive buffer IDB which is supplied power by the secondary control supply voltage Vs inverts signals C', D' and sharpens their trailing edge to produce GQ3 and GQ4, the gating signals for the first and second rectifying transistors, which are produced at the output of the inverted drive buffer IDB. All items of the Figure 4 circuit on the secondary side of the small signal transformer TR2 are fully isolated. Accordingly, this portion of the switch control SC is not powered by the primary side circuit portion P.

Since the circuit of Figure 2 may easily obtain a secondary control supply voltage Vs without the need of a voltage divider or other voltage step down circuitry, the circuit of Figure 2 exhibits not only improved efficiency over a diode rectified DC-DC converter, but further the synchronous switches or rectifying transistors Q3, Q4 may be driven by gating circuitry which is powered by the secondary circuit portion, thereby ensuring full isolation of the converter secondary and it's load.

Figure 6 of the present application illustrates an alternative embodiment of the present application which utilizes a full-bridge primary structure. Such full-bridge primary structures are well known and the bridge transistors QlA, Qls or alternatively Q2A Q2B are simultaneously conductive. These transistor pairs may be gated by the signals GQ1, GQ2 produced at the output of the circuit of Figure 4 in the manner described above. Thus, the secondary of the circuit of Figure 6 operates in the same fashion as the circuit of Figure 2 of the instant application.

Additionally, in the Figure 6 circuit, the secondary control supply voltage Vs is derived directly from the voltage across one or both of the rectifying transformer TRi first and second secondary windings TRiSi, TRlS2. Consequently, Figure 6 illustrates first and second secondary control supply voltage diodes D7-1, D7-2 which produce the desired secondary control supply voltage Vs across a secondary control supply voltage filtering capacitor C7. While Figure 6 shows this secondary control supply voltage Vs being obtained from both of the two isolation transformer secondary coils TRlSl, TRlS2, it should be clear that either of these two secondary coils may be used to access this secondary control supply voltage Vs. However, there are advantages to obtaining this voltage from both transformer secondary coils, as transformer imbalance does not then occur.

It should be understood that the foregoing embodiments are exemplary for the purpose of teaching the inventive aspects of the present

application, which inventive aspects are covered solely by the appended claims and encompass all variations not regarded as a departure from the spirit of the scope of the invention. All such modifications as would be obvious of ordinary skill in the art are intended to be included within the scope of the following claims.