Title:
DOUBLE SIDE POLISHING METHOD FOR WAFERS, EPITAXIAL WAFER MANUFACTURING METHOD USING SAME, AND EPITAXIAL WAFERS
Document Type and Number:
WIPO Patent Application WO/2017/110262
Kind Code:
A1
Abstract:
[Problem] To provide a carrier for double side polishing that allows a desired edge roll-off to be formed intentionally during double side polishing of a wafer and a wafer polishing method using same, and a manufacturing method for epitaxial wafers that can manufacture epitaxial wafers that have increased flatness on the back face by using wafers on which a double side polishing treatment of this sort has been implemented. [Solution] A carrier 10 for double side polishing disposed between a top platen 2 and a bottom platen 3 on each of which a polishing cloth 4, 5 is attached and comprising a retaining hole 10a for holding a wafer W that is sandwiched between the top platen 2 and the bottom platen 3, wherein a chamfer 12c is formed on at least one of the top corner and the bottom corner of the retaining hole 10a. In addition, an epitaxial silicon wafer is manufactured using a silicon wafer manufactured using the carrier 10 for double side polishing.
Inventors:
KIDO RYOSUKE (JP)
Application Number:
PCT/JP2016/082764
Publication Date:
June 29, 2017
Filing Date:
November 04, 2016
Export Citation:
Assignee:
SUMCO CORP (JP)
International Classes:
B24B37/28; H01L21/304
Domestic Patent References:
| WO2006001340A1 | 2006-01-05 |
Foreign References:
| JP2012109310A | 2012-06-07 | |||
| JPH07156062A | 1995-06-20 | |||
| JP2015104771A | 2015-06-08 |
Attorney, Agent or Firm:
WASHIZU Mitsuhiro et al. (JP)
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