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Title:
DOUBLING OF SPEED IN CMOS SENSOR WITH COLUMN-PARALLEL ADCS
Document Type and Number:
WIPO Patent Application WO2003017648
Kind Code:
A3
Abstract:
An imaging system features high speed digitization of pixel signals by utilizing top and bottom digitization circuits which pipeline sample-and-hold operations with analog-to-digital conversion. In operation, while one digitization circuit is performing a sample-and-hold operation, the other digitization circuit is performing analog-to-digital conversion. The speed of the imaging system may be further increased by pipelining and interleaving operations within the top and bottom digitization circuits by using additional sets of sample-and-hold circuits and analog-to-digital converters.

Inventors:
HANSON ERIC
KRYMSKI ALEXANDER
POSTINIKOV KONSTANTIN
Application Number:
PCT/US2002/026061
Publication Date:
May 01, 2003
Filing Date:
August 16, 2002
Export Citation:
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Assignee:
MICRON TECHNOLOGY INC (US)
International Classes:
H01L27/146; H04N5/335; H04N5/341; H04N5/374; H04N5/378; (IPC1-7): H04N5/335
Foreign References:
US6115065A2000-09-05
Other References:
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 16 8 May 2001 (2001-05-08)
KRYMSKI A ET AL: "A HIGH SPEED, 500 FRAMES/S, 1024 X 1024 CMOS ACTIVE PIXEL SENSOR", 1999 SYMPOSIUM ON VLSI CIRCUITS. DIGEST OF TECHNICAL PAPERS. KYOTO, JUNE 17 - 19, 1999, SYMPOSIUM ON VLSI CIRCUITS, NEW YORK, NY: IEEE, US, vol. CONF. 13, 17 June 1999 (1999-06-17), pages 137 - 138, XP000894787, ISBN: 0-7803-5441-9
TORELLI G ET AL: "Analog-to-digital conversion architectures for intelligent optical sensor arrays", ADVANCED FOCAL PLANE ARRAYS AND ELECTRONIC CAMERAS, BERLIN, GERMANY, 9-10 OCT. 1996, vol. 2950, Proceedings of the SPIE - The International Society for Optical Engineering, 1996, SPIE-Int. Soc. Opt. Eng, USA, pages 254 - 264, XP008010312, ISSN: 0277-786X
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