Title:
DRAM ASSIST ERROR CORRECTION METHOD USING DDR SDRAM INTERFACE
Document Type and Number:
WIPO Patent Application WO/2023/106434
Kind Code:
A1
Abstract:
Provided is a method for correcting a memory error of a dynamic random-access memory module (DRAM) by using a double data rate (DDR) interface. The method comprises the steps of: performing a memory transaction including multiple bursts with a memory controller in order to transfer data from data chips of the DRAM to a memory controller; detecting one or more errors using an ECC chip of the DRAM; determining the number of the bursts having the errors, by using the ECC chip of the DRAM; determining whether the number of the bursts having the errors is greater than a threshold number; determining a type of the errors; and providing an instruction to the memory controller on the basis of the determined type of the errors, wherein the DRAM includes one ECC chip per memory channel.
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Inventors:
BYUN GYUNG SU (KR)
Application Number:
PCT/KR2021/018371
Publication Date:
June 15, 2023
Filing Date:
December 06, 2021
Export Citation:
Assignee:
DEEP I INC (KR)
International Classes:
G11C29/42; G06F3/06; G06F11/10; G11C11/4096
Foreign References:
| KR20180019473A | 2018-02-26 | |||
| KR20210055793A | 2021-05-17 | |||
| KR20190049710A | 2019-05-09 | |||
| KR20090118031A | 2009-11-17 | |||
| KR20160030978A | 2016-03-21 |
Attorney, Agent or Firm:
SEO, Pyeong Gang (KR)
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