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Patent Searching and Data


Title:
DRAM CELL MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/177287
Kind Code:
A1
Abstract:
A memory device is disclosed. The memory device comprises: a columnar semiconductor including a source region, a body region, and a drain region; a gate insulating layer formed so as to surround the surface of the columnar semiconductor; and a gate formed on a surface of the gate insulating layer such that at least a part of the region is located in a region corresponding to the body region, wherein the body region is doped with a first type of dopant at a predetermined concentration to store holes by tunneling with the drain region, the source region is formed on one side of the body region such that the first type of dopant is doped at a concentration higher than the predetermined concentration, and the drain region is formed on the other side of the body region such that the first type of dopant is doped at a concentration higher than the predetermined concentration.

Inventors:
KANG IN MAN (KR)
YOON YOUNG JUN (KR)
Application Number:
PCT/KR2019/002379
Publication Date:
September 19, 2019
Filing Date:
February 27, 2019
Export Citation:
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Assignee:
KYUNGPOOK NAT UNIV IND ACADEMIC COOP FOUND (KR)
International Classes:
H01L29/78; H01L27/108; H01L29/06; H01L29/423
Foreign References:
KR101091010B12011-12-08
KR20100094732A2010-08-27
KR101085155B12011-11-18
KR20060114991A2006-11-08
Other References:
ANSARI, HASAN RAZA ET AL.: "Doping Dependent Assessment of Accumulation Mode and Junctioniess FET for IT DRAM", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 65, no. 3, 23 January 2018 (2018-01-23), pages 1205 - 1210, XP055641186
Attorney, Agent or Firm:
KIM, Tae-hun (KR)
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