Driver for LED or OLED Display and Drive Circuit

Field of the Invention

The present invention pertains to the field of displays for example solid state fixed format displays such as discrete light emitting LED or OLED displays, as well as methods of making or operating such displays, as well as optionally a controller and software for executing such methods. In particular the present invention relates to a control or drive circuit and method for a pixel or subpixel of an active LED or OLED display.

Discussion of the prior art

The problem of achieving High Dynamic Range displays and light emitting devices is known from the art.

US6987787B1 describes a LED brightness control system for a wide-range of luminance control. The brightness of Light Emitting Diodes, used as backlighting for a Liquid Crystal Display, must be controlled over a range of at least 20000 to 1. US6,987,787B1 describes a LED control system wherein the duty cycle of a PWM signal is modulated at the same time as the amplitude of the current pulses. Encoding the duty cycle with 8 bits and the amplitude of the current pulses with 8 bits as well would give a total of 65,536 brightness range.

The modulation of both the duty cycle and the amplitude of the current pulses of the PWM signal would allow smaller brightness steps at the lower brightness level and larger brightness steps at the higher brightness levels.

US6,987,787B1 remains silent on how to address at the same time a bandwidth constraint (which would require encoding brightness on less than 16 bits) while maintaining the ability to control the brightness over a range of at least 20000 to 1. Problems associated with the stability of the color point, which varies with the amplitude of the current pulses in the LED also remain.

In US8,339,053 a “LED dimming apparatus” is described which makes use of two dimming regimes to control the brightness of a LED lighting device.

In a first “lower brightness” regime, the current flowing through a LED is pulse width modulated with constant current pulse amplitude. In a second “higher brightness” regime, the current flowing through the LED is controlled in analog fashion and is not pulsed. The current flowing through the LED is continuous and its amplitude is determined by a constant current circuit.

US8,339,053 does not offer a viable solution to drive individual LEDs of a LED display. US8339053 does not discuss the problem of visual artefacts and in particular color artifacts that are bound to exist when driving LEDs at different current amplitudes.

EP1846910B1 “Active matrix organic light emitting diode display” discloses how an active matrix OLED display can be dimmed with a PWM signal common to all pixels while avoiding color artifacts.

Figure 1 which corresponds to figure 3 of EP1846910B 1 shows an example of circuit that can be used to dim the light emitted by a light emitting diode with a PWM signal without affecting the color point. A transistor (element 310 on figure 3 of EP1846910) can be switched on and off by a PWM signal applied to its gate. When the transistor is open, no current can circulate through the OLED 308 and no light is emitted. When the transistor is closed, a current IOLED can circulate through the OLED 308 and light is emitted. The amplitude of the current is determined by a.o. the voltage applied to the gate of transistor 304. Since the same PWM signal is applied to each pixel of the display, there is no issue with bandwidth. An analog signal (to be loaded across the capacitor 306) is still required to “program” the luminance of the (sub-)pixel corresponding to OLED 308.

US2018/0197471A1 “Digital-drive pulse-width-modulated output system” discloses an active-matrix digital-drive display system that includes an array of pixels. Each pixel has an output device, a serial digital memory responsive to a load timing signal for receiving and storing a multi-bit digital pixel value during an uninterrupted load time period, and a drive circuit responsive to a pulse- width-modulation (PWM) timing signal and to the multi-bit digital pixel value stored in the serial digital memory to drive the output device during an uninterrupted output time period.

Digital storage is not practical for conventional flat-panel displays that use thin-film transistors because the thin-film circuits required for digital pixel value storage are much too large to achieve desirable display resolution. US2018/0197471A1 solves this problem with small micro transfer printed integrated circuits (chiplets) having a crystalline semiconductor substrate and that provide small, high-performance serial digital memory circuits and temporally controlled constant-current LED drive circuits in a digital display with practical resolution. Such a display can have excellent resolution because the chiplets are very small. The solutions disclosed in US2018/0197471A1 are not applicable for high resolution displays if chiplets are not available. An example of circuits according to US2018/0197471A1 is given in figure 2.

Another problem in the prior art is the load time period as disclosed in US2018/0197471A1. Indeed, let us take as an example a display tile with 160*135 LEDs. If the frame rate is 60 frames per second, sending e.g. 12 bits to 15 bits to the memory associated to each pixel must be done in less time than the PWM sub-period for the least significant bit bo (in order to avoid visual artefacts). Ideally, this should be done sequentially in order to limit the number of signal tracks that carry the signals to the pixels.

If the PWM signal is encoded with 15 bits or more, the PWM timing period for the least significant bit bo would have to be less than 0.5 ps. Loading every serial memory of the 160*135 pixels in less than 0.5 ps is not easy.

Applying the teachings of US 2018/0197471 A 1 is appealing but appears unfeasible without using chiplets.

The art needs improvement.

Summary of the inventions

Embodiments of the present invention provide a current control or driver circuit for discrete light sources such as solid states light source of which LED or OLED sub-pixels or pixels of an active matrix display are an example whereby there is a memory to store bits or a bit of a control signal used to drive a pixel or sub-pixel, as well as a method to drive said circuit. The light sources are driven by a control signal such as a Pulse Width Modulated signal of a certain bit-depth whereby the memory for storing the bits or bit of the PWM control signal, stores a lower number of bits than the bit-depth of the control signal such as the PWM signal.

An advantage of embodiments of the present invention is that the control circuit elements can be made compatible with thin-film processing such as to produce thin-film transistors. Another advantage of embodiments of the present invention is that a control circuit or driving for controlling the light output of light sources such as LEDs or OLEDs advantageously does not impose a limitation to the resolution (or pixel pitch) of light sources of a LED or OLED display. This I because of the compact design. Yet another advantage of embodiments of the present invention is that the control circuit is fast enough to be compatible with a given frame rate and number of bits used to encode a PWM signal.

Hence, embodiments of the present invention provide a current control or drive circuit for light sources comprising LED or OLED pixels of an active matrix display. The components of the current control or drive circuit and how they are connected are shown particularly in Figures 14A, 14C, 15, and 17 and 22 to 27 In the current control or drive circuit:

A first storage element such as a capacitor or a capacitor circuit of which a Sample and Hold device with a capacitor is an example, is provided to control current in a light emitting element such as a LED or OLED of a subpixel or a pixel for use in an active matrix display. A capacitor, when it stores a value such as required for a bit in a one-bit memory, makes this value available to the circuit on one of its electrodes. Instead of a capacitor, other elements with the same function such as a bistable memeory element can be used such as an unclocked Flip-Flop.

Further a memory element to store the next bit or bits of a control signal such as a PWM control signal is also provided. The number of bits stored in the memory element is less than the bit depth of the control signal such as the PWM control signal. The memory element is preferably a one-bit, two-bit or multibit clocked bistable element such as a clocked Flip-Flop or clocked Flip-Flops.

The driver circuit or current control circuit can also comprise: a control element with a first control electrode, configured to control flow of current through the light emitting element such as the LED or OLED for a pixel or subpixel of an active display.

The control element can be a transistor such as a pMOS transistor and is preferably a thin film transistor. nMOS transistors can also be used or a combination of pMOS and nMOS transistors whereby the transistor or all the transistors may be and preferably are thin film transistors. The control electrode can be the gate of such a transistor or transistors. The light emitting element can be part of a pixel, a sub-pixel or a complete pixel. The current through the light emitting element can be controlled by the voltage placed on the gate of the transistor or transistors.

A second storage element can be a memory element provided to store a second value of the control signal. The second storage element can be a logic element such as a one -bit, two-bit or multibit memory provided the number of bits is less than the bit depth of the control signal such as the PWM signal. For example, the second storage element can be a capacitor in combination with a transistor or a clocked flip-flop or a device which has the same truth table as a flip-flop. Hence, generally it can be a clocked bistable element.

The current control or drive circuit can include a transfer element such as a switch. The transfer element or switch can be a transistor such as a pMOS transistor preferably a thin film transistor or it can be a transistor circuit configured to be a switch. An nMOS transistor or an nMOS transistor circuit or a combination of nMOS and PMOS transistors can be used.

The transfer element can have a second control electrode to load the first storage element with a second value of the control signal, wherein the number of bits stored by the first storage element and/or the second storage element is less than a bit-depth of a resolution of the control signal such as a PWM control signal.

An advantage of embodiments of the present invention is that the elements of the current control or drive circuit can be made in the same technology e.g. the storage elements such as any memory element is made in the same technology, as switches implemented as transistors connected to the light emitting element such as an LED or OLED. In particular this same technology can be thin-film processing (TFT). By these means, a compact design can be achieved.

Embodiments of the present invention provide a current control or driver circuit for discrete light sources such as solid-state light source of which LED or OLED sub-pixels or pixels are examples, e.g. of an active matrix display. The current control or driver circuit can comprise: a memory to store bits or a bit of a control signal such as a PWM control signal used to drive a pixel or sub-pixel of the active matrix display, as well as a method to drive said circuit. The light sources can be driven by a Pulse Width Modulated control signal of a certain bit-depth whereby a memory of each pixel or sub-pixel for storing the bits or bit of the PWM control signal, stores a lower number of bits than the bit-depth of the PWM signal.

The current control or drive circuit can be adapted to load a next bit while a current bit is being used to control the current in a light source such as the LED or OLED, i.e. control of current therefore controls light output.

The memory can be a single bit memory to store just the next bit or can be multibit provided the number of bits is less than the bit depth of the control signal such as a PWM control signal. The active matrix display can include an array of pixels or sub-pixel light emitting elements arranged in rows and columns. The memory e.g. a clocked bistable device, can be part of a column wide shift register.

The length of time a control bit is used gives the width of a control signal sub-period such as a PWM sub-period associated to that bit. As explained below, for bits b-1 and b-2, it means that since TO cannot be decreased, the value of the bit can be overridden by use of a reset signal. For b-1, the length of time is made TO/2 by overriding b-1 between time TO/2 until time TO, For b-2 the length of time is made TO/4 by overriding b- 1 between time TO/4 and time TO (the reset signal (RST signal) erases the bit b-1 or b-2 before the end of the interval TO).

In an embodiment of the present invention, a circuit to control the current in a Light Emitting Element such as an LED or OLED is provided that comprises: a control element with a first control electrode, to control the flow of current through the light emitting element; a first storage element to store a first value of a control signal, said control signal being applied to the first control electrode of the control element; a second storage element to store a second value of a control signal; a transfer element with a second control electrode to load the first storage element with the second value of the control signal. In the circuit the control element, the first storage element, the second storage element and the transfer element such as a transistor can be realized with the same thin film transistor technology.

It is an advantage of that embodiment and other embodiments of the present invention that it is possible to load a second control voltage on the second storage element while the first control voltage is applied to the control electrode of the control element to control the current in the light emitting element. There is thus no “dead time” during which the light emitting element remains idle because no data is available to control it.

It is an advantage of embodiments of the present invention that it is possible to control the control element with an arbitrarily large number of sequential bits even though the second storage element can only store a limited number of bits at a time, e.g. one bit or two bits. In particular, the second storage element can store a number of bits which is less than the number of bits comprising the bit depth of the PWM signal used to drive the pixels.

More in particular, the second storage element stores a single bit or two bits or can be multibit storage element.

This is of particular importance when the current in the light emitting element is controlled by a pulse width modulation scheme (PWM), the required pulse width modulation being encoded as a string of bits that can be applied sequentially one at a time to the control electrode of the control element.

Limiting the size of the storage for the bits that are sequentially controlling the control element makes it possible to realize high density arrays of current control circuits, with a reduced pixel or sub-pixel pitch (i.e. the spatial period of the array of pixels or sub-pixels is reduced).

The first control element can be a switch that conditionally connects a current source with the light emitting element or. The first control element controls how current from the current source can reach the light emitting element. The first control element can be in series with the light emitting element or in parallel. When in parallel it bypasses the light emitting element which prevents the light emitting element from being driven on unless the first control element is open, i.e. non-conducting. The first control element can be a transistor (e.g. a pMOS transistor) and the first control electrode can be the gate of said transistor or said pMOS transistor. This transistor such as the pMOS transistor can be a thin film transistor. nMOS transistors or pMOS or nMOS transistor circuits could be used.

The first storage element can be a capacitor with its first electrode connected to the first control electrode of the first control element and its second electrode connected to a reference node, in particular a supply node. A capacitor, when it stores a value such as when it acts to hold a bit in a one -bit memory, makes this value available to the circuit on one of its electrodes immediately. Instead of a capacitor, other elements with the same function such as a bistable memory element can be used such as an unclocked Flip-Flop.

The transfer element can be a transistor like a pMOS transistor. The transistor can be a thin film transistor such as a thin film pMOS transistor. nMOS transistors or pMOS or nMOS transistor circuits could be used.

The second storage element can be a capacitor and a transistor or another programmable memory such as a single or multibit memory such as a flip-flop or flip-flops. The second storage element is preferably clocked. The multibit memory can store a number of bits less than the bit depth of the control signal such as the PWM control signal.

In an alternative embodiment, the first storage element can be a programmable memory such as a single or multibit memory, e.g. a flip-flop or flip-flops as well. Such a flip-flop is preferably not clocked.

In another aspect of the invention, the control signal applied to the control electrode of the first control element by means of the first storage element, can be overridden.

Overriding the control signal stored on the first storage element can be done by means of a switch that conditionally connects the control electrode to an alternative control signal.

When the first storage element is a capacitor, the switch can be a reset switch that shunts the first storage element. The reset switch can alternatively shunt the light emitting element. The switch can be a transistor and in particular a pMOS transistor. This transistor or the pMOS transistors can be a thin film transistor. In another embodiment of the present invention, a current control or drive circuit according to embodiments of the present invention is used to drive a display. The display can be e.g. a solid-state light source display such as a LED display or an OLED display.

Current control or drive circuits according to embodiments of the present invention and the light emitting element they drive can be disposed in lines and columns, i.e. in an array. Each of the L lines of the array has M current control or drive circuits and their associated light emitting elements.

A second storage element of each circuit in the same column (or line) can be connected to the same data signal line and a second storage element of each circuit in the same line (or column) can be connected to the same scan line. A signal applied to the scan line enables the storage of the signal present on the data signal line. The scan line can for instance control a switch that conditionally brings the data signal line and the second storage element in electrical contact.

Alternatively, the second storage element of each circuit in the same column (or line) can be part of a column wide (or line wide) shift register. The shift register can be realized with thin film transistors together with the thin film transistors of the current control circuit. It is an advantage of that aspect of the invention that it simplifies the routing of data and control signals to the current control circuits.

In another aspect of the invention, a method is provided to update the content of the second storage element while the content of the first storage element is used to control the current in the light emitting element. Each of the bits meant for the second storage element of a current control or drive circuit in the same column (or line) in an array of current control circuits can be applied sequentially to the input of a second storage element such as a one-bit, two-bit or multibit memory element such as a first flip flop in the column (or line) of current control circuits.

To update the second storage element of the current control or drive circuits in a column (or line), N bits are presented sequentially at the input of the column (or line) wide shift register and shifted through the shift register by clocking the shift register with a series of N first clock signals. The content of the second storage element is then transferred to the first storage element.

It is an advantage of that aspect of the invention that the first storage elements of the current control or drive circuits in the same column (or line) are updated at the same time. Alternatively, the update is done for the entire array at the same time.

In yet another aspect of the invention, the shift registers of adjacent arrays are daisy chained.

An advantage of an aspect of the invention is that it simplifies the tiling of light emitting arrays as in tiled displays. In particular, no or little modification of the circuitry to control those arrays is necessary.

In another aspect of the invention, a method to drive the control circuit of a light emitting element involves the step of:

Transferring a control signal from a second storage element to a first storage element Controlling the current in the light emitting element in function of said control signal, whereby the control signal is stored on a first storage element

Loading the second storage element with another control signal while the current in the light emitting element is controlled by the previous control signal.

In another aspect of the invention, a method is provided to modulate the current in a Light Emitting Element in function of N1 bits + N2 bits, the N2 bits having less weight than the N 1 bits; the method comprising the steps: o For each of the Ni bits, the current in the light emitting element is controlled by said Ni bits, one at a time and during a time interval with a duration of at least TMin; o For each of the N2 bits, the current in the light emitting element is controlled by said N2 bits, one at a time and during a first time interval that is less than T _MUI and overriding said one of the N2 bits during a second time interval that is less than T _Min the sum of the duration of the first time interval and the second time interval being equal to T _Min.

It is an advantage of that aspect of the invention that the total number of bits N = NI + N2 can be modified (and in particular increased) without having to modify the duration T _Mi . The N1 + N2 bits can encode the amplitude of the current in the light emitting element.

The current can for instance be Pulse Width Modulated, in which case, the N1 + N2 bits can encode the duty cycle of the PWM signal that will determine the average value of the current during a period T of the PWM signal.

The duty cycle can be encoded with N = N1 + N2 bits with N1 > 1 and N2 > 0. N2 is preferably smaller than N1 in order to limit a non-linearity or an error between the bit code (i.e. the integer number represented by the bits N1 + N2) and the average current circulating in a light emitting element such as a light emitting diode, the average being computed over a period T of the PWM signal.

The duration T _MUI of the time interval can be the duration of the current pulse (within the PWM period) corresponding to the PWM Sub-Period of the bits with the least weight among the N1 bits. The entire sequence of bits can control the current during a time interval equal to (2 ^N _I - l)*T _Min + N2*T _MUI after which the current in the light emitting element can be controlled / determined by another sequence of bits.

It is an advantage of the invention that it can limit the number of electrical tracks to carry signals to a light emitting element and its current controlling circuit in an array of light emitting elements.

The bits can for instance be shifted through a column- wide or line-wide shift register in an array of C column and L line of light emitting elements. The time required to shift a bit from the input of the shift register to its end can determine the time interval T _MHI .

Brief Description of the Figures

These and other technical aspects and advantages of embodiments of the present invention will now be described in more detail with reference to the accompanying drawings, in which: Figure 1 shows a schematic drawing of an active matrix pixel driver circuit according to the art wherein the PWM signal is used for dimming.

Figure 2 shows a schematic drawing of an active matrix pixel driver according to the art with banking, wherein the PWM is applied bit per bit during successive PWM timing periods, the bits encoding the PWM signal being stored in a serial memory. Figure 3 shows an active matrix LED array according to the art.

Figure 4 shows an example of a rectangular pulse wave as can be used with pulse-width modulation. The pulse width of a rectangular pulse wave is modulated resulting in the variation of the average value of the waveform.

Figure 5 shows how one period T can be divided into 4 sub-pulses SP1, SP2, SP3 and SP4 that have been distributed across one period. Depending on the application, it may be desirable to divide one period in more than 4 intervals.

Figure 6 shows the pulse width modulated signal when the duty cycle is set at its minimum value T _ci / T.

Figure 7 shows how, if the duty cycle is further increased compared to Figure 6 e.g. by 3 T _ci / T, the pulse P can be split in two or more sub-pulses, each sub-pulses taking place in one of the intervals (or bitblocks) in which the period T has been divided.

Figure 8 shows an example of PWM sub-periods for a PWM duty cycle encoded with 4 bits bO, bl, b2 and b3 (with bO the LSB and b3 the MSB). In this example, the period T of the PWM signal has been divided in four sub-periods or four PWM time intervals To, Ti, T2, T3 such that T = To+ Ti + T2 + T3.

Figures 9 and 10 show how the PWM time periods can be split instead of being uninterrupted. Figure 9 shows an example of PWM signal encoded on 4 bits with bo = 0, bi = 0, b2 = 0 and b3 = 1 and for which the time period for bs is uninterrupted. The time period for bs is 8 times as long as the time period To for bit bo.

Figure 10 shows an example of PWM signal encoded on 4 bits with bo = 0, bi = 0, b2 = 0 and b3 = 1 and for which the time period for b3 is split as evenly as possible across the PWM period T. The pulse bs has been split into 8 sub-pulses bsi, bs2, bss, b34, L35, bse, b3? and b3s- Each of the sub-pulses has a duration To equal to the duration of the bit bo and the sum of the duration of the sub-pulses is equal to the duration T3 = To*2 ³ .

Figure 11 shows an example of PWM signal encoded on 4 bits with bo = 1, bi = 0, b2 = 0 and b3 = 1 and for which the time period for bo and b3 are split and distributed as evenly as possible across the PWM period T.

Figure 12 shows the PWM signal encoded on 4 bits with bo = 1, bi = 0, b2 = 0 and b3 = 1 with a different distribution of the sub-pulses b3i, bs2, b33, b34, b35, b36, b3? and bss and bo.

The duty cycle D is the same for both figures 11 and 12.

Figure 13 shows the enabled signal ES (Di in Table 1) that drives a Led at a given moment in time and the stored signal SS (Pi in Table 1) that is stored at a given moment in time and that will drive the LED during the next bitblock.

Ligure 14A shows an example of current control circuit according to an embodiment of the present invention.

Figure 14B shows the state of signals at nodes of the circuit of figure 14A in function of time. Figure 14C shows another example of current control circuit according to an embodiment of the present invention.

Figure 15 shows how the second storage element of adjacent current control circuit can be daisy chained to form a shift register according to an embodiment of the present invention. Figure 16 illustrates how bits are sent and stored while the solid state light sources such as OLEDs or LEDs are emitting light according to information encoded in bits previously stored in the memory elements of each pixels or sub-pixels according to an embodiment of the present invention.

Figure 17 shows a reset switch connected in parallel with the capacitor Csn 17, the switch is closed before the end of the time interval To according to an embodiment of the present invention.

Figure 18 illustrates how the RST signal can be used to enable a higher bit depth according to an embodiment of the present invention.

Figure 19 shows for an example with (N1 = 4 and N2 = 2) how the reset signal RST varies in function of time and in function of the PWM sub-period (for each bit bi) according to an embodiment of the present invention.

Figure 20 illustrates how embodiments of the present invention address the problem of connecting different substrates.

Figure 21 illustrates how to upload data to an active display.

Figure 22 shows an alternative arrangement of the control element 1434 e.g. a transistor according to an embodiment of the present invention.

Figure 23 shows an alternative arrangement of the reset element RST e.g. a transistor according to an embodiment of the present invention.

Figure 24 shows a multibit (two-bit) circuit based on a duplication of the current control circuit of Figure 14A according to a further embodiment of the present invention.

Figure 25 shows a multibit (two-bit) circuit based on a duplication of the current control circuit of Figure 14C according to a further embodiment of the present invention.

Figures 26 and 27 show a multibit (two-bit) current control or driving circuit based on a duplication of the current control circuit of Figure 14C in amended form according to a further embodiment of the present invention.

Definitions and Acronyms Active Matrix. Active matrix is a type of addressing scheme used in flat panel displays. In this method of switching individual elements (pixels), each pixel is attached to a switch such as a transistor and a capacitor actively maintaining the pixel state while other pixels are being addressed. An example of schematic of a pixel in an active matrix is given on figure 1.

Active-matrix circuits are commonly constructed with thin-film transistors (TFTs) in a semiconductor layer formed over a display substrate and employing a separate TFT circuit to control each light-emitting pixel in the display. The semiconductor layer is typically amorphous silicon or poly-crystalline silicon and is distributed over the entire flat-panel display substrate. Figure 3 shows a schematic representation of an active matrix. An active matrix display ca also be for example an LCD or an electrophoretic reflective transmissive emitting display or similar.

A display sub-pixel can be controlled by one control element, and each control element includes at least one transistor. For example, in a simple active-matrix light-emitting diode display, each control element includes two transistors (a select transistor and a power transistor) and one capacitor for storing a charge specifying the luminance of the sub-pixel. Each LED element employs an independent control electrode connected to the power transistor and a common electrode. Control of the light-emitting elements in an active matrix known to the art is usually provided through a data signal line, a select signal line, a power or supply connection (referred to as e.g. VDD) and a ground connection.

Critical Flicker Frequency. The highest possible frequency at which flicker is seen when contrast is maximum is the Critical Flicker Frequency (or CFF). The critical flicker frequency is function of several factors like e.g. the luminance. For humans, the lower the luminance, the less sensitive to flicker they are.

Duty Cycle. A duty cycle is the fraction of one period in which a signal or system is active. Duty cycle is commonly expressed as a percentage or a ratio. Thus, a 60% duty cycle means the signal is on 60% of the time but off 40% of the time. In a PWM current control circuit, the duty cycle can represent the fraction of the time that current flows in e.g. a light emitting element.

Flicker. Flicker is a visible fading or decrease in brightness between two successive frames or more generally cycles (like e.g. two successive period of a PWM signal). Programmable memories such as a Flip-Flop.

Embodiments of the present invention make use of a storage element, e.g. one-bit programmable memory such as a flip-flop or a transistor with a select line or a capacitor, e.g. a sample and hold device or a multibit memory. The programmable memory can be clocked in some embodiments.

The embodiments of the present invention can be used with a PWM scheme for driving pixels and/or sub-pixels of a display, e.g. an active display. One-bit programmable memory elements can be used such as a flip flop e.g. a clocked flip-flop or a capacitor or capacitive circuit such as a sample and hold capacitor. Multibit programmable memories can be provided by multiples of one-bit or a multibit memory.

An example of truth tables of a clocked programmable memory is:

“X” denotes a Don’t care condition, meaning the signal is irrelevant, or a programmable memory having the truth table:

These are memories with a NAND and a NOR port. A flip-flop is a programmable memory element. Flip-flops can be clocked or unclocked, e.g. clocked or unclocked programmable elements. For unclocked programmable elements or unclocked flip-flops, the output reacts directly with the input. For clocked programmable elements or clocked flip-flops the input is only transferred to the output after a timing pulse or part of a pulse.

In particular, a D Flip Flop is shown as follows.

D flip-flop symbol

The D flip-flop is widely used. It is also known as a “data” or “delay” flip-flop.

The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell. In particular, a D- flip-flop can be a programmable memory element. A D-flip-flop can be a clocked programmable memory element.

The truth table of the D flip flop or any programmable memory element functioning as a D flip-flop is as follows: I

“X” denotes a Don’t care condition, meaning the signal is irrelevant.

Most D-type flip-flops, e.g. in integrated circuits, have the capability to be forced to the set or reset state (which ignores the D and clock inputs), much like an SR flip-flop. In embodiments where a Flip-Flop is used as a memory element, a clocked D-FF, JK-FF & SR-FF can be used. Embodiments of the present invention can make use of a clocked shift register with Flip-Flops.

Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops. By setting S = R = 0, the flip-flop can be used as described above.

Here is the truth table for the other S and R possible configurations j

In the present application if a B is used as in QB the B means an inverting output. FPGA. Field programmable gate array. An electronic device that can be used to generate the signals required to operate a display and in particular a LED, matrix display. An FPGA can be used as a controller for example. Examples of how an FPGA can be used in LED display can be found in e.g. US7450085B2 “Intelligent lighting module and method of operation of such an intelligent lighting module”.

FPS or fps. Frames per second. The number of frames displayed per second on a LED display or a LED display tile. Frames per second or fps is a unit that measures display device performance. It consists of the number of complete scans of the display screen that occur each second. This is the number of times the image on the screen is refreshed each second, or the rate at which an imaging device produces unique sequential images called frames.

Frame. A frame is one picture of e.g. a series of pictures that makes a sequence of film or animated movie or video. It can also mean a complete image for display (as on a display or a tile of a tiled display). In some contexts, a frame can also mean the time interval during which a frame is displayed. This is better described as “frame time” typically l/60 ^th of a second.

Thin-film technology refers to the use of thin films: A film a few molecules thick deposited on a glass, ceramic, or semiconductor substrate to form a capacitor, resistor, coil, cryotron, or other circuit component. A film of a material from one to several hundred molecules thick deposited on a solid substrate such as glass or ceramic or as a layer on a supporting liquid.

Thin -film Integrated circuit: An integrated circuit consisting entirely of thin films deposited in a patterned relationship on a substrate. The substrate does not have to be a semiconductor but glass, quartz, diamond or polyimide are more often used.

Thin-film transistor: A field-effect transistor constructed entirely by thin-film techniques, for use in thin-film circuits. Abbreviated TFT.

LED. Light Emitting Diode.

OLED. Organic Light Emitting Diode.

LED display.

The following patent applications, from the same applicant, provide definitions of LED displays and related terms. These are hereby incorporated by reference for the definitions of those terms.

US7,972,032B2 “LED Assembly”.

US7,176,861B2 “Pixel structure with optimized subpixel sizes for emissive displays” US7,450,085 “Intelligent lighting module and method of operation of such an intelligent lighting module”.

US7, 071,894 “Method of and device for displaying images on a display device”.

LSB. Least Significant Bit. If a number is encoded with e.g. four bits such that number = bo

+ bi*2 + bi*2 ² + b ₃ *2 ³ then bo is the LSB or least significant bit.

Luminance (L). The luminous intensity per unit area projected in a given direction. The SI unit is the candela per square meter, which is still sometimes called a nit. Luminance and brightness have often been used interchangeably in the literature even though luminance and brightness are not one and the same thing. Here, whenever “brightness” is used, the inventors mean “luminance”.

MSB. Most Significant Bit. If a number is encoded with e.g. four bits such that the number = bo + bi *2 + b2 *2 ² + b ₃ *2 ³ then b3 is the MSB or most significant bit. MSB can also be used for more than one bit, for instance the four bits bo, bi, b2 and bs can be split in two groups. The first two bits bo and bi can be referred to as the least significant bits of the group of four bits. The last two bits b2 and b3 can be referred to as the most significant bits of the group of four bits.

Pitch. Distance between the center of two adjacent pixels (or sub-pixels of the same color) in an array of pixels (or sub-pixels). Also known as spatial period of the array of pixels (or sub-pixels).

Pixel. The one or more light sources used to render a picture element. A pixel can be a unit of an image = picture element. It can be a physical structure of a display which emits light depending upon context. A pixel can include sub-pixels. One or more sub-pixels may emit light of one colour. The sub-pixels can be addressed individually. pMOS. Sometimes called a pMOSFET; p-type Metal-Oxide-Semiconductor Field Effect Transistor.

Light Emitting Element. A light emitting element can be e.g. a solid-state light emitting element, such as a light emitting diode such as an LED or an OLED (Organic LED).

PWM (Pulse- Width Modulation).

Pulse width modulation (PWM) schemes control luminance by varying the time during which a constant current is supplied to a light emitting element such as a light emitting diode. Pulse- width modulation uses a rectangular pulse wave whose pulse width is modulated resulting in the variation of the average value of the waveform. Figure 4 shows an example of such a rectangular pulse wave.

The control signal of a PWM scheme has a bit depth. This is mostly the case in digital systems. Starting from a single pulse and the pulse width is to be controlled with a digital system, the pulse width will follow a binary pattern. The more bits, the more accurate the pulse width will be. In embodiments of the present invention a single pulse can be split up timewise across one frame. This split can be done in a binary way. The more bits the control system has, the smaller the PWM pulse, and the more accurate a value can be displayed.

The square wave has a period T, a lower limit lo (typically, lo = 0), a higher limit Ii and a duty cycle D. The duration of a pulse P (the time during which the signal is at its higher limit Ii) is D/100 * T (if D is expressed in %). For instance if D = 50%, the duration of the pulse is ½ T. In some cases, the shape of the pulse P is modified as illustrated on figure 5. If the period T is “long” or of the same order of magnitude as the time constant of a physical process of importance, it may be advantageous to “split” the pulse into several sub-pulses (SP) that are distributed throughout one period of the wave. In figure 5, one period T has been divided into 4 sub-pulses SP1, SP2, SP3 and SP4 that have been distributed across one period. Depending on the application, it may be desirable to divide one period in more than 4 intervals.

In digital systems, the duration of a pulse is a multiple of a clock period T _ci . The minimum duty cycle that is possible to achieve with a given T and T _ci is thus T _ci /T. As will be described further, the PWM period can be divided in so called bitblocks, each bitblock having the same duration To which may be equal or larger than a reference clock period T _ci .

If the duty cycle is set at its minimum value T _ci / T, the pulse width modulated signal will be as seen on figure 6. If the duty cycle is further increased by e.g. 3 T _ci / T, the pulse P can be split in two or more sub-pulses, each sub-pulses taking place in one of the intervals (or bitblocks) in which the period T has been divided as illustrated on figure 7.

As the duty cycle further increases, each of the intervals is filled-up so that the sum of the duration of the sub-pulses equals D*T.

With Io = 0, the average current <I> circulating in a light emitting element such as a light emitting diode driven by the PWM signal is:

<I> = Ii * D/100 (with D expressed in %) or

<I> = Ii * D (with D expressed as a fraction of T, as a real number in the interval [0,1])

In a LED and other types of fixed format displays, frames are displayed at a frequency of e.g. 60Hz which corresponds to T = 1/60 s. When LEDs are driven with a PWM signal, splitting a pulse into sub-pulses may reduce visible flickering (It is considered that anything below a critical flicker frequency or CFF can be seen. Splitting a pulse into several sub-pulses can be seen as increasing the frequency by as much as N, with N being the number of intervals into which a period is divided).

Even though in those cases, the waveform of the current may not be strictly that of a PWM signal as is usually known (e.g. as on figure 4), nevertheless reference will be made to PWM when discussing the LED current driving scheme. Alternatively, instead of dividing a period T in bitblocks of equal duration, each period T of a PWM signal can be divided into multiple different PWM sub-periods that are sequentially provided at different times. Each PWM sub-period has a different temporal length corresponding to a different bit of the multi-bit digital pixel value (providing a weighted PWM signal). Figure 8 shows an example of PWM sub-periods for a PWM duty cycle encoded with 4 bits bO, bl, b2 and b3 (with bO the LSB and b3 the MSB). In this example, the period T of the PWM signal has been divided in four sub-periods or four PWM time intervals To, Ti, T2, T3 such that T = To+ Ti + T2 + T3.

A light emitting element such as a light emitting diode can be controlled to be on (i.e. with a current of amplitude Tw _ax flowing through it) for a given PWM time period when the corresponding bit of the multi-bit digital pixel value is logically ON and the LED is controlled to be off for a given PWM time period when the corresponding bit of the multi-bit digital pixel value is logically OFF, so that the amount output is specified by the ratio D of the sum of the temporal durations of the ON PWM time periods to the temporal duration of the entire PWM timing signal.

The duty cycle D is, for a bit depth of 4 bits:

D= (bo To + bi Ti + b2 T2 + b3 T3) / T

In particular, the PWM weighted intervals can be such that Ti = To 2 ¹ and D is then given by:

D= (bo To + bi To *2 + b ₂ To *4 + b ₃ To *8) / T

For example, if bo = 0, bi = 0, b2 = 0 and b ₃ = 1; then D = (0*To + 0* To *2 + 0* To *2 ^Z + 1* To *2 ³ ) = 8 To / T = 8 To / (15 To) = 8/15.

The entire PWM timing signal is preferably able to switch at a sufficient rate and have a temporal duration small enough to avoid perceptible flicker. In some cases, the PWM period T and the Frame period (duration of a frame) can be equal. In other cases, the duration of a frame can be longer than the PWM period T and in particular, the duration of a frame can be a multiple of the PWM period T. In the example of embodiments developed further, the PWM period and the frame period can be taken equal for the sake of clarity of the figures.

PWM time periods can be split instead of being uninterrupted. The successive intervals of duration To that divide an entire PWM period T can be called bit blocks. Depending on the context, “bitblock” will refer to one such interval of time or to the logical value (1 or 0, high or low, H or L) of a bit during that time interval.

Detailed Description of Embodiments

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Where the term "comprising" is used in the present description and claims, it does not exclude other elements or steps. Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Pulse width modulation

Embodiments of the present invention use a control scheme such as a Pulse width modulation (PWM) scheme for driving pixels or sub-pixels. Pulse width modulation (PWM) controls luminance by varying the time during which a constant current is supplied to a light emitting element such as a light emitting diode of which an OLED and a LED are two examples. Pulse- width modulation uses a rectangular pulse wave whose pulse width is modulated resulting in the variation of the average value of the waveform. Figure 4 shows an example of such a rectangular pulse wave.

The square wave has a period T, a lower limit Io (typically, Io = 0), a higher limit L and a duty cycle D. The duration of a pulse P (i.e. the time during which the signal is at its higher limit Ii) is D/100 * T (if D is expressed in %). For instance, if D = 50%, the duration of the pulse is ½ T.

In some cases, the shape of the pulse P is modified as illustrated on figure 5. If the period T is “long” or of the same order of magnitude as the time constant of a physical process of importance, it may be advantageous to “split” the pulse into several sub-pulses (SP) that are distributed throughout one period of the wave. In figure 5, one period T has been divided into 4 sub-pulses SP1, SP2, SP3 and SP4 that have been distributed across one period. Depending on the application, it may be desirable to divide one period in more than or less than 4 intervals.

In digital systems, the duration of a pulse is a multiple of a clock period T _ci . The minimum duty cycle that is possible to achieve with a given T and T _ci is thus T _ci /T. As will be described further, the PWM period can be divided in so-called bitblocks, each bitblock having the same duration To which may be equal or larger than a reference clock period T _ci .

If the duty cycle is set at its minimum value T _ci / T, the pulse width modulated signal will be as seen on figure 6. If the duty cycle is further increased by e.g. 3 T _ci / T, the pulse P can be split in two or more sub-pulses, each sub-pulse taking place in one of the intervals (or bitblocks) in which the period T has been divided as illustrated on figure 7.

As the duty cycle further increases, each of the intervals is filled-up so that the sum of the duration of the sub-pulses equals D*T.

With Io = 0, the average current <I> circulating in a light emitting element such as a light emitting diode driven by the PWM signal is:

<I> = Ii * D/100 (with D expressed in %) or

<I> = Ii * D (with D expressed as a fraction of T, as a real number in the interval [0,1])

In a solid-state display such as a LED or OLED display, e.g. of the type that can be used with embodiments of the present invention, frames are displayed at a frequency of e.g. 60Hz which corresponds to T = 1/60 s. When solid state light sources such as OLEDs or LEDs are driven with a PWM signal, splitting a pulse into sub-pulses may reduce visible flickering. For example, it is considered that anything below a critical flicker frequency or CFF can be seen. Splitting a pulse into several sub-pulses can be seen as increasing the frequency by as much as N, with N being the number of intervals into which a period is divided).

Even though in those cases, the waveform of the current may not be strictly that of a PWM signal as is usually known (e.g. as on figure 4), in this application nevertheless reference will be made to PWM when discussing any of the solid state light sources such as LED or OLED current driving schemes according to embodiments of the present invention. Alternatively, instead of dividing a period T in bitblocks of equal duration, each period T of a PWM signal can be divided into multiple different PWM sub-periods that are sequentially provided at different times. Each PWM sub-period has a different temporal length corresponding to a different bit of the multi-bit digital pixel value (providing a weighted PWM signal). Figure 8 shows an example of PWM sub-periods for a PWM duty cycle encoded with 4 bits bO, bl, b2 and b3 (with bO the LSB and b3 the MSB). In this example, the period T of the PWM signal has been divided in four sub-periods or four PWM time intervals To, Ti, T2, T3 such that T = To+ Ti + T2 + T3.

A light emitting element such as a light emitting diode is controlled to be on (i.e. with a current of amplitude i _Max flowing through it) for a given PWM time period when the corresponding bit of the multi-bit digital pixel value is logically ON and the LED is controlled to be off for a given PWM time period when the corresponding bit of the multi-bit digital pixel value is logically OFF, so that the amount output is specified by the ratio D of the sum of the temporal durations of the ON PWM time periods to the temporal duration of the entire PWM timing signal.

The duty cycle D is, for a bit depth of 4 bits:

D= (bo To + bi Ti + b2 T2 + b3 T3) / T

In particular, the PWM weighted intervals can be such that Ti = To 2 ¹ and D is then given by:

D= (bo To + bi To *2 + b ₂ To *4 + b ₃ To *8) / T

In the example of figure 9, with bo = 0, bi = 0, b2 = 0 and bs = 1; then D = (0*To + 0* To *2 +

The entire PWM timing signal is preferably able to switch at a sufficient rate and have a temporal duration small enough to avoid perceptible flicker. In some cases, the PWM period T and the Frame period (duration of a frame) can be equal. In other cases, the duration of a frame can be longer than the PWM period T and in particular, the duration of a frame can be a multiple of the PWM period T. In the example of embodiments developed further, the PWM period and the frame period can be taken equal for the sake of clarity of the figures.

As mentioned earlier, the PWM time periods can be split instead of being uninterrupted. This is illustrated in figures 9 and 10. Figure 9 shows an example of PWM signal encoded on 4 bits with bo = 0, bi = 0, b2 = 0 and b_ = 1 and for which the time period for b _.3 is uninterrupted. The time period for b3 is 8 times as long as the time period To for bit bo.

Figure 10 shows an example of PWM signal encoded on 4 bits with bo = 0, bi = 0, bi = 0 and b3 = 1 and for which the time period for bs is split as evenly as possible across the PWM period T. The pulse bs has been split into 8 sub-pulses b3i, b32, b33, b34, bss, bse, b37 and b3s. Each of the sub-pulses has a duration To equal to the duration of the bit bo and the sum of the duration of the sub-pulses is equal to the duration T3 = To*2 ³ .

Figure 11 shows an example of PWM signal encoded on 4 bits with bo = 1, bi = 0, b ₂ = 0 and bs = 1 and for which the time period for bo and b ₃ are split and distributed as evenly as possible across the PWM period T.

Figure 12 shows the PWM signal encoded on 4 bits with bo = 1, bi = 0, b ₂ = 0 and b3 = 1 with a different distribution of the sub-pulses bsi, b32, b33, b34, bss, b36, b37 and b38 and bo.

The duty cycle D is the same for figures 11 and 12.

The successive intervals of duration To that divide an entire PWM period T can be called bit blocks. Depending on the context, “bitblock” will refer to one such interval of time or to the logical value (1 or 0, high or low, H or L) of a bit during that time interval.

According to embodiments of the present invention, the PWM signal can be used bit after bit (as e.g. in the example of Figure 9) or bit blocks by bit blocks (as e.g. in the example of Figures 10, 11 and 12) to drive a solid state light source such as a LED or OLED. In order to keep the size of an active pixel small enough to be realized with thin film transistors and not to reduce resolution significantly, the memory associated with each pixel or subpixel stores less bits than the bit depth of the encoded PWM signal. For instance, if the bit depth is 12, the memory associated with each pixel or subpixel can store e.g. 2 bits or a single bit at a time. Contrary to what is disclosed in the prior art, it is preferred to store in the memory the value of the bit that must be applied during the next bitblock by _+i while the bit block bi _{, j} is already used to drive a pixel or sub-pixel and the memory is updated at regular intervals To (with To being the duration of a bitblock). Alternatively, the memory stores the value of the bit bi that must be applied during the next PWM sub-period and the memory is updated at different time intervals, the duration of each time interval being function of the weight of the bit bi (as in the example of Figure 8).

This is illustrated in Table 1 here below and in Figure 13.

Table 1 shows the signals Di driving a LED during a given time interval or bitblock and the signals Pi+1 that are stored in a memory element and that will drive the LED during the next time interval or bitblock.

Table 1

Figure 13 shows the enabled signal ES (Di in Table 1) that drives a Led at a given moment in time and the stored signal SS (Pi in Table 1) that is stored at a given moment in time and that will drive the LED during the next bitblock.

Further Embodiments

In the following description of embodiments of the present invention, wherever a B is used as in QB this means an inverting output.

A driver circuit or current control circuit 153 according to embodiments of the present invention can comprise: a control element with a first control electrode, to control the flow of current through a light emitting element; a first storage element to store a first value of a control signal, said control signal being applied to the first control electrode of the control element; a second storage element to store a second value of a control signal; a transfer element with a second control electrode to load the first storage element with the second value of the control signal.

For definitions of the components see the definition section above.

The control element, the first storage element, the second storage element and the transfer element are advantageously realized with the same thin film transistor technology.

With a circuit according to embodiments of the present invention, it is possible to load a second control signal (e.g. voltage) on the second storage element while the first control signal (voltage) is applied to the control electrode of the control element by the first storage element to control the current in the light emitting element. There is thus no “dead time” during which the light emitting element remains idle because no data is available to control it.

In the description of the circuit illustrated on figure 14A:

A control element can be a transistor 143 and a first control electrode can be the gate 1433 of transistor 143. The transistor can be a pMOS transistor, e.g. a thin film transistor. The control element is connected to a LED or OLED diode light emitting element 146 for providing control thereof. The transistor can be operatively connected with a light source such as a LED or OLED and operatively connected with a current source 145.

The first storage element can be a capacitor or a capacitive circuit such as a sample and hold device e.g. comprising a sample and hold capacitor 144 or other storage elements that present their value immediately such as an unclocked flip-flop. The first storage element such as a capacitor e.g. of a sample and hold capacitor 144 is connected between the gate 1433 and a supply voltage VDD. It could also be connected between the gate 1433 and the output of the current source 145.

The second storage element can be a programmable memory such as a one -bit, two- bit or multibit memory such as can be provided by flip-flop 141. The second storage element can be clocked. The number of bits that can be stored on the second storage element should be less than the bit depth of the control signal such as a PWM signal; and

The transfer element can be a transistor 142. The transistor 142 is connected on one side to the second storage element 141 and on the other to the gate 1433. The gate of the transfer element 142 is connected to receive an ENB signal. Transfer element 142 transfers the value (or voltage) from the second storage to the first storage element. The Data signal in figure 14A (control signal) is daisy chained. So every clock cycle on the control signal there is a bit going to the next one-bit memory such as a Flip_Flop. The first and second storage only captures one bit of the control signal towards the light emitting element 146. Figure 14A shows an example of a control circuit or a driver circuit 152 to drive a pixel or a sub-pixel of a solid-state light source 146 according to an embodiment of the present invention.

The PWM bits can be stored one bit at a time in the second storage element such as in a one- bit memory cell like e.g. a D-flip-flop 141 or a programmable device having a two-bit memory or a multibit memory as can be provided by several flip-flops provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal. The second storage element can be clocked. The second storage element such as the flip-flop 141 has an input (D) and an output. The second storage elements such as flip flops 141 being a one-bit memory or a two-bit memory or a multibi t memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, of adjacent pixels in the same column C or the same row R of an array of pixels can be daisy chained (as illustrated in e.g. Figure 15). This daisy chain configuration limits the number of separate tracks that would otherwise be required to control each pixel or sub-pixel of an array.

A value can be captured into the one-bit memory e.g. a Flip-Flop 141 (which is the second storage element in this embodiment) while the light emitting device 146 is enabled with the previous stored value (from the first storage element). A value can be stored without interfering with the value being displayed. Therefore, in figure 14A the output of a one -bit memory such as a Flip_Flop 141 can be updated without interrupting the display of an image.

The output Q of the second storage element such as the flip-flop 141 or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, is updated by a clock signal (Clk). The transistor 142 which is a transfer element is used as a switch that, when closed, connects the output of second storage element such as the flip-flop 141 being a one -bit memory or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, to the gate 1433 of control element such as the transistor 143 and an electrode of a first storage element such as a capacitor C _SH 144 or a capacitive circuit such as a sample and hold circuit with a capacitor CSH 144 or an unclocked flip-flop. The transistor 142 and the transistor 143 can be thin film transistors such as pMOS transistors.

The transfer elements such as transistors 142 are controlled by an enable signal (EN or ENB). In the example of Figure 14 A, the transfer elements such as the transistor 142 is a pMOS transistor that connects the output QB (that can also be noted as Q or ^ as in figure 14 A) of the programmable memory element such as flip-flop 14 lor a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, to the gate 1433 of control element such as the transistor 143 when the enable signal is low (e.g. GND). At the same time, the first storage element such as capacitor (C _SH ) 144 or a capacitive circuit or an unclocked flip-flop with a first electrode connected to the gate 1433 of transistor 143 and with a second electrode connected to e.g. a supply voltage (VDD) samples the voltage Vo _ut at the output of the programmable memory element such as the flip-flop 141 or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, and will hold the gate 1433 of the control element such as transistor 143 at the same voltage even when the transfer element such as the switch or transistor switch 142 is opened.

The control element such as the transistor 143 can be used as a switch. When closed, the transistor used as a switch 143 connects a current source 145 with a light emitting element such as a light emitting diode e.g. a LED or OLED 146, which can emit light. When the switch 143 is open, no current flows through the light emitting element such as the LED or OLED 146 and it emits no light.

If, as in the example of figure 14 A, the control element such as the transistor 143 is a pMOS transi stor, it can be connected to the inverting output QB instead of to the output Q of the flip- flop 14 lor of a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal. Indeed, if a pMOS transistor is used for switch 143, a “low” signal (e.g. GND voltage) will close that switch and allow the current of current source 145 to flow through the light emitting diode 146 such as an OLED or LED. This means that when a bit bi,j is ‘high’ i.e. when the bit bi,j is equal to ‘1’, the light emitting element 146 such as the LED or OLED emits light when the switch, such as a transistor 142 is closed and that when bit bi,j is ‘low’ i.e. when the bit bi,j is equal to Ό’ (and try at the output QB is high), the light emitting element 146 such as the LED or OLED 146 does not emit light when the transfer element such as the switch 142 is closed and the value of by is held by the first storage element e.g. is sampled and held by the sample and hold device such as the capacitor 144.

Once the output of the second storage element comprising the programmable memory element, such as flip-flop 141, has been applied to the first storage element, e.g. has been sampled and stored on the sample and hold device such as capacitor 144, the transfer element such as the switch 142 can be opened and the next bit can be stored in the second storage element e.g. memory element such as a flip-flop 141 or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal.

An advantage of that aspect of the invention is that bits stored in the second memory element such as the flip-flop 141or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, can be updated without interrupting the display of an image.

Figure 14B shows the sequence of signals at various nodes of the circuit shown on figure 14A. The high state (H) corresponds to be binary value 1. The low state (L) corresponds to be binary value 0. The “don’t care” state means that the binary value can be either 1 or 0.

At time to, a data signal e.g. bit bo is presented at the input of the flip-flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal). In the example of figure 14B, bO = 1. At the rising edge of a clocking signal CLK, the output Q of the flip-flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), is updated such that Q = bo while the output QB of the flip-flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), is updated such that QB = bo (the logical inverse of bo).

At time tl > tO, the output of the flip-flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), is connected to a first storage element such as a capacitor or a capacitive circuit such as a sample and hold device with a sample and hold capacitor 144 or an unclocked flip-flop are examples. This is done by closing a switch such as the switch transistor 142 that conditionally connects the output QB of the flip-flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal) and the first storage element such as the capacitor or a capacitive circuit such as the sample and hold device with the sample and hold capacitor 144 (CSH) or an unclocked flip-flop are examples. If the switch such as the switch transistor 142 is a pMOS transistor, it is closed by forcing enable signal ENB to a low state (e.g. ground), as shown in figure 14B. The enable signal ENB is kept low until a time t3 > t2, with At = t3 - 1 ₂ being long enough to guarantee a correct charging or loading of the first storage element 144.

Whatever voltage was stored across the first storage element such as the capacitor or a sample and hold device with a sample and hold capacitor 144 or an unclocked flip-flop are examples, is “erased” and updated in function of the signal (in this case a voltage at the output QB) stored on the second storage element such as the one -bit memory flip-flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal). In the example of figure 14B, with bo = 1, QB = 0 and VG = 0 (with VG the voltage applied to the control electrode 1433, e.g. gate, of the control element 143, e.g. a transistor). With VG = 0 (e.g. GND), the control element 143, e.g. a transistor connects the current source 145 with the light emitting diode such as an LED or OLED146 and the current circulating in the LED or OLED 146 is Lviax.

The updated signal is applied to the control electrode 1433 of the control element 143 such as a transistor for a time T _HO M· T _HO M can be the duration of a bit block. Tuoid can also be the duration of a PWM sub-period (To, Ti, T2, T3 ... as exemplified on e.g. figure 9.

Before the end of T _HO M; e.g. at time t4 > t3; a new data signal (e.g. bi) can be presented at the input of the flip flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal) and the output QB of the one-bit memory flip-flop 141 (or the two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), is updated upon the rising edge of a clock signal CLK. In the example of figure 14B, bi=l with bi following bo.

As was the case for bo, the bit stored on the second storage element 141 such as on a flip-flop or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, can overwrite the data stored on the first storage element 144 such as a capacitor or a capacitive circuit such as a sample and hold device, e.g. with a sample and hold capacitor or an unclocked flip-flop, by closing the transfer element 142 such as a transistor. On figure 14B, this happens at time ts > U with the ENB signal set to low which results in the signal VG being set to high. The control element 143 such as a transistor is opened, disconnecting the current source 145 from the light emitting diode such as the LED or OLED 146. The current ILED is set to I _MPI .

T _Hold can have the same duration for each data signal (i.e. if bit blocks are used). Alternatively, the duration of T _HO M can vary in function of the data signal, in particular in function of the weight of the bit stored on the first storage element 144 such as a capacitor or a capacitive circuit such as a sample and hold device or a sample and hold capacitor or an unclocked flip- flop.

Figure 14C shows an alternative implementation for a pixel according to the invention.

For the circuit illustrated on figure 14C: the control element is, for example, a transistor 143 and the first control electrode 1433 is, for example a gate of the transistor 143; the transistor can be a pMOS transistor, e.g. a thin film transistor. The control element is connected to a light emitting diode such as an OLED or LED 146, The transistor can be operatively connected with a light source such as a LED or OLED and operatively connected with a current source 145; the first storage element can be a capacitor or a capacitive circuit such as a sample and hold device having a sample and hold capacitor 144 or an unclocked flip-flop; the first storage element such as the capacitor or the sample and hold capacitor 144 ior an unclocked flip-flop s connected between the gate 1433 and a supply voltage VDD; The second storage element 147 is, for example, a capacitor C2 or a capacitive circuit such as a sample and hold device or an unclcoked flip-flop; the second storage element is connected between the voltage supply VDD and an electrode of a transfer element 142;

The transfer element is, for example, a transistor 142; a loader which can be a transistor 148; the loader 148 being connected to a data line reset switch such as a reset transistor 149; the reset switch 149 is connected between the voltage supply VDD and the gate electrode 1433; a light emitting element such as an OLED or LED pixel or sub-pixel 146; the light emitting element being connected between the control element such as the transistor 143 and a voltage supply; and a current source 145; the current source 145 being connected between the voltage source VDD and the control element such as the transistor 143. Instead of storing the bits encoding the PWM signal with a flip-flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), a second capacitor C2 is used as the second storage element (element 147 on figure 14C) instead of element 141. The second storage element 147 such as capacitor C2 can be loaded by means of a loading element such as the loading transistor 148 controlled by a “Scan Line #X” signal. The second storage element 147 in combination with the transistor 148 carries out the function of a one-bit memory. If, as shown in figure 14C, the loading element such as the loading transistor 148 is a pMOS transistor, “Scan Line #X” low will bring the “ Data” line in contact with an electrode of the second storage element 147 such as the capacitor C2 and load it with the voltage present on the Data line.

The transfer element such as transistor 142 is closed or opened by the signal ENB and the signal loaded on the second storage element 147 such as capacitor C2 is transferred to the first storage element such as a capacitor or a capacitive circuit such as a sample and hold device, e.g. capacitor C _SH (numbered 144 on figure 14C) or an unclocked flip-flop that controls the control electrode 1433 of the control element such as a transistor switch 143.

A reset element such as a reset transistor 149 is controlled by signal RSTB and can discharge the first storage element such as the capacitor or the capacitive circuit such as a sample and hold device, e.g. having capacitor CSH or an unclocked flip-flop, and turn off the first control element such as transistor switch 143.

When activated, the reset element such as the reset transistor 149 will discharge the capacitor or a capacitive circuit e.g. the sample and hold device such as capacitor 144 or an unclocked flip-flop and no current will circulate in the light source 146 such as a LED or OLED. The role and usefulness of the reset element such as the reset transistor 149 will be discussed below in more detail.

Figure 15 shows adjacent pixels or sub-pixels 150A, 150B, 150C in the same column with their respective programmable memory elements such as flip flops 151A, 151B, 151C (or two-bit memories or a multibit memories provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), connected in a daisy chain (i.e. the output of the programmable memory element such as the flip flop of a sub-pixel (or pixel) is connected to the input of the programmable memory element such as the flip flop of the next sub-pixel (or pixel) (or the same for a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal). For instance, the output QA of the programmable memory element such as flip flop 151 A is connected to the input of the programmable memory element such as the flip flop 15 IB and the output QB of the programmable memory element such as the flip flop 15 IB is connected to the input of the programmable memory element such as the flip flop 151C. In that configuration, the programmable memory elements such as the flip flops of the sub-pixel or pixel in the same column form a shift register.

With this configuration, all the sub-pixels or pixels in the same column can be controlled according to the present invention with only three signals (EN, CLK and DATA). The electrically conducting track for the DATA signal is easy to route from one sub-pixel or pixel to an adjacent pixel or sub-pixel (i.e. track segments connecting the output of a programmable memory element such as a flip flop to the input of the next programmable memory element such as the flip flop).

Each pixel or subpixel in Figure 15 is shown as including a current control or driving circuit of Figure 14A. Herewith expressly disclosed is a substitution of any of the circuits of Figures 14C, 17, 22-27 to replace the circuit shown in this figure.

The programmable memory elements such as the flip flops 151A, 151B, 151C ... (or two-bit memories or a multibit memories (provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal) in the same column must have all been programmed with their corresponding PWM bit or bit block before that PWM bit or bit block is sampled and held by the sample and hold device 144 such as the sample and hold capacitor CSH of each active sub-pixel or pixel 150A, 150B, 150C ...

To illustrate this, let us take as an example the pixels of figure 15 that must display data according to a PWM signal having a bit depth of four.

For this example, in a given frame:

The PWM signal that will determine the grayscale of (sub)pixel 150 A is with bo = 1, bi = 0, b2 = 0 and b3 = 0

The PWM signal that will determine the grayscale of (sub)pixel 150 B is with bo = 0, bi = 1, b2 = 0 and b3 = 0 and

The PWM signal that will determine the grayscale of (sub)pixel 150 C is with bo = 1, bi = 0, b2 = 1 and b3 = 0

Figure 16 illustrates how bits are sent and stored while the light emitting elements such as the LEDs or OLEDs 146 are emitting light according to information encoded by bits previously stored in the first storage element (e.g. memory element) of each pixel or sub-pixel. For the sake of simplicity and merely as an example, the discussion will be limited to three successive pixels or sub-pixels 150 A, 150B and 150C. As seen on figure 15, the second storage elements are memory elements and are preferably programmable memory elements such as D flip-flops or two-bit memories or multibit memories provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, that are daisy chained to form a shift register. Data is fed into the shift register through the input D of the flip flop 151 A (input Data_In on figure 15) (or through a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal).

As an example, a description will be made of how a first bit (e.g. bo) is stored in the first storage element, e.g. a programmable memory element such as the flip-flop (bo _A in 151 A, bo _B in 151B, boc in 151C) of each sub-pixel or pixel (150A, 150B, 150C), respectively and how a second bit (e.g. bi) is eventually stored in the same second storage element, e.g. the programmable memory element such as a flip-flop (bi _A in 151 A, b in 15 IB, bic in 151C) while the light emitting elements such as LEDs or OLEDS keep emitting light according to the information encoded in the first bit in the first storage element. As was the case for figure 14 A, the description is given for a circuit where the transfer element and the control element are pMOS transistors, 142, 143 respectively: each of these elements behaves like a switch that (a) is closed when a LOW signal is applied to their control electrode and (b) is open when a HIGH signal is applied to their control electrode.

By way of example, assuming that boA =1, boB = 0, boc = 1 and biA =0, b = 1, bic = 0.

To shift the bits bo _A , bo _B and boc through the shift register, boc is first presented at the input of a second storage element, e.g. a programmable memory element such as at the input Data_In before a clock signal (CLK) is applied. The operation is repeated for bo _B and bo _A as seen on figure 16. After three clock cycles, QA = 1, QB = 0 and QC = 1. An enable signal (EN) is set to high at time to (which means that ENB (which is the logical inverse of the EN signal) applied to the gate of the transfer element such as the pMOS transistor 142 of figure 14A is set to low and the transfer element such as the pMOS transistor 142 acts as a closed switch). With EN high, the output of the second storage element e.g. the programmable memory element such as the flip flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), is copied onto the first storage element, e.g. the capacitor or capacitive circuit such as the sample and hold device 144 e.g. having the capacitor CSH, or an unclocked flip-flop, of each pixel or sub-pixel thereby opening or closing the control element such as the transistor 143 connecting the light emitting element such as the LED or OLED 146 of each pixel or sub pixel to the current source 145 according to the state of the bit bo that was stored as QA, QB or QC. In the embodiments of figures 14A, 15 and 16, with QA = QC = 1 and QB = 0, current flows through the light emitting element such as the LED or OLED 146 of pixels or sub-pixels 150A and 150C while no current flows through the light emitting element such as LED or OLED 146 of pixel or sub-pixel 150B. The EN signal is then set back to low and the currents IA, IB and Ic flowing in light emitting elements such as the LEDs or OLEDs 146 of pixels or sub-pixels 150A, 150B and 150C respectively, will remain unchanged as long as the voltage across the first storage element such as the capacitor or capacitive circuit, e.g. sample and hold device 144 such as the sample and Hold capacitor CSH, is not updated.

The light emitting elements such as LEDs or OLEDs 146A, 146B andl46C are now emitting light according to the bits bo _A =1, be _® = 0 and boc = 1. This will remain unchanged for a time interval To (which can be the duration of the PWM sub-period of the least significant bit if PWM sub-periods are used as well as the duration of a bit block if bit blocks are used). During that time interval To, the next bits bi _A , b and bic can be shifted through the shift register exactly as was done for the bits bo _A , bo _B and boc.

At the end of the time interval To, the EN signal is set high again. With EN high, the output of the second storage element, e.g. the programmable memory element such as the flip-flop (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), is copied onto the first storage element, e.g. the capacitor or a capacitive circuit sample and hold device 144 having the sample and hold capacitor CSH or an unclocked flip-flop, of each pixel or sub-pixel thereby opening or closing the control element such as transistor 143 connecting the light emitting element such as the LED or OLED of each pixel or sub-pixel 146 to the current source 145 according to the state of the bit bi that was stored as QA, QB or QC. In the examples of figures 14A, 15 and 16, with QA = Qc = 0 and QB = 1, current flows through the light emitting element such as the LED or OLED 146 of pixel or sub-pixel 150B while no current flows through the light emitting elements such as the LED or OLED 146 of pixels or sub-pixels 150A and 150C. The EN signal is then set back to low and the currents IA, IB and Ic in the light emitting elements such as the LEDs or OLEDS 146 of pixel or sub-pixel 150 A, 150B and 150C respectively will remain unchanged as long as the voltage across the first storage element, e.g. the sample and hold device 144 having the Sample and Hold capacitor CSH or an unclocked flip-flop, is not updated.

The other bits encoding the PWM signal that control the light emitted by the light emitting element such as the LED or OLED 146 of the pixel or sub-pixel can be programmed in the same way for the next time interval (of duration To when bit blocks are used and of duration TN = To * 2 ^N for a bit of weight N if PWM sub-periods are used instead of bit blocks).

This can of course be generalized to more than 3 pixels in the same column (row) of an array.

Each of the bits meant for the second storage element of the current control circuits 153 in the same column (or line) in an array of current control circuits 153 are applied sequentially to the input Data_In of the second storage element; e.g. the programmable memory element such as the flip flop 141 (or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), in the column (or line) of current control circuits 153 and shifted through the shift register formed by the second storage elements such as the programmable memory elements or flip-flops 141 (or two-bit memories or multibit memories provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), of adjacent current control circuits 153 in the same column (or line).

The bits are presented sequentially at the input of the column (or line) wide shift register and shifted through the shift register by clocking the shift register with a series of Nb first clock signals (where Nb is the length of the shift register). When the Nb bits have been shifted through the shift register, the content of the second storage element 141 such as the flip-flop or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, is then transferred to the first storage elementl44 such as a capacitor or a capacitive circuit such as the sample and hold device or the sample and hold capacitor or an unclocked flip-flop by applying an enabling signal to the control electrode 1433 of the transfer element 143 which can be a transistor of each current control circuit 153. In that case, TO must be at least as long as the time required to load the shift register with the Nb bits.

It is an advantage of that aspect of the invention that the first storage elements 144 (such as capacitors or capacitive circuits such as sample and hold devices or sample and hold capacitors or unclocked flip-flops) of the current control circuits 153 in the same column (or line) are updated at the same time. Alternatively, the update can be done for the entire array at the same time.

In a further embodiment of the invention, the bit depth encoding the PWM signal is increased without having to change the duration of To.

As was described earlier, the minimum duration for To is equal to the time required to shift the bits (like e.g boA, boa, boc ...) through the shift register formed with the second storage elements, e.g. programmable memory elements (151A, 151B, 151C) such as flip-flops or two- bit memories or multibit memories provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, of the pixels or sub-pixels 150.

The PWM period T cannot be increased beyond a maximum value determined by the required frame rate.

Increasing the bit depth is therefore not easy and, in some cases, it is even impossible with the solutions described in the prior art.

Let us take an example where e.g. the PWM signal will be encoded with 2 additional bits with lesser weight than the bit bo. These bits will be referred to as b-i and b- ₂ .

In the previous example, the bit depth was e.g. 4 and the PWM signal was encoded with the bits bo, bi, b2 and fo. To illustrate how the bit depth can be increased, it is assumed that a PWM signal is encoded with 6 bits b-2, b-i, bo, bi, b2 and b_ .

If PWM sub-periods are used, the duration of PWM sub-periods for each bit is given in table 2: Table 2

As mentioned earlier, the minimum PWM sub-period cannot be decreased below To otherwise, one cannot keep using the same shift register according to the same method. An alternative solution would for instance require an increase of the number of signal tracks to bring the data in parallel to each pixel or group of pixels (sub-pixels or group of sub-pixels).

To nevertheless keep using the same architecture for the array of pixels or sub-pixels and the associated driver circuit according to another aspect of the present invention, a reset signal RST is used. The reset signal RST actuates a reset element e.g. a switch 171 in the active pixels or sub-pixels. The circuit of figure 14A is modified as shown on figure 17. A reset element or switch 171 is connected between the gate 1433 of the control element such as transistor 143 and a reference voltage e.g. VDD, whereby the choice of VDD is particular to the case of a pMOS transistor 143. When closed, the reset element or switch 171 forces the voltage at the gate 1433 of the control element such as transistor 143 to VDD thereby opening it and no current can flow through the light emitting element such as the OLED or LED 146. When the reset element or switch 171 is open, the voltage at the gate 1433 of transistor 143 is determined by the voltage of the first electrode of the first storage element, an example being a capacitor or a capacitive circuit such as the sample and hold device 144 e.g. the sample and hold capacitor CSH or an unclocked flip-flop In this example, when the reset signal RST is high, the reset element such as the switch 171 is closed and when the reset signal RST is low, the reset element or switch 171 is open. With RST high and the control element such as the transistor 143 “open”, the light emitting element or LED or OLED 146 is turned off. In figure 17, element 171 can overwrite the value stored in the first storage element.

Figure 18 illustrates how the RST signal can be used to enable a higher bit depth. A circuit similar to that of figure 15 is still used and the description is limited to the three first pixels in a row or column of the pixel array for clarity reasons. This time, each current driver circuit 153 is equipped with a reset element such as the reset switch 171 as on the circuit of figure 17. As was the case for figure 16, a second storage element, e.g. a programmable memory element such as a D flip-flop or a two-bit memory or a multibit memory, provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, is provided that is triggered on the rising edge of the clock signal.

As was described earlier, the minimum PWM sub-period or the duration of a bit block is To. To can for instance be a minimum time interval required to load the second storage elements such as the programmable memory elements such as flip-flops or two-bit memories or a multibit memories provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, in an entire line or column of pixels or sub-pixels i.e. making the line or column ready for the next bit of information.

For the first NT MSBs (with e.g. N1 = 4 the bits being for instance bo, bi, b2 and bs), the current in the light emitting element 146 of a pixel or sub-pixel is controlled as was previously described and is determined by the value of the first N 1 bits during the entire time interval (sub-period or bitblock).

For the last N2 LSBs (with e.g. N2 = 2 the bits being b-i and b-2), the current in the light emitting element 146 of a pixel or sub-pixel is determined by the value of the last N2 bits during a first part of the time interval To (duration of the sub-period associated to bo or duration of a bitblock) and by the value of the reset signal RST during a second part of the time interval To. The sum of the duration of the first part of the time interval and the duration of the second part of the time interval is equal to the duration of the time interval To.

In the example of figure 18, the following is assumed: b-i _A =l, b-i _B =0, b-ic=l and b- _2A =0, b- _2B =l, b- ₂ c=0. By activating the RST signal before the end of the time interval To for all of the pixels or sub-pixels for which the second storage elements e.g. the memory programmable elements such as flip-flops or two-bit memories or multibit memories provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, are daisy chained, the voltage at the gate 1433 of the control element such as e.g. pMOS transistor 143 of each of these pixels or sub-pixels is set to the supply voltage VDD thereby closing the control element such as the transistor 143 and interrupting the current l _Ref through the light emitting element such as the LED or OLED 146. If the reset signal RST is activated before the end of the time interval To, it is in effect guaranteed that the bits b-i and b- ₂ will have a lesser weight than the bit bo. On figure 18, the RST signal is set high in the middle of the time interval To for b-i. The current through the light emitting element such as the LED or OLED 146 will return to zero at that time. For b-2, the RST signal is set high ¼ To after the beginning of the bit block of duration To.

The reset signal RST can be applied at the same time for all the pixels or sub-pixels in the same column (or the same line). Alternatively, the reset signal RST can be applied at the same time for all the pixels or sub-pixels in the pixel array (with N lines and M columns). Alternatively, the reset signal RST is applied to a subset of the pixels or sub-pixels in the same column (or the same line) or to a subset n X m (with n < N and m < M) of the pixels or sub pixels in the pixel array.

Embodiments of the present invention offer a solution to the problem of increasing the bit depth (i.e. the number of bits) with which the brightness / luminance of a (sub-)pixel is encoded.

If a (LED or OLED ) solid state display has been designed to operate with a minimum PWM sub-period To or bitblock of duration To, applying a reset signal as described in embodiments of the present invention allows one to increase the bit depth beyond what is possible with the solution known to the art.

Figure 19 shows, with an example (NT = 4 and N2 = 2), how the reset signal RST varies in function of time and in function of the PWM sub-period (for each bit bi). The sub-periods Tl, T2 and T3 that correspond to the bit bi, bi and bs each have a duration that matches the weight of the bit i.e. Ti = 2*To; T2 = 4*To and T ₃ = 8*To. The sub-periods that correspond to the additional bit b_i and b-2 have the same duration To as the sub-period corresponding to the bit bo. This limitation is imposed by e.g. the minimum amount of time it takes to load the second storage elements, e.g. the programmable memory elements such as flip-flops 141 or two-bit memories or multibit memories provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal, in e.g. the same column of pixels. Since the second storage elements, e.g. the programmable memory elements such as flip-flops 141 (or two-bit memories or multibit memories provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal), in the circuits of e.g. figures 14 and 15 are updated with one bit (e.g. bi) while the previous bit (e.g. bo) still determines the current in the light emitting element such as the LED or OLED 146, the bit bi must be loaded before the end of the sub-period during which bo is used. If the sub-period for bit b-i is ½ To (as would be the case according to Table 2), the following bit b-2 will not necessarily have been loaded at the time it is needed to drive the current. This is true whether the bits are shifted through a column or line- wide shift register to reach their destination or whether a scanline is used.

The prior art addresses this problem by using a multi-bit memory element: the sequence of bits bo, bi, b2, bs is first loaded in a local shift-register and then the bits are used successively to drive the current by clocking them at increasing time intervals. This has an impact on (a) the load time (not used to display information) and (b) the size of the memory element.

The inventors realized that they could override the driving signal for bits which would normally have a sub-period smaller than To.

The sub-period for bits b-i (and b-2) starts exactly as for the other bits: the bit b-i stored by the flip-flop is “copied” (or loaded or transferred) on first storage element such as a capacitor or a capacitive circuit such as the sample and hold device 144, e.g. the capacitor CSH or an unclocked flip-flop. Once the transfer is completed, the next bit (b-2) is being loaded on the second storage element e.g. the programmable memory element such as the flip-flop 141. As explained earlier, the next bit might not be available before a time To which is larger than the time ½ To. Unless one shortens the time during which the bit b-i controls the current in the light emitting element such as the LED or OLED 146, the bit b-i will have the same weight as the bit bo.

Figure 17 shows an alternative implementation for a pixel according to the invention.

In the description of the circuit illustrated on figure 17: the control element is, for example, a transistor 143 and the first control electrode 1433 is, for example a gate of the transistor 143; the transistor can be a pMOS transistor, e.g. a thin film transistor; the transistor can be connected to a LED or OLED diode light emitting device 146 for driving it. The transistor can be operatively connected with a light source such as a LED or OLED and operatively connected with a current source 145; the first storage element can be a capacitor or a capacitive circuit such as a sample and hold device e.g. a sample and hold device such as a sample and hold capacitor 144 or an unclocked flip flop; the first storage element such as the capacitor, e.g. the sample and hold capacitor 144 is connected between the gate 1433 and a supply voltage VDD;

The second storage element can be a flip-flop 14 lor a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal; the transfer element is, for example, a transistor 142, such as a pMOS transistor, e.g. a TFT transistor; reset element such as reset switch 171; a light emitting element such as an OLED or LED pixel or sub-pixel 146; a current source 145.

A reset element such as the reset switch 171 is connected in parallel with the first storage element, e.g. the capacitor or the capacitive circuit such as the sample and hold device 144 having a sample and hold capacitor C _SH as shown on figure 17 or an unclocked flip-flop. The reset element such as the reset switch 171 is closed before the end of the time interval To:

For bit b-i, the reset element such as the reset switch 171 is closed at ½ To after the start of the sub-period of duration To. As a result, the current in the first half of the time interval is determined by b-i (i.e. the current is 0 if b-i = 0 and the current is Lviax if bn = 1) and is zero in the second half of the time interval (as determined by the state of the reset element such as the reset switch 171 that shunts the capacitor CSH (144) when it is closed.

For bit b-2, the reset element such as the reset switch is closed at ¼ To after the start of the sub-period of duration To. As a result, the current in the first quarter of the time interval is determined by b-2 (i.e. the current is 0 if b-2 = 0 and the current is Fw _ax if b-2 = 1) and is zero in the remaining three quarter of the time interval (as determined by the state of the switch 171 that shunts the capacitor C _SH (144) when it is closed).

For bit b- _n , the reset switch is closed at 2 ^~n To after the start of the sub -period of duration To.

In the example here above, for the first N1 MSBs (with e.g. N1 = 4 the N4 MSBs being for instance bo, bi, b2 and b3), the current in the light emitting element 146 of a pixel or sub-pixel is determined by the value of the first N 1 bits during the entire time interval (sub-period or bitblock).

For each of the last N2 LSBs (with e.g. N2 = 2 the N2 LSBs being b-i and b-2), the current in the light emitting element 146 of a pixel or sub-pixel is determined by the value of the bit during a first part of the time interval (sub -period or bitblock) and by the value of the reset signal RST during a second part of the time interval. The sum of the duration of the first part of the time interval and the duration of the second part of the time interval is equal to the duration of the time interval.

This allows one to modify the bit depth with which the signal controlling the current in the light emitting elements 146 is encoded. The technique circumvents the limitation caused by timing (minimum value for To, maximum value for T) and size (e.g. the size of the second storage element, e.g. the programmable memory element (such as a flip-flop or a two-bit memory or a multibit memory provided the number of bits of the memory is less than the bit depth of the control signal such as a PWM signal)), when more than one bit must be loaded before controlling the current.

The contribution of bits b-i and b-2 over the duty cycle can be evaluated. Whether one uses bit blocks or PWM sub-periods, the duration T of one PWM period with the duty cycle encoded on the six bits b-i, b-2, bo, bi, b2 and b3 is T = To + To + To + 2* To + 4* To + 8* To = 17*To.

Since the pulses corresponding to b-i and b-2 are cut to 0 after ½ To and ¼ To, the maximum duty cycle that can be achieved is less than 100%:

DC _Max = 15,75 To / 17 To ~ 0,93 (or 93 %).

The bit depth usually used for an OLED or LED display is at least 12 (instead of e.g. 4 as in the example). By using the reset signal RST, the inventors realized that they could increase the bit depth to e.g. 16 bits (i.e. by adding the lesser significant bits b-4,b-3, b-2 and b-i to the standard 12 bits bo, bi, b2, b _. 3, b ₄ , bs, b ₆ , b7, bg, b9, bio and bn _.

The maximum duty cycle in that case is

DC Max = [(1/16 + 1/8 + ¼ + ½) + 2 ¹² - 1] / (4 + 2 ¹² - 1) ~ 0,99925.. (or 99,925%).

The smallest duty cycle increment with 12 bits (without using the global RST signal) will be:

D _MIP DC = 1/4095 ~ 0,00025 (or 0,025%).

The smallest duty cycle increment with 12 bits + the 4 lesser significant bits b-4,b-3, b and b-i (and using the RST signal) will be:

D _Mίh DC = 1/16 /(4 + 2 ¹² - 1) ~ 0,000015 (or 0,0015 %).

The mere addition of the reset element such as the reset switch 171 and the global reset signal RST provides an improvement of the resolution of the grayscale by a factor 16 without significant impact on the maximum duty cycle and without impact on the resolution of the array of pixels or sub-pixels (for example, the switch 171 can be one single thin film transistor).

In a further example of embodiments, the shift registers of one display tile can be daisy chained with the shift registers of an adjacent display tile thereby facilitating the assembly of tiled displays wherein each tile is composed of N X M pixels (i.e. N columns of M pixels) according to an embodiment of the present invention. Figure 15 illustrates how the shift registers of pixels in the same column can be daisy chained to form a column-wide shift register. The concept of column of pixels is usually limited to pixels for which the thin film transistors were formed in the same substrate. In a large display, several substrates can be assembled together. One of the major difficulties of assembling different substrates is how to connect these different substrates while keeping the distance between two adjacent substrates to a minimum. Figure 20 illustrates how embodiments of the present invention address the problem of connecting different substrates.

A first substrate 2001, a second substrate 2002 and a third substrate 2003 are positioned next to each other along a direction DIR that is parallel to the direction of the columns of pixels on the first, second and third substrate. The substrates can be semiconductors (less preferred) being preferably insulating for use with thin film processing. Such substrates can be insulating substrates like polyimide, glass, quartz, diamond, sapphire, etc. Substrates are carriers to process the different layers of conductive and non-conductive material on top of it.

The second storage elements e.g. the programmable memory elements for example flip-flops (like e.g. 2004 and 2005 on second substrate 2002) on each substrate are connected (per column) to form a column wide shift register like e.g. 2006, 2007 and 2008 on the substrates 2001, 2002 and 2003, respectively.

Each shift register needs two input signals: a data signal (i.e. the bits encoding the PWM signal for each of the light emitting elements such as LEDs or OLEDS in the same column) and a clock signal as was described earlier. The data signal can be shifted to the next shift register (e.g. 2007) if a connection is made between the last second storage element such as between the Q electrode of the last flip-flop of the column wide shift register 2006 on substrate 2001 and the first second storage element e.g. the D electrode of the first flip-flop of the column wide shift register 2007 on substrate 2002. For the sake of simplicity, any buffer, level shifter ... have been omitted that might be used to protect the circuits on each substrate and that may exist between the last flip-flop in shift register 2006 and the first flip-flop in shift register 2007.

Figure 21 illustrates an active matrix display in which the select lines, select a full row. The data lines are used to provide the data for each column. Line 0 is selected (through select 0), all other select lines are disabled. By doing this, the switch 148 in figure 14C is closed. The data is put on each of the column data lines (DATA 0 -> Data 2) for ROW 0. By doing this, the value on each of the data lines in each element of the same row is stored in element 147 in figure 14C Then select line 0 is deselected. Then line 1 is selected. Data is put on each of the column data lines for ROW 1 ... . This sequence is repeated until the full height of the active matrix display is loaded with data.

This selecting of lines is a preferred technique to get data into each separate element of the active display. A simpler active matrix example (2T1C) is shown in Figures 1 and 3 and can be driven by the same way as described above. These methods can be extended to include the current control or driver circuits of Figures 14 A, 17, 22 - 27 or similar.

In a further embodiment of the present invention as shown in Figure 22, a reset signal RST is used as shown in Figure 17 with an amendment to the way that the control element such as a transistor 1434 controls the current through the light emitting element e.g. an OLED or LED of a pixel or subpixel 146. Reference numbers in Figure 22 refer to the same circuit elements shown in Figure 17 with the exception of the bypass switch or transistor 1434. Instead of putting a control element such as a TFT transistor 143 in series with the light emitting element such as an FED or OFED 146 of a subpixel or pixel to switch the current through the light emitting element such as the FED or OFED 146, the light emitting element is shorted directly with the control element such as a TFT transistor 1434. The principle is the same, i.e. to switch the current through the light emitting element 146 on and off with the control signal such as a PWM driving signal. An advantage of this schematic is that the current source 145 is always delivering current, whether or not through the light emitting element 146. This means the power consumption would be constant and not depending on the light output. This embodiment is herewith explicitly disclosed to include this current control or driver circuit applied to the circuits of Figures 14A, 14C, 22-27 or similar.

Figure 23 shows an alternative arrangement of the reset device 149 e.g. a transistor according to an embodiment of the present invention. Circuit elements with the same reference numbers refer to the same element in Figure 17 except the reset device 149 e.g. a switch such as a transistor functions as a control element and is connected to bypass the light emitting element 146. When the reset element or switch 149 is closed the current from the current source 145 bypasses the light emitting element 146 and no current passes through the light emitting element 146. When the reset element or switch 149 is open the current from the current source 145 passes through the light emitting element 146. In this embodiment, when the reset signal RST is high, the reset element such as the switch 149 is closed and when the reset signal RST is low, the reset element or switch 149 is open.

In this embodiment as soon as the reset is active, there can flow no current through the light emitting element 146. This can be done as follows:

1) Reset the bit value stored in the first storage element (e.g. capacitor 144), therefore opening switch 143 and, thus, no current can flow through the light emitting element 146.

2) Shorting the light emitting element 146 with the reset device 149 such as a switch being open, there will flow no current through the light emitting element 146. When the reset device 149 is active, ghosting of the light emitting element 146 can be avoided as a power electrode such as the anode of the light emitting element 146 is completely discharged. Ghosting is a phenomenon in light emitting elements like an OLED or a LED, when the current source 145 is disconnected from the light emitting element 146 while this is still emitting light. This can have multiple reasons, one of them is the capacitance of the light emitting element 146 in combination with a voltage present on the anode of the LED or OLED. Another reason of ghosting can be leakage currents. By bypassing the light emitting element 146, this is avoided, which is an advantage. This embodiment is herewith explicitly disclosed to include this current control or driver circuit applied to the circuits of Figures 14 A, 14B, 22 - 27 or similar.

Figures 24 to 27 illustrate how a two-bit memory can be implemented in a selection of current control or driver circuits. In these figures -1 and -2 refer to elements relevant to a first bit and a second bit respectively. Figure 24 shows a two-bit memory applied to the circuit of Figure 14A. The number of bits in memory should be less than the bit depth of the control signal such as a PWM signal . The basic reference numbers, i.e. 143 in the reference number 1431-1, refer to the same elements as in Figure 14A. This two-bit circuit can be extended to any number of bits by increasing the number of current sources 145 and the memory devices 141 and other components as indicated in Figure 24. The number of bits in memory should be less than the bit depth of the control signal such as a PWM signal. The storage elements 144-1 and 144-2, such as capacitors or a capacitor circuit such as a sample and hold circuit, set the voltage on the gates of the control elements such as transistors 143-1 and 143-2, respectively. One light emitting element 146 is used for a subpixel or pixel of an active display, whereas two current sources 145-1, 145-2 are used for one bit and the second bit, respectively.

Figure 25 shows a two-bit memory applied to the circuit of Figure 14C. The basic reference numbers, i.e. 143 in the reference number 1431-1 refer to the same elements as in Figure 14C. This two-bit circuit can be extended to any number of bits by increasing the number of current sources 145 and the memory select devices 148-1, 148-2 and other components as indicated in Figure 25. The number of bits in memory should be less than the bit depth of the control signal such as a PWM signal. One light emitting element 146 is used for a subpixel or pixel of an active display whereas two (or more for multibit) current sources 145-1, 145-2 are used for one bit and the second bit, respectively.

Figures 26 and 27 show the same principle of duplication of circuit elements to provide a two- bit memory 141 and 141-2 whereas only one light emitting element 146 is used for a subpixel or pixel of an active display. These circuits are based on Figure 14C but with the use of a two- bit memory such as provided by Flip-Flops. The difference between Figures 26 and 27 is that a single data line is used in figure 26 and two data lines in Figure 27.

If there is one dataline with two single bit memories such as Flip-Flops: a. The time to upload the data to the two single bit memories such as Flip-Flops (with twice as many two single bit memories such as Flip-Flops on one line)is Tblock time x 2. However, because two bits are sent at the same time (2 currents), the number of TBlocks (lbit/TBlock) is divided by two. b. Thus, there is a balanced or null operation (Same Clk speed).

If there are two datalines: c. The time to upload the data to the two single bit memories, such as Flip-Flops, stays the same (#FF’s / line doesn’t change); however, because two bits are now sent two at the same time (2 currents), the number of TBlocks is doubled. d. Thus, the refresh rate of the active matrix display is twice as high or with the same amount of TBlocks, the clock speed can be divided by two.

It is herewith exclusively disclosed the use of two data lines as described above with any of the embodiments of the present invention that use a two-bit memory such as those described with reference to Figure 24 or 25.

These two-bit circuits can be extended to any number of bits by increasing the number of current sources 145 and the memory devices 141-1, 141-2 and other components as indicated in Figures 26 and/or 27. The number of bits in memory should be less than the bitdepth of the control signal such as a PWM signal.