INCORPORATION BY REFERENCE

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of priority of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.

BACKGROUND

[0002] The fabrication of semiconductor devices, such as integrated circuits, is a multi-step process involving photolithography. In general, the process includes the deposition of material on a wafer, and patterning the material through lithographic techniques to form structural features (e.g., transistors and circuitry) of the semiconductor device. The steps of a typical photolithography process known in the art include: preparing the substrate; applying a photoresist, such as by spin coating; exposing the photoresist to light in a desired pattern, causing the exposed areas of the photoresist to become more or less soluble in a developer solution; developing by applying a developer solution to remove either the exposed or the unexposed areas of the photoresist; and subsequent processing to create features on the areas of the substrate from which the photoresist has been removed, such as by etching or material deposition.

[0003] The evolution of semiconductor design has created the need, and has been driven by the ability, to create ever smaller features on semiconductor substrate materials. This progression of technology has been characterized in“Moore’s Law” as a doubling of the density of transistors in dense integrated circuits every two years. Indeed, chip design and manufacturing has progressed such that modern microprocessors may contain billions of transistors and other circuit features on a single chip. Individual features on such chips may be on the order of 22 nanometers (nm) or smaller, in some cases less than 10 nm.

[0004] One challenge in manufacturing devices having such small features is the ability to reliably and reproducibly create photolithographic masks having sufficient resolution. Current photolithography processes typically use 193 nm ultraviolet (UV) light to expose a photoresist. The fact that the light has a wavelength significantly greater than the desired size of the features to be produced on the semiconductor substrate creates inherent issues. Achieving feature sizes smaller than the wavelength of the light requires use of complex resolution enhancement techniques, such as multipatterning. Thus, there is significant interest and research effort in developing photolithographic techniques using shorter wavelength light, such as extreme ultraviolet radiation (EUV), having a wavelength of from 10 nm to 15 nm, e.g., 13.5 nm.

[0005] EUV photolithographic processes can present challenges, however, including low power output and loss of light during patterning. Traditional organic chemically amplified resists (CAR) similar to those used in 193nm UV lithography have potential drawbacks when used in EUV lithography, particularly as they have low absorption coefficients in EUV region and the diffusion of photo-activated chemical species can result in blur or line edge roughness. Furthermore, in order to provide the etch resistance required to pattern underlying device layers, small features patterned in conventional CAR materials can result in high aspect ratios at risk of pattern collapse. Accordingly, there remains a need for improved EUV photoresist materials, having such properties as decreased thickness, greater absorbance, and greater etch resistance.

[0006] The background description provided herein is for the purpose of generally presenting the context of the present technology. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present technology.

SUMMARY

[0007] Dry chamber clean can happen in the context of photoresist patterning. After photoresist material is dry-deposited in a process chamber, unwanted photoresist material may accumulate on internal surfaces of the process chamber. The photoresist material may be, for example, a metal- containing EUV resist material. A dry chamber clean may be performed to remove the unwanted photoresist material by exposure to an etch gas. In some embodiments, the etch gas may be a hydrogen halide, a hydrogen gas and halogen gas, boron trichloride, or combinations thereof. Purging may follow to remove residual etch gas from the process chamber. In some embodiments, conditioning or seasoning of the process chamber may follow to recover the internal surfaces by depositing a coating of film (e.g., photoresist material) on the internal surfaces. [0008] Disclosed herein are methods and systems of cleaning a process chamber. The method includes providing, in a process chamber, a semiconductor substrate with a dry-deposited metal- containing resist film on a substrate layer of the semiconductor substrate, and introducing an etch gas into the process chamber, where a first thickness of dry-deposited metal-containing resist material is formed on one or more surfaces of the process chamber, where the etch gas removes the first thickness of the dry-deposited metal-containing resist material.

[0009] In some implementations, the method further includes conditioning the one or more surfaces of the process chamber by forming a second thickness of the dry-deposited metal- containing resist material on the one or more surfaces of the process chamber. In some implementations, the method further includes purging the process chamber after introducing the etch gas to remove residual etch gas from the process chamber. In some embodiments, purging the process chamber comprises flowing an inert gas and/or reactive gas into the process chamber, where the process chamber is heated to an elevated temperature between about 20°C and about 140°C, where the process chamber is pumped to a chamber pressure between about 0.1 Torr and about 6 Torr. In some implementations, purging the process chamber comprises exposing the one or more surfaces of the process chamber to a remote plasma-based treatment to remove the residual etch gas, where the remote plasma-based treatment includes fluorine-based chemistry. In some implementations, purging the process chamber comprises exposing the one or more surfaces of the process chamber to ozone and/or oxygen gas to remove the residual etch gas. In some implementations, the method further includes heating the one or more surfaces of the process chamber to an elevated temperature prior to introducing the etch gas, where the elevated temperature is between about 20°C and about 140°C. In some implementations, the etch gas includes a hydrogen halide, hydrogen gas and halogen gas, boron trichloride, or combinations thereof. In some implementations, removal of the first thickness of the dry-deposited metal- containing resist material occurs without exposure to plasma. In some implementations, the method further includes the pumping the process chamber to a chamber pressure between about 0.1 Torr and 6 Torr, heating the one or more surfaces of the process chamber to an elevated temperature between about 20°C and about 140°C, and introducing a dummy wafer into the process chamber before introducing the etch gas. In some implementations, the dry-deposited metal-containing resist material is an organo-metal oxide or organo-metal-containing thin film. [0010] Disclosed herein is an apparatus for depositing resist. The apparatus includes a process chamber with a substrate support, a vacuum line coupled to the process chamber, and an etch gas line coupled to the process chamber. The apparatus further includes a controller configured with instructions for cleaning the process chamber, the instructions comprising code for: vapor depositing a metal-containing resist film on a substrate layer of a semiconductor substrate in the process chamber, and cleaning the process chamber by flowing an etch gas into the process chamber, where the etch gas removes a first thickness of dry-deposited metal-containing resist material formed on one or more surfaces of the process chamber.

[0011] In some implementations, the apparatus further includes one or more heaters coupled to the one or more surfaces of the process chamber, where the controller is further configured with instructions comprising code for: heating the one or more surfaces of the process chamber to an elevated temperature, where the elevated temperature is between about 20°C and about 140°C. In some implementations, the controller is configured with instructions comprising code for: conditioning the one or more surfaces of the process chamber by forming a second thickness of the dry-deposited metal-containing resist material on the one or more surfaces of the process chamber. In some implementations, the controller is configured with instructions comprising code for: purging the process chamber after introducing the etch gas to remove residual etch gas from the process chamber.

[0012] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 presents a flow diagram of an example method for performing a dry chamber clean when depositing and developing a photoresist according to some embodiments.

[0014] Figure 2 presents a flow diagram of an example method of performing a dry chamber clean according to some embodiments.

[0015] Figures 3A-3D show cross-sectional schematic illustrations of various processing stages of dry chamber clean according to some embodiments. [0016] Figure 4 illustrates an example dry chamber clean mechanism for chemical reactions of hydrogen chloride or hydrogen bromide with organotin oxide/hydroxide resist materials coated on internal surfaces of a process chamber according to some embodiments.

[0017] Figure 5 shows a graph comparing HC1, HBr, and BCE, in etching metal-containing EUV resist versus time in a cleaning operation.

[0018] Figure 6 shows a graph comparing etch rates for different metal-containing EUV resist materials when using HBr as an etch gas.

[0019] Figure 7 shows a graph illustrating the effects of temperature on etch selectivity for removal of exposed and unexposed regions of photopatterned metal-containing EUV resist.

[0020] Figure 8A shows a graph illustrating the effects of temperature on selectivity for removal of EUV resist.

[0021] Figure 8B shows a bar graph illustrating the effects of temperature on etch rate for removal of EUV resist.

[0022] Figure 9 shows a graph illustrating the effects of pressure on etch selectivity for removal of exposed and unexposed regions of photopatterned metal-containing EUV resist.

[0023] Figure 10A shows a graph illustrating the effects of pressure on selectivity for removal of EUV resist.

[0024] Figure 10B shows a bar graph illustrating the effects of pressure on etch rate for removal of EUV resist.

[0025] Figures 11A-11E show graphs illustrating the performance of HC1 as an etch gas for different pressures and temperatures.

[0026] Figure 12 shows a graph illustrating an amount of bromine over time in a process chamber when purging.

[0027] Figure 13 depicts a schematic illustration of an example process station for maintaining a low-pressure environment that is suitable for performing dry chamber clean according to some embodiments. [0028] Figure 14 depicts a schematic illustration of an example multi-station processing tool suitable for implementation of various development, dry clean, rework, descum, and smoothing operations described herein.

[0029] Figure 15 shows a cross-sectional schematic view of an example inductively-coupled plasma apparatus for implementing certain embodiments and operations described herein.

[0030] Figure 16 depicts a semiconductor process cluster tool architecture with vacuum- integrated deposition and patterning modules that interface with a vacuum transfer module, suitable for implementations of processes described herein.

DETAILED DESCRIPTION

[0031] This disclosure relates generally to the field of semiconductor processing. In particular aspects, the disclosure is directed to process and apparatus for processing of EUV photoresists (e.g., EUV-sensitive metal and/or metal oxide-containing photoresist films) in the context of EUV patterning and EUV patterned film development to form a patterning mask.

[0032] Reference is made herein in detail to specific embodiments of the disclosure. Examples of the specific embodiments are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the disclosure to such specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail so as to not unnecessarily obscure the present disclosure.

Introduction

[0033] Patterning of thin films in semiconductor processing is often an important step in the fabrication of semiconductors. Patterning involves lithography. In conventional photolithography, such as 193nm photolithography, patterns are printed by emitting photons from a photon source onto a mask and printing the pattern onto a photosensitive photoresist, thereby causing a chemical reaction in the photoresist that, after development, removes certain portions of the photoresist to form the pattern.

[0034] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include nodes 22 nm, 16 nm, and beyond. In the 16 nm node, for example, the width of a typical via or line in a Damascene structure is typically no greater than about 30nm. Scaling of features on advanced semiconductor integrated circuits (ICs) and other devices is driving lithography to improve resolution.

[0035] Extreme ultraviolet (EUV) lithography can extend lithography technology by moving to smaller imaging source wavelengths than would be achievable with conventional photolithography methods. EUV light sources at approximately 10-20 nm, or 11-14 nm wavelength, for example 13.5 nm wavelength, can be used for leading-edge lithography tools, also referred to as scanners. The EUV radiation is strongly absorbed in a wide range of solid and fluid materials including quartz and water vapor, and so operates in a vacuum.

[0036] EUV lithography makes use of EUV resists that are patterned to form masks for use in etching underlying layers. EUV resists may be polymer-based chemically amplified resists (CARs) produced by liquid-based spin-on techniques. An alternative to CARs is directly photopattemable metal oxide-containing films, such as those available from Inpria, Corvallis, OR, and described, for example, in US Patent Publications US 2017/0102612, US 2016/021660 and US 2016/0116839, incorporated by reference herein at least for their disclosure of photopattemable metal oxide-containing films. Such films may be produced by spin-on techniques or dry vapor-deposited. The metal oxide-containing film can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum ambient providing sub-30 nm patterning resolution, for example as described in US Patent 9,996,004, issued June 12, 2018 and titled EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS, and/or in Application PCT/US 19/31618, filed May 9, 2019, and titled METHODS FOR MAKING EUV PATTERNABLE HARD MASKS, the disclosures of which at least relating to the composition, deposition, and patterning of directly photopattemable metal oxide films to form EUV resist masks is incorporated by reference herein. Generally, the patterning involves exposure of the EUV resist with EUV radiation to form a photo pattern in the resist, followed by development to remove a portion of the resist according to the photo pattern to form the mask.

[0037] It should also be understood that the while present disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, it is also applicable to other next generation lithographic techniques. In addition to EUV, which includes the standard 13.5 nm EUV wavelength currently in use and development, the radiation sources most relevant to such lithography are DUV (deep-UV), which generally refers to use of 248 nm or 193 nm excimer laser sources, X-ray, which formally includes EUV at the lower energy range of the X-ray range, as well as e-beam, which can cover a wide energy range. The specific methods may depend on the particular materials and applications used in the semiconductor substrate and ultimate semiconducting device. Thus, the methods described in this application are merely exemplary of the methods and materials that may be used in present technology.

[0038] Directly photopattemable EUV resists may be composed of or contain metals and/or metal oxides mixed within organic components. The metals/metal oxides are highly promising in that they can enhance the EUV photon adsorption and generate secondary electrons and/or show increased etch selectivity to an underlying film stack and device layers.

[0039] When fabricating semiconductor devices, it is important for the fabrication process to be precise and repeatable. Unfortunately, as a semiconductor fabrication reaction chamber processes multiple substrates over time, the processing conditions and chemistries within the reaction chamber change. During deposition and application of a metal-containing EUV resist film on a semiconductor substrate, e.g., dry deposition as described herein, there may be some unintended deposition of metal-containing EUV resist material on chamber surfaces. After performing several processing operations in a process chamber, the unintended formation of metal-containing EUV resist material on chamber surfaces may reach a level that makes the EUV resist material more prone to flaking and peeling. In some instances, particles and film impurities originating from the EUV resist material on internal surfaces of the process chamber may fall onto a substrate surface during processing. For example, particles and film impurities may originate from internal chamber walls, ceiling, showerhead, substrate support, lift pins, gas lines, nozzles, etc. Such particles and film impurities that flake or peel from internal surfaces of the process chamber may result in contamination and defect issues in semiconductor substrates. This contamination not only causes contamination in a semiconductor substrate itself, but potentially causes contamination in downstream processing tools such as patterning (scanner) and development tools.

[0040] Conventionally, removal of unintended deposits on internal surfaces of a process chamber can be performed by manually opening up the process chamber and mechanically scrubbing/wiping the internal surfaces using one or more cleaning agents. In some instances, these methods may involve replacement of parts and can take more than a day to perform chamber maintenance. Such methods may be time-consuming, costly, and ineffective.

Dry Clean of EUV Resist in Process Chamber

[0041] The present disclosure provides for a dry clean of EUV resist material from internal surfaces of a process chamber. The dry clean can be performed using halide-containing chemistries. In some embodiments, the halide-containing chemistry may include a hydrogen halide such as HC1, HBr, or HI. For example, the hydrogen halide can be HC1. In some embodiments, the halide-containing chemistry may include a hydrogen gas and halogen gas. The dry clean may be a non-plasma thermal-based cleaning operation. For instance, a chamber wall temperature may be between about 20°C and about 140°C. The dry clean may be followed by a dehalogenation step to remove excess halides from the process chamber and/or a conditioning step to protect the internal surfaces of the process chamber. Though the dry clean is particularly useful in a process chamber used for EUV dry deposition, the dry clean may be performed in any process chamber used in bevel edge and/or backside clean, bake, development, or etch operation. The present in situ dry clean decreases the frequency between cleaning operations, improves particle performance, and enables higher tool availability.

[0042] Figure 1 presents a flow diagram of an example method for performing a dry chamber clean when depositing and developing a photoresist according to some embodiments. The operations of a process 100 may be performed in different orders and/or with different, fewer, or additional operations. Aspects of the process 100 may be described with reference to Figures 2 and 3A-3D. One or more operations of the process 100 may be performed using an apparatus described in any one of Figures 13-16. In some embodiments, the operations of the process 100 may be implemented, at least in part, according to software stored in one or more non-transitory computer readable media.

[0043] At block 102 of the process 100, a layer of photoresist is deposited. This may be either a dry deposition process such as a vapor deposition process or a wet process such as a spin-on deposition process.

[0044] The photoresist may be a metal-containing EUV resist. An EUV-sensitive metal or metal oxide-containing film may be deposited on a semiconductor substrate by any suitable technique, including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, described processes have been demonstrated for EUV photoresist compositions based on organotin oxides, being applicable to both commercially spin-coatable formulations (e.g., such as are available from Inpria Corp, Corvallis, OR) and formulations applied using dry vacuum deposition techniques, further described below.

[0045] Semiconductor substrates may include any material construct suitable for photolithographic processing, particularly for the production of integrated circuits and other semiconducting devices. In some embodiments, semiconductor substrates are silicon wafers. Semiconductor substrates may be silicon wafers upon which features have been created ("underlying features"), having an irregular surface topography. As referred to herein, the "surface" is a surface onto which a film of the present disclosure is to be deposited or that is to be exposed to EUV during processing. Underlying features may include regions in which material has been removed (e.g., by etching) or regions in which materials have been added (e.g., by deposition) during processing prior to conducting a method of this disclosure. Such prior processing may include methods of this disclosure or other processing methods in an iterative process by which two or more layers of features are formed on the substrate.

[0046] EUV-sensitive thin films may be deposited on the semiconductor substrate, such films being operable as resists for subsequent EUV lithography and processing. Such EUV-sensitive thin films comprise materials which, upon exposure to EUV, undergo changes, such as the loss of bulky pendant substituents bonded to metal atoms in low density M-OH rich materials, allowing their crosslinking to denser M-O-M bonded metal oxide materials. Through EUV patterning, areas of the film are created that have altered physical or chemical properties relative to unexposed areas. These properties may be exploited in subsequent processing, such as to dissolve either unexposed or exposed areas, or to selectively deposit materials on either the exposed or unexposed areas. In some embodiments, the unexposed film has a more hydrophobic surface than the exposed film under the conditions at which such subsequent processing is performed. For example, the removal of material may be performed by leveraging differences in chemical composition, density and cross-linking of the film. Removal may be by wet processing or dry processing, as further described below.

[0047] The thin films are, in various embodiments, organometallic materials, for example organotin materials comprising tin oxide, or other metal oxide materials/moieties. The organometallic compounds may be made in a vapor phase reaction of an organometallic precursor with a counter reactant. In various embodiments, the organometallic compounds are formed through mixing specific combinations of organometallic precursors having bulky alkyl groups or fluoroalkyl with counter-reactants and polymerizing the mixture in the vapor phase to produce a low-density, EUV-sensitive material that deposits onto the semiconductor substrate.

[0048] In various embodiments, organometallic precursors comprise at least one alkyl group on each metal atom that can survive the vapor-phase reaction, while other ligands or ions coordinated to the metal atom can be replaced by the counter-reactants. Organometallic precursors include those of the formula:

MaRbLc

(Formula 1) wherein: M is a metal with a high EUV absorption cross-section; R is alkyl, such as CnFbn+i, preferably wherein n > 2; L is a ligand, ion or other moiety which is reactive with the counter reactant; a > 1 ; b > 1 ; and c > 1.

[0049] In various embodiments, M has an atomic absorption cross section equal to or greater than lxlO ⁷ cm ² /mol. M may be, for example, selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, germanium, and combinations thereof. In some embodiments, M is tin. R may be fluorinated, e.g., having the formula C _n F _x H(2n+i). In various embodiments, R has at least one beta-hydrogen or beta-fluorine. For example, R may be selected from the group consisting of ethyl, i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec- butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L may be any moiety readily displaced by a counter-reactant to generate an M-OH moiety, such as a moiety selected from the group consisting of amines (such as dialky lamino, monoalkylamino), alkoxy, carboxylates, halogens, and mixtures thereof.

[0050] Organometallic precursors may be any of a wide variety of candidate metal-organic precursors. For example, where M is tin, such precursors include t-butyl tris(dimethylamino) tin, i-butyl tris(dimethylamino) tin, n-butyl tris(dimethylamino) tin, sec -butyl tris(dimethylamino) tin, i-propyl(tris)dimethylamino tin, n-propyl tris(dimethylamino) tin, ethyl tris(dimethylamino) tin, and analogous alkyl(tris)(t-butoxy) tin compounds such as t-butyl tris(t-butoxy) tin. In some embodiments, the organometallic precursors are partially fluorinated.

[0051] Counter-reactants have the ability to replace the reactive moieties, ligands or ions (e.g., L in Formula 1, above) so as to link at least two metal atoms via chemical bonding. Counter reactants can include water, peroxides (e.g., hydrogen peroxide), di- or polyhydroxy alcohols, fluorinated di- or polyhydroxy alcohols, fluorinated glycols, and other sources of hydroxyl moieties. In various embodiments, a counter-reactant reacts with the organometallic precursor by forming oxygen bridges between neighboring metal atoms.

[0052] Other potential counter-reactants include hydrogen sulfide and hydrogen disulfide, which can crosslink metal atoms via sulfur bridges. In other instances, Te-containing precursors may be used counter-reactants with or instead of water to form Te-Sn-Te-Sn cross-links, for example. Suitable tellurium co-reactants for use with Sn(NMe2)x type precursors are RTeH or RTeD (D=deuterium) and RiTc precursors, with R=alkyl groups, particularly t-butyl or isopropyl, such as t-butylTeD. For use with M(OR)x type precursors, Bis(trimethylsilyl)Te may be used, for example.

[0053] The thin films may include optional materials in addition to an organometallic precursor and counter-reactants to modify the chemical or physical properties of the film, such as to modify the sensitivity of the film to EUV or enhancing etch resistance. Such optional materials may be introduced, such as by doping during vapor phase formation prior to deposition on the semiconductor substrate, after deposition of the thin film, or both. In some embodiments, a gentle remote Fh plasma may be introduced so as to replace some Sn-L bonds with Sn-H, which can increase reactivity of the resist under EUV. [0054] In various embodiments, the EUV-pattemable films are made and deposited on the semiconductor substrate using vapor deposition equipment and processes among those known in the art. In such processes, the polymerized organo metallic material is formed in vapor phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter reactants are separated in either time or space.

[0055] In general, methods comprise mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant so as to form a polymerized organometallic material, and depositing the organometallic material onto the surface of the semiconductor substrate. In some embodiments, more than one organometallic precursor is included in the vapor stream. In some embodiments, more than one counter-reactant is included in the vapor stream. As will be understood by one of ordinary skill in the art, the mixing and depositing aspects of the process may be concurrent, in a substantially continuous process.

[0056] In an example continuous CVD process, two or more gas streams, in separate inlet paths, of organometallic precursor and source of counter-reactant are introduced to the deposition chamber of a CVD apparatus, where they mix and react in the gas phase, to form agglomerated polymeric materials (e.g., via metal-oxygen-metal bond formation). The streams may be introduced, for example, using separate injection inlets or a dual-plenum showerhead. The apparatus is configured so that the streams of organometallic precursor and counter-reactant are mixed in the chamber, allowing the organometallic precursor and counter-reactant to react to form a polymerized organometallic material. Without limiting the mechanism, function, or utility of present technology, it is believed that the product from such vapor-phase reaction becomes heavier in molecular weight as metal atoms are crosslinked by counter-reactants, and is then condensed or otherwise deposited onto the semiconductor substrate. In various embodiments, the steric hindrance of the bulky alkyl groups prevents the formation of densely packed network and produces smooth, amorphous, low-density films.

[0057] The CVD process is generally conducted at reduced pressures, such as from 10 milliTorr to 10 Torr. In some embodiments, the process is conducted at from 0.5 to 2 Torr. In some embodiments, the temperature of the semiconductor substrate is at or below the temperature of the reactant streams. For example, the substrate temperature may be from 0°C to 250°C, or from ambient temperature (e.g., 23°C) to 150°C. In various processes, deposition of the polymerized organometallic material on the substrate occurs at rates inversely proportional to surface temperature.

[0058] The thickness of the EUV-patternable film formed on the surface of the semiconductor substrate may vary according to the surface characteristics, materials used, and processing conditions. In various embodiments, the film thickness may range from 0.5 nm to 100 nm, and may be a sufficient thickness to absorb most of the EUV light under the conditions of EUV patterning. The EUV-pattemable film may be able to accommodate absorption equal to or greater than 30%, thereby having significantly fewer EUV photons available towards the bottom of the EUV-pattemable film. Higher EUV absorption leads to more cross-linking and densification near the top of an EUV-exposed film compared to the bottom of the EUV-exposed film. Though efficient utilization of EUV photons may occur with EUV-pattemable films having higher overall absorption, it will be understood that in some instances, the EUV-pattemable film may be less than about 30%. For comparison, the maximum overall absorption of most other resist films are less than 30% (e.g., 10% or less, or 5% or less) so that the resist material at the bottom of the resist film is sufficiently exposed. In some embodiments, the film thickness is from 5 nm to 40 nm or from 10 nm to 20 nm. Without limiting the mechanism, function, or utility of present disclosure, it is believed that, unlike wet, spin-coating processes of the art, the processes of the present disclosure have fewer restrictions on the surface adhesion properties of the substrate, and therefore can be applied to a wide variety of substrates. Moreover, as discussed above, the deposited films may closely conform to surface features, providing advantages in forming masks over substrates, such as substrates having underlying features, without "filling in" or otherwise planarizing such features.

[0059] In addition to depositing a metal-containing EUV resist thin film on a semiconductor substrate at block 102 of the process 100, metal-containing EUV resist material may be formed on internal surfaces of the process chamber. The internal surfaces may include chamber walls, floors, and ceilings of the process chamber. Other internal surfaces may include a showerhead, nozzles, and substrate support surfaces. The metal-containing EUV resist material may form as a result of dry deposition processes, such as CVD or ALD processes. A thickness of the metal-containing EUV resist material formed on the internal surfaces may increase over time as a result of additional processing (e.g., deposition) operations being performed in the process chamber. The metal- containing EUV resist material is prone to flake off, shed particles, or peel from the internal surfaces of the process chamber to contaminate subsequent semiconductor substrates during processing.

[0060] At block 150 of the process 100, a dry chamber clean operation of the present disclosure may be performed after deposition of the metal-containing EUV resist thin film on the semiconductor substrate at block 102 of the process 100. This allows for deposition and dry cleaning to be performed in the same process chamber. However, it will be understood that the dry chamber clean may be performed in a different process chamber than the deposition operation in embodiments. In fact, the dry chamber clean may be performed subsequent to a bevel and/or backside clean, bake, development, or etch operation.

[0061] The dry-deposited EUV photoresist films being removed are generally composed of Sn, O and C, but the same clean approaches can be extended to films of other metal oxide resists and materials. In addition, this approach can also be used for film strip and PR rework.

[0062] At block 104 of the process 100, an optional cleaning process is performed to clean a backside and/or bevel edge of the semiconductor substrate. The backside and/or bevel edge clean may non-selectively etch EUV resist film to equally remove film with various levels of oxidation or crosslinking on the substrate backside and bevel edge. During application of the EUV- pattemable film, either by wet deposition processing or dry deposition processing, there may be some unintended deposition of resist material on the substrate bevel edge and/or backside. The unintended deposition may lead to undesirable particles later moving to a top surface of the semiconductor substrate and becoming particle defects. Moreover, this bevel edge and backside deposition can cause downstream processing problems, including contamination of the patterning (scanner) and development tools. Conventionally, removal of this bevel edge and backside deposition is done by wet cleaning techniques. For spin-coated photoresist material, this process is called edge bead removal (EBR) and is performed by directing a stream of solvent from above and below the bevel edge while the substrate is spinning. The same process can be applied to soluble organotin oxide-based resists deposited by vapor deposition techniques.

[0063] The substrate bevel edge and/or backside clean may also be a dry clean process. In some embodiments, the dry clean process involves a vapor and/or plasma having one or more of the following gases: HBr, HC1, BCb, SOCh, CI2, BBr3, ¾, O2, PCI3, CH4, methanol, ammonia, formic acid, NF3, HF. In some embodiments, the dry clean process may use the same chemistries as a dry development process described herein. For example, the bevel edge and backside clean may use hydrogen halide development chemistry. For the backside and bevel edge clean process, the vapor and/or the plasma has to be limited to a specific region of the substrate to ensure that only the backside and the bevel are removed, without any film degradation on a frontside of the substrate.

[0064] Process conditions may be optimized for bevel edge and backside clean. In some embodiments, higher temperature, higher pressure, and/or higher reactant flow may lead to increased etch rate. Suitable process conditions for a dry bevel edge and backside clean may be: reactant flow of 100-500 seem (e.g., 500 seem HC1, HBr, or ¾ and CI2 or Br2 _, BCb or ¾), temperature of -10 to 120°C (e.g., 20°C), pressure of 20-500 mTorr (e.g., 300 mTorr), plasma power of 0 to 500 W at high frequency (e.g., 13.56 MHz), and for a time of about 10 to 20 seconds, dependent on the photoresist film and composition and properties. It should be understood that while these conditions are suitable for some processing reactors, e.g., a Kiyo etch tool available from Lam Research Corporation, Fremont, CA, a wider range of process conditions may be used according to the capabilities of the processing reactor.

[0065] The dry cleaning operation may alternatively be extended to a full photoresist removal or photoresist“rework” in which an applied EUV photoresist is removed and the semiconductor substrate prepared for photoresist reapplication, such as when the original photoresist is damaged or otherwise defective. Photoresist rework should be accomplished without damaging the underlying semiconductor substrate, so an oxygen-based etch should be avoided. Instead, variants of halide-containing chemistries as described herein may be used. It will be understood that the photoresist rework operation may be applied at any stage during the process 100. Thus, the photoresist rework operation may be applied after photoresist deposition, after bevel edge and backside clean, after PAB treatment, after EUV exposure, after PEB treatment, or after development. In some embodiments, the photoresist rework may be performed for non-selective removal of exposed and unexposed regions of the photoresist but selective to an underlayer.

[0066] In some embodiments, the photoresist rework process involves a vapor and/or plasma having one or more of the following gases: HBr, HC1, BCI3, CI2, BBr3, ¾, PCI ,, CH4, methanol, ammonia, formic acid, NF3, HF. In some embodiments, the photoresist rework process may use the same chemistries as a dry development process described herein. For example, the photoresist rework may use hydrogen halide development chemistry.

[0067] Process conditions may be optimized for the photoresist rework. In some embodiments, higher temperature, higher pressure, and/or higher reactant flow may lead to increased etch rate. Suitable process conditions for a photoresist rework may be: reactant flow of 100-500 seem (e.g., 500 seem HC1, HBr, BCE, or ¾ and Ch or Bn), temperature of -10 to 120°C (e.g., 20°C), pressure of 20-500 mTorr (e.g., 300 mTorr), plasma power of 300 to 800 W (e.g., 500 W) at high frequency (e.g., 13.56 MHz), wafer bias of 0 to 200 V _b (a higher bias may be used with harder underlying substrate materials) and for a time of about 20 seconds to 3 minutes, sufficient to completely remove the EUV photoresist, dependent on the photoresist film and composition and properties. It should be understood that while these conditions are suitable for some processing reactors, e.g., a Kiyo etch tool available from Lam Research Corporation, Fremont, CA, a wider range of process conditions may be used according to the capabilities of the processing reactor.

[0068] At block 150 of the process 100, a dry chamber clean operation of the present disclosure may be performed after a bevel edge and/or backside clean operation. This allows for bevel and/or backside clean and dry chamber clean to be performed in the same process chamber. However, it will be understood that the dry chamber clean may be performed in a different process chamber than the bevel edge and/or backside clean operation in some embodiments.

[0069] At block 106 of the process 100, an optional post-application bake (PAB) is performed after deposition of the EUV-patternable film and prior to EUV exposure. The PAB treatment may involve a combination of thermal treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV-pattemable film, reducing the EUV dose to develop a pattern in the EUV- pattemable film. The PAB treatment temperature may be tuned and optimized for increasing the sensitivity of the EUV-patternable film. For example, the treatment temperature may be between about 90°C and about 250°C or between about 100°C and about 200°C. In some embodiments, the PAB treatment may be conducted with a pressure between atmospheric and vacuum, and a treatment duration of about 1 to 15 minutes, for example about 2 minutes. In some embodiments, the PAB treatment is conducted at a temperature between about 100°C to 200°C for about 1 minute to 2 minutes. [0070] At block 150 of the process 100, a dry chamber clean operation of the present disclosure may be performed after a PAB treatment. This allows for bake and dry chamber clean to be performed in the same process chamber. However, it will be understood that the dry chamber clean may be performed in a different process chamber than the PAB treatment operation in some embodiments.

[0071] At block 108 of the process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop a pattern. Generally speaking, the EUV exposure causes a change in the chemical composition and cross-linking in the metal-containing EUV resist film, creating a contrast in etch selectivity that can be exploited for subsequent development.

[0072] The metal-containing EUV resist film may then be patterned by exposing a region of the film to EUV light, typically under relatively high vacuum. EUV devices and imaging methods among those useful herein include methods known in the art. In particular, as discussed above, exposed areas of the film are created through EUV patterning that have altered physical or chemical properties relative to unexposed areas. For example, in exposed areas, metal-carbon bond cleavage may occur, as through a beta-hydride elimination, leaving behind reactive and accessible metal hydride functionality that can be converted to hydroxide and cross-linked metal oxide moieties via metal-oxygen bridges during a subsequent post-exposure bake (PEB) step. This process can be used to create chemical contrast for development as a negative tone resist. In general, a greater number of beta-H in the alkyl group results in a more sensitive film. Following exposure, the metal-containing EUV resist film may be baked, so as to cause additional cross- linking of the metal oxide film. The difference in properties between exposed and unexposed areas may be exploited in subsequent processing, such as to dissolve unexposed areas or to deposit materials on the exposed areas. For example the pattern can be developed using a dry method to form a metal oxide-containing mask.

[0073] In particular, in various embodiments, the hydrocarbyl-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed region(s) of an imaging layer, particularly when the exposure is performed in a vacuum using EUV. However, removing exposed imaging layers from vacuum into air, or the controlled introduction of oxygen, ozone, H2O2, or water, can result in the oxidation of surface Sn-H into Sn-OH. The difference in properties between exposed and unexposed regions may be exploited in subsequent processing, such as by reacting the irradiated region, the unirradiated region, or both, with one or more reagents to selectively add material to or remove material from the imaging layer.

[0074] Without limiting the mechanism, function or utility of present technology, EUV exposure, for example, at doses of from 10 mJ/cm ² to 100 mJ/cm ² results in the cleavage of Sn-C bonds resulting in loss of alkyl substituent, alleviating steric hindrance and allowing the low- density film to collapse. In addition, reactive metal-H bond generated in the beta-hydride elimination reactions can react with neighboring active groups such as hydroxyls in the film, leading to further cross-linking and densification, and creating chemical contrast between exposed and unexposed region(s).

[0075] Following exposure of the metal-containing EUV resist film to EUV light, a photopattemed metal-containing EUV resist is provided. The photopatterned metal-containing EUV resist includes EUV-exposed and unexposed regions.

[0076] At block 110 of the process 100, an optional post-exposure bake (PEB) is performed to further increase contrast in etch selectivity of the photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist can be thermally treated in the presence of various chemical species to facilitate cross-linking of the EUV-exposed regions of the photopattemed metal-containing EUV resist or simply baked on a hot plate in ambient air, for example, between 150°C and 250°C for between one and five minutes (e.g., 190°C for two minutes).

[0077] In various embodiments, a bake strategy involves careful control of the bake ambient, introduction of reactive gases, and/or careful control of the ramping rate of the bake temperature. Examples of useful reactive gases include e.g., air, H2O, H2O2 vapor, CO2, CO, O2, O3, CH4, CH3OH, N2, ¾, NH3, N2O, NO, alcohol, acetyl acetone, formic acid, Ar, He, or their mixtures. The PEB treatment is designed to (1) drive complete evaporation of organic fragments that are generated during EUV exposure and (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated by EUV exposure into metal hydroxide, and (3) facilitate cross-linking between neighboring Sn- OH groups to form a more densely cross-linked Sn0 ₂ -like network. The bake temperature is carefully selected to achieve optimal EUV lithographic performance. Too low a PEB temperature would lead to insufficient cross-linking, and consequently less chemical contrast for development at a given dose. Too high a PEB temperature would also have detrimental impacts, including severe oxidation and film shrinkage in the unexposed region (the region that is removed by development of the patterned film to form the mask in this example), as well as, undesired interdiffusion at the interface between the photopattemed metal-containing EUV resist and an underlayer, both of which can contribute to loss of chemical contrast and an increase in defect density due to insoluble scum. The PEB treatment temperature may be between about 100°C and about 300°C, between about 170°C and about 290°C, or between about 220°C and about 250°C. In some embodiments, the PEB treatment may be conducted with pressure between atmospheric and vacuum, and a treatment duration of about 1 to 15 minutes, for example about 2 minutes. In some embodiments, PEB thermal treatment may be repeated to further increase etch selectivity.

[0078] At block 150 of the process 100, a dry chamber clean operation of the present disclosure may be performed after a PEB treatment. This allows for bake and dry chamber clean to be performed in the same process chamber. However, it will be understood that the dry chamber clean may be performed in a different process chamber than the PEB treatment operation in some embodiments.

[0079] At block 112 of the process 100, the photopattemed metal-containing resist is developed to form a resist mask. In various embodiments, the exposed regions are removed (positive tone) or the unexposed regions are removed (negative tone). In some embodiments, development may include selective deposition on either the exposed or unexposed regions of the photopattemed metal-containing resist, followed by an etching operation. In various embodiments, these processes may be dry processes or wet processes. Examples of processes for development involve an organotin oxide-containing EUV-sensitive photoresist thin film (e.g., 10-30 nm thick, such as 20 nm), subjected to a EUV exposure dose and post-exposure bake, and then developed. The photoresist film may be, for example, deposited based on a gas phase reaction of an organotin precursor such as isopropyl(tris)(dimethylamino)tin and water vapor, or may be a spin-on film comprising tin clusters in an organic matrix. The photopattemed metal-containing resist is developed by exposure to a development chemistry. In some embodiments, the development chemistry includes a halide-containing chemistry.

[0080] At block 150 of the process 100, a dry chamber clean operation of the present disclosure may be performed after development. This allows for development and dry chamber clean to be performed in the same process chamber. However, it will be understood that the dry chamber clean may be performed in a different process chamber than the development operation in some embodiments. Moreover, it will be understood that the dry chamber clean may be performed in the same or different process chamber than an etch operation in some embodiments. The etch operation may be applied to etch a substrate underlayer of the semiconductor substrate.

[0081] Figure 2 presents a flow diagram of an example method of performing a dry chamber clean according to some embodiments. The dry chamber clean may be performed after deposition, bevel and/or backside clean, bake, development, or etch operation. In some embodiments, the dry chamber clean may be performed after deposition of photoresist material and in the same process chamber as deposition of photoresist material. Aspects of the process 200 may be described with reference to Figures 3A-3D. One or more operations of the process 200 may be performed using an apparatus described in any one of Figures 13-16. In some embodiments, the operations of the process 200 may be implemented, at least in part, according to software stored in one or more non- transitory computer readable media.

[0082] At block 202 of the process 200, a semiconductor substrate with a dry-deposited metal- containing resist film on a substrate layer of the semiconductor substrate is provided in a process chamber. The composition and deposition of such dry-deposited metal-containing resist films may be described, for example, in Application PCT/US 19/31618, filed May 9, 2019, incorporated herein by reference for the disclosure of these methods and materials applicable to the present disclosure. Methods include those where polymerized organometallic materials are produced in the vapor phase and deposited on the semiconductor substrate. In particular, methods for making EUV-pattemable thin films on a surface of the semiconductor substrate comprise: mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant so as to form a polymerized organometallic material; and depositing the organometallic polymer-like material onto the surface of the semiconductor substrate. In some embodiments, more than one organometallic precursor is included in the vapor stream. In some embodiments, more than one counter-reactant is included in the vapor stream. In some embodiments, the mixing and depositing operations are performed in a continuous CVD process, an ALD process, or ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter reactants are separated in either time or space. In some embodiments, the dry-deposited metal- containing resist film is a metal oxide-containing EUV resist film. For example, an element in the metal-containing resist film is selected from a group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, the metal-containing resist film includes organo-metal oxides such as organotin oxides.

[0083] In some embodiments, the process chamber in which the semiconductor substrate is provided in may be a dry deposition chamber. In other embodiments, the process chamber in which the semiconductor substrate is provided in may be a bevel edge and/or backside clean chamber, PAB treatment chamber, PEB treatment chamber, development chamber, or etch chamber. Any of the foregoing process chambers may accumulate metal-containing resist material on internal surfaces over time. As more and more semiconductor substrates are processed in a process chamber, unintended metal-containing resist material may grow on the internal surfaces. Periodic cleaning is needed to remove the unintended deposits of metal-containing resist material. The cleaning is performed“/n situ” where the dry chamber clean is performed in the same process chamber where unintended metal-containing resist material formed.

[0084] Figure 3A shows a cross-sectional schematic illustration of a metal-containing EUV resist material 302 formed on chamber walls 304 of a process chamber. The metal-containing EUV resist material 302 may include particles or clusters of metal oxide 306. Particles or clusters of metal oxide 306 are generally difficult to remove. In some embodiments, the metal-containing EUV resist material 302 is formed by a vapor deposition method such as CVD or ALD. Over time, the metal-containing EUV resist material may accumulate in thickness on the chamber walls 304 of the process chamber. The metal-containing EUV resist material 302 may be an organotin oxide. The particles or clusters of metal oxide 306 may include tin oxide.

[0085] Returning to Figure 2, at block 204 of the process 200, an etch gas is introduced into the process chamber, where a first thickness of dry-deposited metal-containing resist material is formed on one or more surfaces of the process chamber, and where the etch gas removes the first thickness of the dry-deposited metal-containing resist material. In some embodiments, the etch gas includes a halide-containing chemistry. In some embodiments, the etch gas includes a hydrogen halide, hydrogen and halogen gas, boron trichloride, or combinations thereof. For example, the etch gas may be HC1. In some embodiments, the etch gas may remove the dry- deposited metal-containing resist material without striking a plasma. In some embodiments, the etch gas may remove the dry-deposited metal-containing resist material by heating the process chamber to an elevated temperature. The first thickness of the dry-deposited metal-containing resist material may be equal to or greater than about 2 nm, equal to or greater than about 3 nm, equal to or greater than about 5 nm, or equal to or greater than about 10 nm. The first thickness may correspond to an average thickness of film material formed on the one or more surfaces of the process chamber.

[0086] Prior to introducing the etch gas, the process chamber may be prepared with desired conditions for dry chamber cleaning. Preparation of the process chamber may achieve certain pressure conditions, levels of loose particles or film impurities, moisture levels, temperature conditions, or protection of surfaces or components (e.g., substrate support) in the process chamber from the etch gas.

[0087] In some embodiments, preparing the process chamber may include purging and/or pumping the process chamber to remove unwanted particles in the process chamber. A vacuum line or purge line may be coupled to the process chamber. The vacuum line may include a vacuum pump system, which can include a one or two stage mechanical dry pump and/or turbomolecular pump. A purge gas may be flowed into the process chamber to facilitate removal of unwanted particles in the process chamber. Such unwanted particles may include particles or flakes from the metal-containing resist material. A vacuum pump system may reduce a chamber pressure and/or remove unwanted particles from the process chamber. The vacuum pump system may be configured to produce a vacuum pressure that is in the relatively low range (e.g., between about 6 Torr and atmosphere) or in the relatively high range (e.g., between about 1 mTorr and about 6 Torr). In some embodiments, preparing the process chamber may include a combination of pumping and purging operations.

[0088] A purge of the metal organic precursor may be useful to avoid undesired byproducts and ensure sufficient removal of the metal organic CVD precursor before dry cleaning. Sufficient pump/purging and/or water dosing may be performed before dry clean to encourage complete reaction. In some embodiments, chamber walls and other components may be heated to release unreacted precursor.

[0089] In some embodiments, preparing the process chamber may include increasing a temperature of one or more surfaces in the process chamber. The one or more surfaces in the process chamber may include at least chamber walls in the process chamber. The increased temperature may facilitate removal of moisture in the process chamber. Without being limited by any theory, the presence of water vapor slows down the reaction between the etch gas and the metal-containing resist material for removal of the metal-containing resist material. In addition, the increased temperature in the process chamber promotes a higher etch rate for removal of the metal-containing resist material. One or more heaters may be thermally coupled to the one or more surfaces of the process chamber to heat the one or more surfaces to an elevated temperature. In some embodiments, the elevated temperature may be between about 20°C and about 140°C, between about 40°C and about 120°C, or between about 80°C and about 120°C.

[0090] In some embodiments, preparing the process chamber may include providing a dummy substrate on a substrate support in the process chamber. Thus, the semiconductor substrate having the dry-deposited metal-containing resist film may be transferred out of the process chamber prior to dry cleaning. That way, the semiconductor substrate provided earlier in the process chamber is not exposed to the etch gas when removing the first thickness of the dry-deposited metal- containing resist material. The dummy substrate may be provided on the substrate support to protect the substrate support (e.g., electrostatic chuck) from exposure to the etch gas during dry cleaning. Alternatively, protection of the substrate support may occur by providing a protective cover over the substrate support during dry cleaning.

[0091] The etch gas may be introduced through a showerhead or separate chamber inlet coupled to the process chamber. The etch gas may flow into the process chamber to react with the dry- deposited metal-containing resist material to form volatile products. Without being limited by any theory, an organo-metal-oxide resist material may have a tetrahedrally coordinated structure, and an etch gas with a halide-based chemistry (e.g., HBr or HC1) may protonate an oxygen lone pair to form a volatile byproduct such as R-Sn-Br. Water is a byproduct as well. The speed of the reaction may be increased by removal of water and increasing a temperature of the process chamber. After volatile products are formed, the process chamber may be pumped and purged to remove the volatile products. Additionally, the process chamber may be pumped and purged to remove residual etch gas. Such residual etch gas may cause undesired etching of subsequent semiconductor substrates.

[0092] The dry clean may be optimized for low etch selectivity or high etch rate of resist material deposited in the process chamber. That way, unwanted resist material may be quickly and efficiently removed. Low etch selectivity may be achieved for non-selective removal of photoresist material and metal oxide materials (e.g., tin oxide). Low etch selectivity may be achieved for non-selective removal of exposed EUV resist material and unexposed EUV resist material. In some embodiments, higher temperatures and/or higher pressures may result in lower etch selectivity of the etch gas. During exposure to the etch gas, the metal-containing resist material on the one or more surfaces may be subjected to an elevated temperature. The elevated temperature may be between about 20°C and about 140°C, between about 40°C and about 120°C, or between about 80°C and about 120°C. During exposure to the etch gas, the pressure in the process chamber may be high. In some embodiments, a chamber pressure is between about 0.01 Torr and atmosphere, between about 0.1 Torr and 100 Torr, or between about 0.1 Torr and about 6 Torr. In some embodiments, the chamber pressure is cycled between high and low pressures during exposure to the etch gas. Etch gas flow rate may also be tuned to control etch selectivity. In some embodiments, an etch gas flow rate is between about 50 seem and about 10000 seem, between about 100 seem and about 10000 seem, or between about 100 seem and about 2000 seem.

[0093] The etch gas serves to remove resist material from interior chamber surfaces, where the etch rate may be modulated by adjusting a temperature of the one or more surfaces of the process chamber. The resist material can be removed with an etch rate of up to 1 nm/s. Higher temperatures and/or pressures may increase the etch rate. Although the resist material can be removed using vapors at various temperatures (e.g., HC1 or HBr at a temperature greater than 10°C, or BCE at a temperature greater than 80°C, for example), a plasma can be used to further accelerate or enhance the reactivity. Accordingly, in some embodiments, the etch gas can be activated by heating or by a remote plasma source. This may further accelerate etching or enhance reactivity.

[0094] In a non-plasma thermal process for dry clean, the etch gas may be a hydrogen halide, hydrogen gas and halogen gas, boron trichloride, or mixtures thereof. In some embodiments, the hydrogen halide includes HC1, HBr, or HI. For example, the hydrogen halide can be HC1. In some embodiments, the halogen gas is Ch, Bn, or I2. In some embodiments, the etch gas is flowed with or without inert/carrier gas such as He, Ne, Ar, Xe, or N2. Though the first thickness of the metal- containing resist material is removed by an etch gas without striking a plasma, residual carbon, contaminants, or other remaining materials may be removed by exposure to plasma. In some embodiments, introduction of the etch gas may be followed by exposing the one or more surfaces to an oxidizing gas such as oxygen (O2), ozone (O3), carbon dioxide (CO2), or carbon monoxide (CO). The one or more surfaces may be exposed to an radicals and/or ions of the oxidizing gas in a plasma.

[0095] In some embodiments, the dry clean may be a plasma-based dry clean. Thus, the dry clean may occur by a direct in situ plasma or remote plasma. The process chamber may be a plasma-generating chamber or coupled to a plasma-generating chamber remote from the process chamber. The plasma-generating chamber may be an inductively-coupled plasma (ICP) reactor, transformer-coupled plasma (TCP) reactor, or capacitively-coupled plasma (CCP) reactor, employing equipment and techniques among those known in the art. In a plasma-based dry clean, the metal-containing resist material in the process chamber is exposed to radicals of certain gases. The gases may be selected from a group consisting of: HBr, HC1, BCb, SOCI2, CI2, BBr3, ¾, PCh, CH4, methanol, ammonia, formic acid, NF3, HF, and HI. Non-halogen chemistries may be used in plasma-based dry cleans. Halogen-based chemistries may be used in non-plasma thermal dry cleans.

[0096] Due to the ability to clean the as-deposited films (non-exposed or non-crosslinked) thermally, without the need for use of plasma, the approach described herein can also clean the downstream and upstream components of tool, beyond the process chamber (e.g., the exhaust lines going from the process chamber to the vacuum pump). More generally, this dry clean method can be used to clean other parts and components contaminated having a similar composition of a metal that has volatile products with -Cl, -Br, -F, -H, -CH4 _, and an oxide and/or R groups.

[0097] It is important to note that, in some embodiments, unexposed, non-crosslinked resist film can be cleaned and removed according to the approach described herein, without plasma. The exposed film has a much slower etch rate, and can use either elevated temperatures, pressures, or plasma for removal and cleaning.

[0098] In some embodiments, coatings that are compatible with halogen cleaning chemistry may be used on the chamber walls and other components exposed to the clean, such as PTFE, anodized aluminum, yttrium oxide (Y2O3), or organic polymer coatings. In some embodiments, the process chamber may include chamber parts temperature control coupled to the one or more surfaces (e.g., chamber walls) to control temperature. In some embodiments, the process chamber may include gas inlets other than the showerhead for delivery of the etch gas. The gas inlets may be positioned in regions of the process chamber with a higher concentration of the metal-containing resist material. Or, the gas inlets may be positioned in regions of the process chamber where etch gas is less likely to reach through delivery via a showerhead. In some embodiments, the gas inlets may be positioned below the substrate support, positioned in the walls of the process chamber, and/or positioned close to an exhaust of the process chamber. Multiple gas inlets may be used for delivery of the etch gas into the process chamber. This can ensure the dry clean of the entire process chamber.

[0099] For prevention of corrosion of chamber components, the etch gas may be separated from the deposition gases/precursors. In various embodiments, the etch gas is delivered into the process chamber through one or more gas inlets separate from the showerhead, and deposition gases may be delivered into the process chamber through the showerhead. In some embodiments, the showerhead may supply separate gases by keeping the gases largely segregated within the showerhead. The showerhead may include multiple plenum volumes. Multiple exhaust lines may be used to ensure separation of gases downstream from the process chamber. A switch may be operably coupled to the multiple exhaust lines so as to permit separation of etch gas chemistry from deposition gases/precursors. For example, hydrogen halide chemistry may be separated from organotin precursors and water vapor. Halides may be exhausted through a first exhaust line during a pumping/purging operation, and deposition precursors and water vapor may be exhausted through a second exhaust line during a pumping/purging operation.

[0100] To protect the showerhead, a pressure differential may be used to prevent the etch gas from entering the showerhead (e.g., backflow). In some embodiments, the etch gas may clean internal surfaces of the showerhead by flowing the etch gas through the showerhead. However, residual halides or moisture may be retained inside channels of the showerhead. In some embodiments, the showerhead may be made out of a transparent material and heated with a suitable light source. For example, an irradiation source tuned to the appropriate wavelength (e.g., IR or blue wavelength) can directly heat the residual halides and/or moisture to remove the residual halides and/or moisture. Alternatively, the residual halides and/or moisture may be removed by gas purging.

[0101] In some embodiments, periodic dry cleaning may occur upon detection. A detection source may trigger chamber clean and/or endpoint of clean. The detection source may be a sensor installed in the process chamber, such as a color-based sensor, intensity -based sensor, vision-based camera/sensor, or combination thereof. The sensor may trigger dry chamber clean by monitoring particle count or uniformity, wafer count, or thickness count. Alternatively, the sensor may trigger dry chamber clean by an in situ measurement device for chamber wall deposition. For example, the sensor may detect the presence of photoresist material using infrared (IR) measurements. After a certain amount of photoresist material is formed or a threshold particle, uniformity, wafer, or thickness count is reached, the dry chamber clean may be triggered. In some embodiments, the sensor may be installed downstream in a foreline. Such a sensor may detect what gases/byproducts are being exhausted. When volatile byproducts are no longer detected in the foreline, the dry chamber clean may be terminated.

[0102] Figure 3B shows a cross-sectional schematic illustration of the chamber walls 304 after an etch gas removes the metal-containing EUV resist material 302 from the chamber walls 304. The etch gas may be a hydrogen halide, hydrogen gas and halogen gas, or boron trichloride. The chamber walls 304 may be heated to an elevated temperature to promote low etch selectivity. The process chamber may be increased to a high pressure to promote low etch selectivity. Removal of the metal-containing EUV resist material 302 may occur without using plasma. Residual particles or clusters of metal oxide 306 may remain on the chamber walls 304 after exposure to the etch gas. In addition, residual etch gas 308 may remain in the process chamber.

[0103] Figure 4 illustrates an example dry chamber clean mechanism for chemical reactions of hydrogen chloride or hydrogen bromide with organotin oxide/hydroxide resist materials coated on internal surfaces of a process chamber according to some embodiments. Hydrogen halide (HC1 or HBr) reacts with an EUV resist such as an organotin oxide/hydroxide resist material coating internal chamber surfaces and downstream components. The hydrogen halide cleaves Sn-OH bonds and Sn-O-Sn bonds to generate H2O and volatile organotin halide and tin halide products, which can be subsequently pumped away.

[0104] Returning to Figure 2, at block 206 of the process 200, the process chamber is optionally purged to remove residual etch gas from the process chamber. The purge operation may involve flowing a purge gas into the process chamber or a combination of flowing a purge gas and pumping the process chamber to a desired chamber pressure. The purge gas may be an inert gas and/or a reactive gas. The reactive gas may react with residual etch gas to facilitate ease of removal. The reactive gas may be, for example, a tin-based precursor such as an organotin precursor. The inert gas may be Ar, He, Xe, or N2. The chamber pressure may be between about 0.1 Torr and about 6 Torr.

[0105] The residual etch gas may be exhausted from the process chamber. In some embodiments, the purge operation may also be referred to as dehalogenation. Halides may readily stick to chamber walls, chamber components, or wafers. If the halides stick to the wafer, there is an increased risk of the halides (e.g., bromine) being released from the wafer during EUV scanning, thereby corroding or damaging the scanner. Furthermore, if halides stick to the chamber walls or chamber components, the halides may readily form organic salts with subsequent precursors during dry deposition operations. Purging the residual etch gas may exhaust through a separate exhaust line than the deposition precursors and counter-reactant (e.g., water vapor).

[0106] In some embodiments, the purge operation may proceed at a high temperature. The high temperature may facilitate removal of halides from the process chamber. In one example, one or more heaters coupled to the one or more surfaces of the process chamber may heat the process chamber to the high temperature. In another example, one or more IR sources or LEDs may be installed in the process chamber to heat the process chamber to the high temperature. The high temperature may be between about 20°C and about 140°C or between about 80°C and about 120°C.

[0107] A variety of direct or remote plasma-based treatments are useful to accelerate the removal of residual etch gas (e.g., Cl-containing chemistry or Br-containing chemistry), where the residual etch gas may cover internal surfaces of the process chamber following removal of metal-containing resist material. Such treatments may be used individually or in combination to recover the internal surfaces of the process chamber. The internal surfaces of the process chamber may be, for example, aluminum oxide-based ceramics, anodized aluminum, and stainless steel hardware components (generally downstream). Recovery of the internal surfaces may suggest being free or substantially free of residual etch gas (e.g., free of Cl and/or Br). In one approach, a remote plasma-based treatment is a remote NF3 plasma process, since both F radicals and F2 gas are generated and may be effective in converting residual halide-containing chemistries to volatile halogens. The volatile halogens are then pumped away, leaving behind passivated surfaces such as Al-F passivated surfaces. Reactive gases used in the remote plasma process may include but are not limited to NF3, SF ₆ , CF4, or CIF3. In another approach that may be considered less aggressive but also effective is an oxygen-based plasma process. For example, the oxygen-based plasma process may target the oxidation of bromide surface residues to form volatile bromine gas (Bn). Oxygen -based reactants may include but are not limited to O2, O3, a mixture of Fh and O2, and N2O. For example, after a fluorine-based clean, an H2/O2 plasma at low pressure of N2O plasma may be utilized for recovery of internal surfaces. In some embodiments, it may be advantageous to cycle between a fluorine -based plasma process and an oxygen-based plasma process or utilize a mixture of a fluorine -based chemistry and oxygen-based chemistry. In some embodiments, it may be advantageous to interrupt a sequence with a hydrogen-containing plasma process (e.g., H plasma), which can target the formation of volatile hydrogen halide (e.g., HBr, HC1) based byproducts. This can also leave behind passivated surfaces. In some embodiments, a plasma-based treatment or a sequence of plasma-based treatments may be terminated with an oxygen-based plasma conditioning step. In an oxygen-based plasma conditioning step, the internal surfaces may be exposed to an oxygen-based plasma to form a metal oxide (e.g., aluminum oxide) passivation layer for recovery. As described below, the recovered internal surfaces may be subsequently covered/seasoned with photoresist film (to avoid undesirable first wafer effects) before re-initiating deposition operations on semiconductor substrates.

[0108] In other embodiments, a non-plasma treatment may be useful to accelerate removal of residual etch gas (e.g., Cl-containing chemistry or Br-containing chemistry), where the residual etch gas may cover internal surfaces of the process chamber following removal of metal-containing resist material. Oxidizing gas may be introduced to oxidize residual halides such as Cl or Br on internal chamber surfaces. Thus, the non-plasma treatment may include delivering a flow of ozone gas (O3) and/or oxygen gas (O2). For instance, the non-plasma treatment may include delivering a flow of ozone gas and oxygen gas (e.g., 0.1%-30% ozone in oxygen). The non-plasma treatment can have the additional benefit of oxidizing and removing any remaining organic material such as carbon-containing and hydrogen-containing residues remaining on internal surfaces.

[0109] Figure 3C shows a cross-sectional schematic illustration of the chamber walls 304 after dehalogenation to remove residual etch gas 308 from the process chamber. Pumping/purging operations may be performed to exhaust the residual etch gas 308 from the process chamber. In some embodiments, the chamber walls 304 or other components of the process chamber may be heated to promote release of the residual etch gas 308. In some embodiments, direct or remote plasma-based treatments may be applied to remove the residual etch gas 308, where such plasma- based treatments may include a fluorine-based plasma process, oxygen-based plasma process, or combinations thereof. Particles or clusters of metal oxide 306 may remain on the chamber walls 304.

[0110] Returning to Figure 2, at block 208 of the process 200, the one or more surfaces of the process chamber are optionally conditioned by forming a second thickness of the dry-deposited metal-containing resist material on the one or more surfaces of the process chamber. The second thickness is less than the first thickness of the dry-deposited metal-containing resist material. In some embodiments, the second thickness is equal to or greater than about 1 nm, equal to or greater than about 2 nm, equal to or greater than about 3 nm, or between about 1 nm and about 5 nm. Alternatively, the one or more surfaces of the process chamber are optionally conditioned by forming a protective film different than the dry-deposited metal-containing resist material. Such a protective film may be a variation of SnO _x C _y . After exposure to the etch gas, the one or more surfaces are left exposed. Exposed surfaces in the process chamber may be vulnerable to attack especially by halogen-based species. The conditioning operation may provide protection of the one or more surfaces. Additionally, the conditioning operation may cover residual particles or clusters of metal oxide stuck on the one or more surfaces. That way, the particles or clusters of metal oxide are less likely to contaminate wafers during subsequent processing.

[0111] Conditioning the one or more surfaces of the process chamber may occur by a vapor- based deposition technique such as a CVD or ALD technique. Organometallic materials are produced in the vapor phase and deposited on the one or more surfaces of the process chamber. The organometallic materials may be, for example, deposited based on a gas phase reaction of an organotin precursor such as isopropyl(tris)(dimethylamino)tin and water vapor. The flow of water vapor may be relatively low. During conditioning, the substrate support may be protected or covered by a dummy wafer or other protective covering. The second thickness of the metal- containing resist material may be formed on chamber walls, floors, and ceilings. In addition, the second thickness of the metal-containing resist material may be formed on chamber components such as gas inlets, showerheads, and exhaust lines. After deposition of the second thickness of the metal-containing resist material, pumping/purging operations may follow to remove excess precursor and/or counter-reactant. Conditioning the one or more surfaces of the process chamber can trap residual particles of metal oxide and limit particle contamination. [0112] Figure 3D shows a cross-sectional schematic illustration of a metal-containing resist material 310 formed on the chamber walls 304 of the process chamber. The metal-containing EUV resist material 310 may be re-deposited in a conditioning operation to protect the chamber walls 304 and trap the particles or clusters of metal oxide 306 from contaminating wafers during processing. This may also be referred to as chamber seasoning. The metal-containing EUV resist material 310 is formed by a vapor deposition method such as CVD or ALD. In some embodiments, the metal-containing EUV resist material 310 may be an organotin oxide. By conditioning/seasoning the chamber walls 304 and other internal surfaces of the process chamber, undesirable first wafer effects are mitigated when re-initiating deposition operations on semiconductor substrates.

[0113] While this disclosure frequently refers to the cleaning of EUV-sensitive films that have been exposed and/or developed, the cleaning processes described can be extended to EUV films of similar composition (e.g., other MO _x R _y -based films), for example, other films containing a metal oxide, in which the metal can form volatile products with -Cl, -Br, -F, -H, -CEB, etc., as described herein, including unexposed EUV resist films. Additionally, in some embodiments, films other than EUV resists can be cleaned by this method, for example hard masks, UV resists or films of similar composition having other applications; in this respect, the described cleaning process relates to the film’s chemical composition, as opposed to its function.

[0114] Also, in some embodiments, cleaning in accordance with this disclosure may be conducted by combining a thermal process to remove the majority of the contamination residue, followed by a plasma process to remove any additional residue. This is potentially applicable in all applications, including chamber clean, backside, bevel, strip, and rework. In some embodiments, this approach may be particularly advantageously applied to chamber clean, where the plasma can provide enhanced control of the surface clean for thoroughness. Downstream, where the clean may be mainly for preventing blockage, the clean quality may not be as important, and it may be acceptable if some residue remains following the clean.

[0115] Figure 5 shows a graph comparing HC1, HBr, and BCE, in etching metal-containing EUV resist versus time in a cleaning operation. As shown in Figure 5, the target metal-containing EUV resist material can be thermally removed by each of HC1, HBr, and BCE, at elevated temperatures, and the etch rates are fast. [0116] Figure 6 shows a graph comparing etch rates for different metal-containing EUV resist materials when using HBr as an etch gas. Each of the lines represent different concentrations of tin oxide in the metal-containing EUV resist. Each of the materials have slightly different etch rates, but each of the materials can be etched quickly using HBr as an etch gas. The higher the concentration of tin oxide, the slower the etch rate.

[0117] Figure 7 shows a graph illustrating the effects of temperature on etch selectivity for removal of exposed and unexposed regions of photopatterned metal-containing EUV resist. Dashed lines correspond to exposed regions of metal-containing EUV resist, and solid lines correspond to unexposed regions of metal-containing EUV resist. At low temperatures of 0°C or 10°C, low etch rates were observed for both exposed and unexposed regions of the metal- containing EUV resist. However, at a high temperature of 80°C, high etch rates were observed for both exposed and unexposed regions of the metal-containing EUV resist. Thus, high etch selectivity occurs with lower temperatures, and lower etch selectivity occurs with higher temperatures. Figure 8 A shows a graph illustrating the effects of temperature on selectivity for removal of EUV resist. As shown in Figure 8A, etch selectivity decreases in a nonlinear manner with increasing temperature. Figure 8B shows a bar graph illustrating the effects of temperature on etch rate for removal of EUV resist. As shown in Figure 8B, the etch rate increases with increasing temperature.

[0118] Figure 9 shows a graph illustrating the effects of pressure on etch selectivity for removal of exposed and unexposed regions of photopatterned metal-containing EUV resist. Dashed lines correspond to exposed regions of metal-containing EUV resist, and solid lines correspond to unexposed regions of metal-containing EUV resist. At a low pressure of 20 mTorr, low etch rates were observed for exposed regions of the metal-containing EUV resist while moderately high etch rates were observed for unexposed regions of the metal-containing EUV resist. However, at a higher pressure of 300 mTorr, high etch rates were observed for both exposed and unexposed regions of the metal-containing EUV resist. High etch selectivity is seen with higher pressure, and high etch rates are seen with higher pressure. Figure 10A shows a graph illustrating the effects of pressure on selectivity for removal of EUV resist. In Figure 10A, etch selectivity increases with increasing pressure. Figure 10B shows a bar graph illustrating the effects of pressure on etch rate for removal of EUV resist. In Figure 10B, the etch rate increases with increasing pressure. [0119] Figures 11A-11E show graphs illustrating the performance of HC1 as an etch gas for different pressures and temperatures. Figure 11A shows a graph illustrating etch amount of EUV resist material over time using HC1 as an etch gas at various temperatures of -10°C, 20°C, and 40°C at a fixed pressure of 20 mTorr. Figure 1 IB shows a graph illustrating etch amount of EUV resist material over time using HC1 as an etch gas at various temperatures of -10°C and 20°C at a fixed pressure of 100 mTorr. Figure 11C shows a graph of etch amount of EUV resist material over time comparing HC1 and HBr. Figure 1 ID shows a bar graph illustrating etch rates of EUV resist material using HC1 as an etch gas at different temperatures. Figure 11E shows a bar graph illustrating etch rates of EUV resist material using HC1 as an etch gas at different pressures.

[0120] Figure 12 shows a graph illustrating an amount of bromine over time in a process chamber when purging. As shown in Figure 12, purging is able to reduce HBr on chamber walls over time. The purge gas is Ar and the chamber wall is heated to 60°C. After 60 minutes, the amount of HBr in the process chamber is less than 200 x 10 ¹² atoms/cm ² .

Apparatus

[0121] An apparatus of the present disclosure is configured for performing an in situ dry chamber clean. The apparatus may be configured to perform other processing operations such as deposition, bevel and backside cleaning, post-application baking, post-exposure baking, photoresist reworking, descum, smoothing, curing, etching, and other operations. In some embodiments, the apparatus is configured to perform all dry operations. For instance, the apparatus is configured to perform dry deposition of EUV resist in a process chamber as well as dry clean of EUV resist formed on internal surfaces of the process chamber. This enhances throughput and reduces the likelihood of contamination by exposing a substrate to vacuum breaks between wet and dry operations.

[0122] The apparatus configured for dry chamber clean includes a process chamber with a substrate support. The apparatus may include one or more vacuum lines coupled to the process chamber for pressure control and one or more etch gas lines coupled to the process chamber for delivery of etch gas. In some embodiments, there may be multiple vacuum lines for separating etch gas chemistries from deposition precursors and counter-reactants. In some embodiments, there may be multiple gas inlets positioned within the process chamber to flow etch gas near regions where unintended EUV resist material tend to form. In some embodiments, the etch gas includes a halide-containing chemistry such as a hydrogen halide (e.g., HBr or HC1). The apparatus may include one or more heaters for temperature control. Such heaters may be provided in the process chamber and/or in the substrate support. In some embodiments, the one or more heaters may include an IR source. The apparatus may further include one or more sensors for sensing particle count, wafer count, thickness count, or other parameters for triggering the dry chamber clean and/or endpoint of the dry chamber clean.

[0123] Figure 13 depicts a schematic illustration of an embodiment of process station 1300 having a process chamber body 1302 for maintaining a low-pressure environment that is suitable for implementation of described dry clean embodiments. A plurality of process stations 1300 may be included in a common low pressure process tool environment. For example, Figure 14 depicts an embodiment of a multi-station processing tool 1400, such as a VECTOR® processing tool available from Earn Research Corporation, Fremont, CA. In some embodiments, one or more hardware parameters of the process station 1300 including those discussed in detail below may be adjusted programmatically by one or more computer controllers 1350.

[0124] A process station may be configured as a module in a cluster tool. Figure 16 depicts a semiconductor process cluster tool architecture with vacuum-integrated deposition and patterning modules suitable for implementation of the embodiments described herein. Such a cluster process tool architecture can include resist deposition, resist exposure (EUV scanner), resist dry development and etch modules, as described above and further below with reference to Figures 15 and 16.

[0125] In some embodiments, certain of the processing functions can be performed consecutively in the same module, for example dry development and etch. And embodiments of this disclosure are directed to methods and apparatus for receiving a wafer, including a photopattemed EUV resist thin film layer disposed on a layer or layer stack to be etched, to a dry development/etch chamber following photopatteming in an EUV scanner; dry developing photopattemed EUV resist thin film layer; and then etching the underlying layer using the patterned EUV resist as a mask, as described herein.

[0126] Returning to Figure 13, process station 1300 fluidly communicates with reactant delivery system 1301a for delivering process gases to a distribution showerhead 1306. Reactant delivery system 1301a optionally includes a mixing vessel 1304 for blending and/or conditioning process gases, for delivery to showerhead 1306. One or more mixing vessel inlet valves 1320 may control introduction of process gases to mixing vessel 1304. Where plasma exposure is used, plasma may also be delivered to the showerhead 1306 or may be generated in the process station 1300. As noted above, in at least some embodiments, non-plasma thermal exposure is favored.

[0127] Figure 13 includes an optional vaporization point 1303 for vaporizing liquid reactant to be supplied to the mixing vessel 1304. In some embodiments, a liquid flow controller (LFC) upstream of vaporization point 1303 may be provided for controlling a mass flow of liquid for vaporization and delivery to process station 1300. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. A plunger valve of the LFC may then be adjusted responsive to feedback control signals provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM.

[0128] Showerhead 1306 distributes process gases toward substrate 1312. In the embodiment shown in Figure 13, the substrate 1312 is located beneath showerhead 1306 and is shown resting on a pedestal 1308. Showerhead 1306 may have any suitable shape, and may have any suitable number and arrangement of ports for distributing process gases to substrate 1312.

[0129] In some embodiments, pedestal 1308 may be raised or lowered to expose substrate 1312 to a volume between the substrate 1312 and the showerhead 1306. It will be appreciated that, in some embodiments, pedestal height may be adjusted programmatically by a suitable computer controller 1350.

[0130] In some embodiments, pedestal 1308 may be temperature controlled via heater 1310. In some embodiments, the pedestal 1308 may be heated to a temperature of greater than 0°C and up to 300°C or more, during exposure of a photopattemed resist to clean chemistry reactant gas (e.g., HC1, HBr, HI, and BCL), as described in disclosed embodiments.

[0131] Further, in some embodiments, pressure control for process station 1300 may be provided by a butterfly valve 1318. As shown in the embodiment of Figure 13, butterfly valve 1318 throttles a vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of process station 1300 may also be adjusted by varying a flow rate of one or more gases introduced to the process station 1300. [0132] In some embodiments, a position of showerhead 1306 may be adjusted relative to pedestal 1308 to vary a volume between the substrate 1312 and the showerhead 1306. Further, it will be appreciated that a vertical position of pedestal 1308 and/or showerhead 1306 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, pedestal 1308 may include a rotational axis for rotating an orientation of substrate 1312. It will be appreciated that, in some embodiments, one or more of these example adjustments may be performed programmatically by one or more suitable computer controllers 1350.

[0133] Where plasma may be used, for example in gentle plasma-based dry development embodiments and /or etch operations conducted in the same chamber, showerhead 1306 and pedestal 1308 electrically communicate with a radio frequency (RF) power supply 1314 and matching network 1316 for powering a plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of a process station pressure, a gas concentration, an RF source power, an RF source frequency, and a plasma power pulse timing. For example, RF power supply 1314 and matching network 1316 may be operated at any suitable power to form a plasma having a desired composition of radical species. Examples of suitable powers are up to about 500W.

[0134] In some embodiments, instructions for a controller 1350 may be provided via input/output control (IOC) sequencing instructions. In one example, the instructions for setting conditions for a process phase may be included in a corresponding recipe phase of a process recipe. In some cases, process recipe phases may be sequentially arranged, so that all instructions for a process phase are executed concurrently with that process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe phase. For example, a recipe phase may include instructions for setting a flow rate of clean chemistry reactant gas (e.g., HC1, HBr, HI, and BCb) and time delay instructions for the recipe phase. In some embodiments, the controller 1350 may include any of the features described below with respect to system controller 1450 of Figure 14.

[0135] As described above, one or more process stations may be included in a multi- station processing tool. Figure 14 shows a schematic view of an embodiment of a multi-station processing tool 1400 with an inbound load lock 1402 and an outbound load lock 1404, either or both of which may include a remote plasma source. A robot 1406 at atmospheric pressure is configured to move wafers from a cassette loaded through a pod 1408 into inbound load lock 1402 via an atmospheric port 1410. A wafer is placed by the robot 1406 on a pedestal 1412 in the inbound load lock 1402, the atmospheric port 1410 is closed, and the load lock is pumped down. Where the inbound load lock 1402 includes a remote plasma source, the wafer may be exposed to a remote plasma treatment to treat the silicon nitride surface in the load lock prior to being introduced into a processing chamber 1414. Further, the wafer also may be heated in the inbound load lock 1402 as well, for example, to remove moisture and adsorbed gases. Next, a chamber transport port 1416 to processing chamber 1414 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal of a first station shown in the reactor for processing. While the embodiment depicted in Figure 14 includes load locks, it will be appreciated that, in some embodiments, direct entry of a wafer into a process station may be provided.

[0136] The depicted processing chamber 1414 includes four process stations, numbered from 1 to 4 in the embodiment shown in Figure 14. Each station has a heated pedestal (shown at 1418 for station 1), and gas line inlets. It will be appreciated that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between dry development and etch process modes. Additionally or alternatively, in some embodiments, processing chamber 1414 may include one or more matched pairs of dry development and etch process stations. While the depicted processing chamber 1414 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments a processing chamber may have three or fewer stations.

[0137] Figure 14 depicts an embodiment of a wafer handling system 1490 for transferring wafers within processing chamber 1414. In some embodiments, wafer handling system 1490 may transfer wafers between various process stations and/or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. Figure 14 also depicts an embodiment of a system controller 1450 employed to control process conditions and hardware states of process tool 1400. System controller 1450 may include one or more memory devices 1456, one or more mass storage devices 1454, and one or more processors 1452. Processor 1452 may include a CPU or computer, analog, and/or digital input/output connections, stepper motor controller boards, etc. [0138] In some embodiments, system controller 1450 controls all of the activities of process tool 1400. System controller 1450 executes system control software 1458 stored in mass storage device 1454, loaded into memory device 1456, and executed on processor 1452. Alternatively, the control logic may be hard coded in the controller 1450. Applications Specific Integrated Circuits, Programmable Logic Devices (e.g., field-programmable gate arrays, or FPGAs) and the like may be used for these purposes. In the following discussion, wherever“software” or“code” is used, functionally comparable hard coded logic may be used in its place. System control software 1458 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and/or station pressure, chamber and/or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and/or susceptor position, and other parameters of a particular process performed by process tool 1400. System control software 1458 may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components used to carry out various process tool processes. System control software 1458 may be coded in any suitable computer readable programming language.

[0139] In some embodiments, system control software 1458 may include input/output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and/or programs stored on mass storage device 1454 and/or memory device 1456 associated with system controller 1450 may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0140] A substrate positioning program may include program code for process tool components that are used to load the substrate onto pedestal 1418 and to control the spacing between the substrate and other parts of process tool 1400.

[0141] A process gas control program may include code for controlling gas composition (e.g., HBr, HC1 or BCF, gas as described herein) and flow rates and optionally for flowing gas into one or more process stations prior to deposition in order to stabilize the pressure in the process station. A pressure control program may include code for controlling the pressure in the process station by regulating, for example, a throttle valve in the exhaust system of the process station, a gas flow into the process station, etc.

[0142] A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas (such as helium) to the substrate.

[0143] A plasma control program may include code for setting RF power levels applied to the process electrodes in one or more process stations in accordance with the embodiments herein.

[0144] A pressure control program may include code for maintaining the pressure in the reaction chamber in accordance with the embodiments herein.

[0145] In some embodiments, there may be a user interface associated with system controller 1450. The user interface may include a display screen, graphical software displays of the apparatus and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0146] In some embodiments, parameters adjusted by system controller 1450 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing the user interface.

[0147] Signals for monitoring the process may be provided by analog and/or digital input connections of system controller 1450 from various process tool sensors. The signals for controlling the process may be output on the analog and digital output connections of process tool 1400. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0148] System controller 1450 may provide program instructions for implementing the above- described deposition processes. The program instructions may control a variety of process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate dry development and/or etch processes according to various embodiments described herein.

[0149] The system controller 1450 will typically include one or more memory devices and one or more processors configured to execute the instructions so that the apparatus will perform a method in accordance with disclosed embodiments. Machine-readable media containing instructions for controlling process operations in accordance with disclosed embodiments may be coupled to the system controller 1450.

[0150] In some implementations, the system controller 1450 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the“controller,” which may control various components or subparts of the system or systems. The system controller 1450, depending on the processing conditions and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.

[0151] Broadly speaking, the system controller 1450 may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the system controller 1450 in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.

[0152] The system controller 1450, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 1450 may be in the“cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 1450 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the system controller 1450 is configured to interface with or control. Thus as described above, the system controller 1450 may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0153] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a dry development chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.

[0154] As noted above, depending on the process step or steps to be performed by the tool, the system controller 1450 might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

[0155] Inductively coupled plasma (ICP) reactors which, in certain embodiments, may be suitable for etch operations suitable for implementation of some embodiments, are now described. Although ICP reactors are described herein, in some embodiments, it should be understood that capacitively coupled plasma reactors may also be used.

[0156] Figure 15 schematically shows a cross-sectional view of an inductively coupled plasma apparatus 1500 appropriate for implementing certain embodiments or aspects of embodiments such as dry development and/or etch, an example of which is a Kiyo® reactor, produced by Lam Research Corp. of Fremont, CA.

[0157] The inductively coupled plasma apparatus 1500 includes an overall process chamber 1524 structurally defined by chamber walls 1501 and a window 1511. The chamber walls 1501 may be fabricated from stainless steel or aluminum. The window 1511 may be fabricated from quartz or other dielectric material. An optional internal plasma grid 1550 divides the overall process chamber into an upper sub-chamber 1502 and a lower sub chamber 1503. In most embodiments, plasma grid 1550 may be removed, thereby utilizing a chamber space made of sub chambers 1502 and 1503. A chuck 1517 is positioned within the lower sub-chamber 1503 near the bottom inner surface. The chuck 1517 is configured to receive and hold a semiconductor wafer 1519 upon which the etching and deposition processes are performed. The chuck 1517 can be an electrostatic chuck for supporting the wafer 1519 when present. In some embodiments, an edge ring (not shown) surrounds chuck 1517, and has an upper surface that is approximately planar with a top surface of the wafer 1519, when present over chuck 1517. The chuck 1517 also includes electrostatic electrodes for chucking and dechucking the wafer 1519. A filter and DC clamp power supply (not shown) may be provided for this purpose. Other control systems for lifting the wafer 1519 off the chuck 1517 can also be provided. The chuck 1517 can be electrically charged using an RF power supply 1523. The RF power supply 1523 is connected to matching circuitry 1521 through a connection 1527. The matching circuitry 1521 is connected to the chuck 1517 through a connection 1525. In this manner, the RF power supply 1523 is connected to the chuck 1517. In various embodiments, a bias power of the electrostatic chuck may be set at about 50V or may be set at a different bias power depending on the process performed in accordance with disclosed embodiments. For example, the bias power may be between about 20 Vb and about 100 V, or between about 30 V and about 150 V.

[0158] Elements for plasma generation include a coil 1533 is positioned above window 1511. In some embodiments, a coil is not used in disclosed embodiments. The coil 1533 is fabricated from an electrically conductive material and includes at least one complete turn. The example of a coil 1533 shown in Figure 15 includes three turns. The cross sections of coil 1533 are shown with symbols, and coils having an“X” extend rotationally into the page, while coils having a“·” extend rotationally out of the page. Elements for plasma generation also include an RF power supply 1541 configured to supply RF power to the coil 1533. In general, the RF power supply 1541 is connected to matching circuitry 1539 through a connection 1545. The matching circuitry 1539 is connected to the coil 1533 through a connection 1543. In this manner, the RF power supply 1541 is connected to the coil 1533. An optional Faraday shield 1549a is positioned between the coil 1533 and the window 1511. The Faraday shield 1549a may be maintained in a spaced apart relationship relative to the coil 1533. In some embodiments, the Faraday shield 1549a is disposed immediately above the window 1511. In some embodiments, the Faraday shield 1549b is between the window 1511 and the chuck 1517. In some embodiments, the Faraday shield 1549b is not maintained in a spaced apart relationship relative to the coil 1533. For example, the Faraday shield 1549b may be directly below the window 1511 without a gap. The coil 1533, the Faraday shield 1549a, and the window 1511 are each configured to be substantially parallel to one another. The Faraday shield 1549a may prevent metal or other species from depositing on the window 1511 of the process chamber 1524.

[0159] Process gases may be flowed into the process chamber through one or more main gas flow inlets 1560 positioned in the upper sub-chamber 1502 and/or through one or more side gas flow inlets 1570. Likewise, though not explicitly shown, similar gas flow inlets may be used to supply process gases to a capacitively coupled plasma processing chamber. A vacuum pump, e.g., a one or two stage mechanical dry pump and/or turbomolecular pump 1540, may be used to draw process gases out of the process chamber 1524 and to maintain a pressure within the process chamber 1524. For example, the vacuum pump may be used to evacuate the lower sub-chamber 1503 during a purge operation of ALD. A valve-controlled conduit may be used to fluidically connect the vacuum pump to the process chamber 1524 so as to selectively control application of the vacuum environment provided by the vacuum pump. This may be done employing a closed loop-controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown), during operational plasma processing. Likewise, a vacuum pump and valve controlled fluidic connection to the capacitively coupled plasma processing chamber may also be employed.

[0160] During operation of the apparatus 1500, one or more process gases may be supplied through the gas flow inlets 1560 and/or 1570. In certain embodiments, process gas may be supplied only through the main gas flow inlet 1560, or only through the side gas flow inlet 1570. In some cases, the gas flow inlets shown in the figure may be replaced by more complex gas flow inlets, one or more showerheads, for example. The Faraday shield 1549a and/or optional grid 1550 may include internal channels and holes that allow delivery of process gases to the process chamber 1524. Either or both of Faraday shield 1549a and optional grid 1550 may serve as a showerhead for delivery of process gases. In some embodiments, a liquid vaporization and delivery system may be situated upstream of the process chamber 1524, such that once a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process chamber 1524 via a gas flow inlet 1560 and/or 1570.

[0161] Radio frequency power is supplied from the RF power supply 1541 to the coil 1533 to cause an RF current to flow through the coil 1533. The RF current flowing through the coil 1533 generates an electromagnetic field about the coil 1533. The electromagnetic field generates an inductive current within the upper sub-chamber 1502. The physical and chemical interactions of various generated ions and radicals with the wafer 1519 etch features of and selectively deposit layers on the wafer 1519.

[0162] If the plasma grid 1550 is used such that there is both an upper sub-chamber 1502 and a lower sub-chamber 1503, the inductive current acts on the gas present in the upper sub-chamber 1502 to generate an electron-ion plasma in the upper sub-chamber 1502. The optional internal plasma grid 1550 limits the amount of hot electrons in the lower sub-chamber 1503. In some embodiments, the apparatus 1500 is designed and operated such that the plasma present in the lower sub-chamber 1503 is an ion-ion plasma.

[0163] Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, though the ion-ion plasma will have a greater ratio of negative ions to positive ions. Volatile etching and/or deposition byproducts may be removed from the lower sub-chamber

1503 through port 1522. The chuck 1517 disclosed herein may operate at elevated temperatures ranging between about 10°C and about 250°C. The temperature will depend on the process operation and specific recipe.

[0164] Apparatus 1500 may be coupled to facilities (not shown) when installed in a clean room or a fabrication facility. Facilities include plumbing that provide processing gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to apparatus 1500, when installed in the target fabrication facility. Additionally, apparatus 1500 may be coupled to a transfer chamber that allows robotics to transfer semiconductor wafers into and out of apparatus 1500 using typical automation.

[0165] In some embodiments, a system controller 1530 (which may include one or more physical or logical controllers) controls some or all of the operations of a process chamber 1524. The system controller 1530 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 1500 includes a switching system for controlling flow rates and durations when disclosed embodiments are performed. In some embodiments, the apparatus 1500 may have a switching time of up to about 500 ms, or up to about 750 ms. Switching time may depend on the flow chemistry, recipe chosen, reactor architecture, and other factors.

[0166] In some implementations, the system controller 1530 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be integrated into the system controller 1530, which may control various components or subparts of the system or systems. The system controller , depending on the processing parameters and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system.

[0167] Broadly speaking, the system controller 1530 may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer.

[0168] The system controller 1530, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the“cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 1530 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the system controller 1530 may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0169] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a dry development chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers.

[0170] As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory.

[0171] EUVL patterning may be conducted using any suitable tool, often referred to as a scanner, for example the TWINSCAN NXE: 3300B® platform supplied by ASML of Veldhoven, NL). The EUVL patterning tool may be a standalone device from which the substrate is moved into and out of for deposition and etching as described herein. Or, as described below, the EUVL patterning tool may be a module on a larger multi-component tool. Figure 16 depicts a semiconductor process cluster tool architecture with vacuum-integrated deposition, EUV patterning and dry development/etch modules that interface with a vacuum transfer module, suitable for implementation of the processes described herein. While the processes may be conducted without such vacuum integrated apparatus, such apparatus may be advantageous in some implementations.

[0172] Figure 16 depicts a semiconductor process cluster tool architecture with vacuum- integrated deposition and patterning modules that interface with a vacuum transfer module, suitable for implementation of processes described herein. The arrangement of transfer modules to“transfer” wafers among multiple storage facilities and processing modules may be referred to as a“cluster tool architecture” system. Deposition and patterning modules are vacuum-integrated, in accordance with the requirements of a particular process. Other modules, such as for etch, may also be included on the cluster.

[0173] A vacuum transport module (VTM) 1638 interfaces with four processing modules 1620a- 1620d, which may be individually optimized to perform various fabrication processes. By way of example, processing modules 1620a-1620d may be implemented to perform deposition, evaporation, ELD, dry development, etch, strip, and/or other semiconductor processes. For example, module 1620a may be an ALD reactor that may be operated to perform in a non-plasma, thermal atomic layer depositions as described herein, such as Vector tool, available from Lam Research Corporation, Fremont, CA. And module 1620b may be a PECVD tool, such as the Lam Vector®. It should be understood that the figure is not necessarily drawn to scale.

[0174] Airlocks 1642 and 1646, also known as a loadlocks or transfer modules, interface with the VTM 1638 and a patterning module 1640. For example, as noted above, a suitable patterning module may be the TWINSCAN NXE: 3300B® platform supplied by ASML of Veldhoven, NL). This tool architecture allows for work pieces, such as semiconductor substrates or wafers, to be transferred under vacuum so as not to react before exposure. Integration of the deposition modules with the lithography tool is facilitated by the fact that EUVL also requires a greatly reduced pressure given the strong optical absorption of the incident photons by ambient gases such as FLO, O2, etc.

[0175] As noted above, this integrated architecture is just one possible embodiment of a tool for implementation of the described processes. The processes may also be implemented with a more conventional stand-alone EUVL scanner and a deposition reactor, such as a Lam Vector tool, either stand alone or integrated in a cluster architecture with other tools, such as etch, strip etc. (e.g., Lam Kiyo or Gamma tools), as modules, for example as described with reference to Figure 16 but without the integrated patterning module.

[0176] Airlock 1642 may be an“outgoing” loadlock, referring to the transfer of a substrate out from the VTM 1638 serving a deposition module 1620a to the patterning module 1640, and airlock 1646 may be an“ingoing” loadlock, referring to the transfer of a substrate from the patterning module 1640 back in to the VTM 1638. The ingoing loadlock 1646 may also provide an interface to the exterior of the tool for access and egress of substrates. Each process module has a facet that interfaces the module to VTM 1638. For example, deposition process module 1620a has facet 1636. Inside each facet, sensors, for example, sensors 1-18 as shown, are used to detect the passing of wafer 1626 when moved between respective stations. Patterning module 1640 and airlocks 1642 and 1646 may be similarly equipped with additional facets and sensors, not shown.

[0177] Main VTM robot 1622 transfers wafer 1626 between modules, including airlocks 1642 and 1646. In one embodiment, robot 1622 has one arm, and in another embodiment, robot 1622 has two arms, where each arm has an end effector 1624 to pick wafers such as wafer 1626 for transport. Front-end robot 1644, in is used to transfer wafers 1626 from outgoing airlock 1642 into the patterning module 1640, from the patterning module 1640 into ingoing airlock 1646. Front-end robot 1644 may also transport wafers 1626 between the ingoing loadlock and the exterior of the tool for access and egress of substrates. Because ingoing airlock module 1646 has the ability to match the environment between atmospheric and vacuum, the wafer 1626 is able to move between the two pressure environments without being damaged.

[0178] It should be noted that a EUVL tool typically operates at a higher vacuum than a deposition tool. If this is the case, it is desirable to increase the vacuum environment of the substrate during the transfer between the deposition to the EUVL tool to allow the substrate to degas prior to entry into the patterning tool. Outgoing airlock 1642 may provide this function by holding the transferred wafers at a lower pressure, no higher than the pressure in the patterning module 1640, for a period of time and exhausting any off-gassing, so that the optics of the patterning tool 1640 are not contaminated by off-gassing from the substrate. A suitable pressure for the outgoing, off-gassing airlock is no more than IE-8 Torr. [0179] In some embodiments, a system controller 1650 (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and/or its separate modules. It should be noted that the controller can be local to the cluster architecture, or can be located external to the cluster architecture in the manufacturing floor, or in a remote location and connected to the cluster architecture via a network. The system controller 1650 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and/or digital input/output connections, stepper motor controller boards, and other like components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored on the memory devices associated with the controller or they may be provided over a network. In certain embodiments, the system controller executes system control software.

[0180] The system control software may include instructions for controlling the timing of application and/or magnitude of any aspect of tool or module operation. System control software may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operations of the process tool components necessary to carry out various process tool processes. System control software may be coded in any suitable compute readable programming language. In some embodiments, system control software includes input/output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of a semiconductor fabrication process may include one or more instructions for execution by the system controller. The instructions for setting process conditions for condensation, deposition, evaporation, patterning and/or etching phase may be included in a corresponding recipe phase, for example.

[0181] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus may include a processing chamber for patterning, deposition and etch, and a controller including instructions for forming a negative pattern mask. The instructions may include code for, in the processing chamber, patterning a feature in a chemically amplified (CAR) resist on a semiconductor substrate by EUV exposure to expose a surface of the substrate, dry developing the photopattemed resist, and etching the underlying layer or layer stack using the patterned resist as a mask. [0182] It should be noted that the computer controlling the wafer movement can be local to the cluster architecture, or can be located external to the cluster architecture in the manufacturing floor, or in a remote location and connected to the cluster architecture via a network. A controller as described above with respect to any of Figs. 13, 14 or 15 may be implemented with the tool in Figure 16.

Conclusion

[0183] Process and apparatus for dry chamber clean of metal and/or metal oxide photoresists, for example to remove EUV resist material from internal surfaces of process chambers in the context of EUV patterning is disclosed.

[0184] It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art. Although various details have been omitted for clarity’s sake, various design alternatives may be implemented. Therefore, the present examples are to be considered as illustrative and not restrictive, and the disclosure is not to be limited to the details given herein, but may be modified within the scope of the disclosure.