Title:
DUAL-GATE MOSFET STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2019/205537
Kind Code:
A1
Abstract:
A dual-gate MOSFET structure, comprising: a channel region having a gradually changing thickness. A source region is provided at the side of the channel region having a small thickness, and a drain region is provided at the side of the channel region having a large thickness. A source is provided at the side edge of the source region distant from the channel region. A drain is provided at the side of the drain region distant from the channel region. The upper and lower surfaces of the channel region, the source region, and the drain region that are connected to one another are covered with a first gate oxide layer and a second gate oxide layer, respectively. The upper surface of the portion of the first gate oxide layer covering the channel region is provided with a first gate, the lower surface of the portion of the second gate oxide layer covering the channel region is provided with a second gate, and the first gate and the second gate form a dual-gate structure. The device structure provided by the present invention can effectively suppress the short-channel effect, and can also improve the current driving capability and reduce the electric field peak of the drain region. Moreover, the process is relatively simple in steps and can be compatible with an existing CMOS process.
Inventors:
GUO YUFENG (CN)
ZHANG MAOLIN (CN)
TONG YI (CN)
CHEN JING (CN)
LI MAN (CN)
ZHANG MAOLIN (CN)
TONG YI (CN)
CHEN JING (CN)
LI MAN (CN)
Application Number:
PCT/CN2018/111908
Publication Date:
October 31, 2019
Filing Date:
October 25, 2018
Export Citation:
Assignee:
UNIV NANJING POSTS & TELECOMMUNICATIONS (CN)
International Classes:
H01L29/78
Foreign References:
| JP2008192819A | 2008-08-21 | |||
| KR20120066150A | 2012-06-22 | |||
| US20130001589A1 | 2013-01-03 | |||
| CN101501861A | 2009-08-05 |
Attorney, Agent or Firm:
NANJING SUKE PATENT AGENT LIMITED LIABILITY COMPANY (CN)
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