Technical background Recent publications have demonstrated the ever- increasing importance of RF CMOS circuits because CMOS technology offers the big advantage of cheap processing and system-on-chip together with digital building blocks.

However new circuit techniques are needed to fully implement the high frequency operation. One of the major building blocks of an RF transceiver is a PLL-type frequency synthesizer, as shown in Fig. 1 of the appended drawing. In the frequency synthesizer, it is desired to have a frequency divider, which divides by N, where N is programmable. However, such a programmable divider is unable to operate at the very high operating frequency of the RF system. Hence, the frequency synthesizer further comprises a prescaler, which is shown in more detail in Fig. 2. The prescaler is operable at the full high frequency range of the PLL-type frequency synthesizer.

The prescaler is of a dual-modulus type and divides output frequency of the voltage controlled oscillator (VCO) by a certain ratio to a low-frequency signal. The prescaler operates at different divide ratios, for example 32 or 33, which is controlled by the modulus control signal in the frequency synthesizer. The high- speed dual-modulus characteristic is favorable compared to a fixed-division-ratio frequency divider though makes the prescaler much more difficult to design.

A traditional high-speed dual-modulus prescaler generally consists of a synchronous divide-by 4/5 counter and an asynchronous divide-by-8 counter as shown in Figure 2. The divide-by 32/33 function is selected through a modulus-selection input M. With this input at logic zero the synchronous counter does divide-by-4 only, and the prescaler functions as a divide-by-32 counter.

For the divide-by-33, the synchronous counter does divide-by-4 until all the flip-flops in the asynchronous counter reset to logic zero. Then the outputs from these flip-flops, together with the modulus-selection input at logic one, generate a signal pulse enabling the synchronous counter to do divide-by-5 only once in a 33- clock cycle. Afterwards the divide-by-4 is resumed. In this architecture, the prescaler speed is limited by the speed of the synchronous counter, implemented using three D-type flip-flops and two NAND gates.

The main problem of the traditional topology is related to power consumption. The divide-by 4/5 synchronous counter uses three D-type flip-flops and two NAND gates. These three DFFs all operate at the highest frequency, and consequently consume a lot of power.

Additionally, the feedback using the NAND gates greatly limit the maximum speed.

A minor modification in order to reduce the power consumption is to change the divide-by 4/5 synchronous counter with a divide-by-2/3 counter so that only one DFF is clocked by the high-frequency input signal. However, the weakness of this configuration is a lower operation margin compared with the conventional configuration. For example, even though the fixed divide-by-2 counter, which can be used in the divide-by-4/5 synchronous counter, can operate at more than 3GHz the operating frequency can be as low as 1.5GHz, when using the traditional topology solution, mainly due to the above-mentioned feedback.

Summary of the invention The object of this invention is to provide a dual- modulus prescaler having an increased operating speed and a decreased power consumption.

The object is achieved by a dual-modulus prescaler according to the appended claims.

Thus, in one aspect of the present invention there is provided a CMOS prescaler device for frequency dividing a high frequency signal, said device having two operating modes providing two different divisional ratios and comprising: -a first fixed division ratio divider having an input terminal for receiving a high frequency input signal; -a phase differentiator having an input connected to said first fixed division ratio divider for receiving a frequency divided output signal therefrom, said phase differentiator being arranged to generate two phase differentiated output signals having a phase difference of 180 degrees, ; -a phase switch connected to said phase differentiator for receiving said two phase differentiated output signals therefrom and arranged to output one or the other thereof by switching between said phase differentiated output signals ; -a second fixed division ratio divider connected to said phase switch for receiving the output signal thereof, and providing a further frequency divided output signal at an output terminal of the prescaler; and -a phase switch controller connected to the second fixed division ratio divider for receiving the output thereof, said phase switch controller comprising a mode select input, and being connected to the phase switch for controlling said switching between the two phase differentiated output signals.

By providing a fixed division ratio divider at the input of the prescaler, and combining it with circuitry

for shifting between the two modes embodied as the phase differentiator and phase switch a fast device is accomplished. Also, only the fixed division ration divider operates at the full RF frequency, thereby reducing the power consumption.

Further objects and advantages of the present inven- tion will be discussed below by means of exemplary em- bodiments.

Brief description of the drawing Exemplifying embodiments of the invention will be described below with reference to the accompanying drawings, in which: Fig. 1 is a schematic block diagram of a general frequency synthesizer employing a phase locked loop ; Fig. 2 is a schematic circuit diagram of a prior art dual-modulus prescaler; Fig. 3 is a schematic block diagram of an embodiment of the dual-modulus prescaler in acordance with the invention; Fig. 4 is a schematic circuit diagram of the prescaler as shown in Fig. 3; and Fig. 5 is a schematic circuit diagram of a phase shift circuit, which consitutes a part of the prescaler of Fig. 4.

Description of embodiments An embodiment of the prescaler according to the present invention will be described below. However, before that, in order to more fully understand the use of the prescaler according to the invention, the frequency synthesizer of Fig. 1 and the prior art prescaler of Fig.

2 will be described.

A frequency synthesizer of the PLL-type comprises a voltage controlled oscillator (VCO) 11, the output of which is connected to an output buffer 12 as well as to a dual modulus prescaler 13, which i turn is connected to a

programmable divider 14. The programmable divider 14 is connected to a phase detector 15, which in turn is connected to a charge pump 16. The charge pump 16 is connected to a loop filter 17, the output of which finally controls the VCO 11.

As shown in Fig. 2, the divide-by-4/5 synchronous counter of the above discussed prior art prescaler is embodied by three D-type flip-flops (DFFs) 21-23, which are all receiving the full high frequency input, and two NAND gates 24,25 involved in providing a feedback for the first DFF 21. The asynchronous divide-by-8 counter is embodied by three flip-flops 26-28. The outputs from two of these flip-flops 26,27 respectively, together with the modulus-selection input M at logic one, are fed to a NAND gate 29. The output of the third flip-flop 18, together with the output of NAND gate 29, are fed to NAND gate 25 and thereby generate the signal enabling the synchronous counter to do divide-by-5.

As shown in fig. 3 said embodiment of the prescaler comprises a fixed division ratio divider 31, which in this embodiment is a full speed divide-by-two DFF 41, as shown in Fig. 4, and which comprises the input terminal of the prescaler, a half-speed phase differentiator 32 connected to the full speed DFF, and compsrising a buffer 42 and an inverter 43, a phase switch 33 connected to the phase differentiator 32, and comprising three AND-gates 44-46, and a chain of five pure divide-by-two circuits 411-415, four of which 411-414 embodies a second fixed division ratio divider 34 implemented as a divide-by-16 counter, while the fifth thereof 415 is a part of a switch controller 35, which further comprises a NAND-gate 416 having the output connected to the clock input of said fifth divide-by-two circuit 415. The divide-by-16 counter is connected to the phase switch 33 and comprises an output terminal of the prescaler. The switch controller 35 is connected to said output terminal and to a control input of the phase switch 33. The switch

controller 35 comprises a mode control input M, which constitutes one of two inputs of an enable signal generator, the output of which is connected to the divide-by-two circuit. Here said NAND gate 416 is chosen for the enable signal generator, generating an enable signal for the divide-by-two circuit.

The prescaler operates as follows. The single ended input signal IN is fed to the full-speed divide-by-two flip-flop 41. The buffer 42 and inverter 43 of the phase differentiator 32 are used to generate two half-speed signals with a phase difference of 180 degrees, which signals are provided to the phase switch 33 on a respective input thereto. When the mode control input M is low, the low speed DFF 415 is disabled, thus the phase switch control signal will be constant. The switch simply connects one of the two inputs to the divide-by-16 counter 34. The resulting divide-ratio of the prescaler is 2x16=32. The divide-by-33 operation is enabled by setting M high. The divide-by-2 low speed DFF 415 is now working. On every positive edge of the OUT signal, the output of the DFF 415 will flip from zero to one, or one to zero. Thus the input of the divide-by-16 asynchronous divider 34 is switched between the two different signals with 180 degree phase shift each time. The signal is thus delayed by 180 degrees once OUT has one positive edge. So the output period is increased with this delay which equals one input signal IN period. The overall prescaler division ratio now is 32+1=33.

In the prescaler according to this invention, the D- type flip-flop can be implemented by any high-speed flip- flop circuit. The phase switch 33 together with the phase differentiator 32 is also shown in Fig. 5, though in a slightly modified realisation, which however performs the same operation. Three NAND-gates 54-56 are substituted for the. AND-gates 44-46 described above. Further an inverter 53 connected between an input of NAND-gate 54 and an input of NAND-gate 55 and receiving a signal C, is

representative for an operation that is actually performed by the fifth DFF 415, which generates, in the implementation of Fig. 4, two output signals, one thereof being C and the other being C inverted. The alternating selection of the two different signals (180 degree shift) is done by control signal C, generated by the switch controller. Note that the input signal is buffered and inverted by two inverters 51,52. Two extra DFFs 47,48 (see Fig. 4), which are clocked by the VCO output, are used to synchronize C with FIN2. However, the power consumption of these two DFFs is negligible since their states are changed once every 32 periods of FIN2.

Both the traditional prescalers and the prescaler according to this invention have been implemented in a standard 0.35um CMOS process. The final specifications that we get from detailed simulations for the prior art prescaler of Fig. 2 and for the above-described embodiment are shown in Table 1.

Table 1: Performance Comparison Traditional New architecture topology Highest operating 1.7GHz 3. OGHz frequency Supply Voltage 2.7V 2. 7V Current 1. 5mA at 1.7GHz 1. 5mA at 3. OGHz consumption Input Amplitude 1. 6Vpp 600mVpp As seen in table 1 the inventive prescaler has the following merits in comparison with the traditional approach. The circuit operates at a much higher frequency. The speed improvement is more than 60%. The input power of the signal can be much lower, which means that the output power of the VCO in the PLL can be lower and thus saving the total power consumption of the PLL system. Operating at the same frequency, the new prescaler consumes lower power than the traditional counterpart.

Above a preferred embodiment of the method according to the present invention has been described. This should be seen as merely a non-limiting example. Many modifica- tions will be possible within the scope of the invention as defined by the claims.