Title:
DUAL-PATH CLOCK GENERATION CIRCUIT AND METHOD, AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/284116
Kind Code:
A1
Abstract:
The present disclosure relates to the technical field of integrated circuits. Provided are a dual-path clock generation circuit and method, and an electronic device. The dual-path clock generation circuit comprises: a first inverting module, which is configured to access a first signal and output a first clock output signal; a second inverting module, which is configured to access a second signal and output a second clock output signal, wherein the first signal and the second signal are clock signals, which are inverse to each other; a first feedforward buffer, which is arranged between an input end of the first inverting module and an output end of the second inverting module, and which is configured to transmit the first signal, so as to compensate for the second clock output signal; and a second feedforward buffer, which is arranged between an input end of the second inverting module and an output end of the first inverting module, and which is configured to transmit the second signal, so as to delay the first clock output signal.
Inventors:
GU YINCHUAN (CN)
Application Number:
PCT/CN2021/120130
Publication Date:
January 19, 2023
Filing Date:
September 24, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H03M1/06; H03K5/151
Domestic Patent References:
| WO2016199522A1 | 2016-12-15 |
Foreign References:
| JPH0851347A | 1996-02-20 | |||
| US20070247205A1 | 2007-10-25 |
Attorney, Agent or Firm:
BOXIN CHINA INTELLECTUAL PROPERTY (CN)
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