Title:
DUAL PROCESS SEMICONDUCTOR HETEROSTRUCTURES AND METHODS
Document Type and Number:
WIPO Patent Application WO2000063961
Kind Code:
B1
Abstract:
A method for forming an epitaxial layer (4) involves depositing a buffer layer (2) on a substrate (1) by a first deposition process, followed by deposition of an epitaxial layer (4) by a second deposition process. By using such a dual process, the first and second deposition processes can be optimized, with respect to performance, growth rate, and cost, for different materials of each layer. A semiconductor heterostructure prepared by a dual deposition process includes a buffer layer (2) formed on a substrate by MOCVD, and an epitaxial layer (4) formed on the buffer layer (2), the eptitaxial layer deposited by hydride vapor-phase deposition.
Inventors:
SOLOMON GLENN S
MILLER DAVID J
UEDA TETSUZO
MILLER DAVID J
UEDA TETSUZO
Application Number:
PCT/US2000/009999
Publication Date:
February 15, 2001
Filing Date:
April 13, 2000
Export Citation:
Assignee:
CBL TECHNOLOGIES INC (US)
MATSUSHITA ELECTRONICS CORP (JP)
MATSUSHITA ELECTRONICS CORP (JP)
International Classes:
H01L21/205; H01L33/12; C30B29/38; H01L33/32; (IPC1-7): H01L21/31
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