The present invention relates to analog to digital converters. More specifically it relates to dual slope analog to digital converters.

Dual slope A/D converters are well known in the art. Most dual slope A/D converters initialize themselves in a manner which does not minimize the switching action which occurs during a conversion. Typically at the start ofthe A/D conversion the input switch is closed and the other two switches open. The opening ofthe ground switch and the closing ofthe input switch at the start ofthe conversion creates a transient conversion accuracy error.

Applicant's invention eliminates this error by initializing the states ofthe switches in a manner which eliminates the transient.

SUMMARY OF THE INVENTION Applicants invention is an improved dual slope A/D converter. The system comprises two operational amplifiers. The first op amp is an integrator and the second is a comparator with hysterisis. The system further incoφorates three switches. The first switch provides the voltage to be measured (V _x ) to the integrating amp when closed. The second switch provides ground to the integrating amp when closed. The third switch shorts the integrating amp when closed.

V _x is converted into a pulse width using the two op amps. Before a conversion begins the circuit is at a "rest" or in an initialized state with the second switch open and the other switches closed. In this condition integrating amp is connected as a voltage follower and the output voltage of integrating amp is equal to the reference voltage. The processor begins a conversion by raising the start pulse input high. The third switch then opens and the integrating amp integrates using the error signal between V _x and the reference voltage toward ground. Before the output of integrating amp reaches ground the start pulse input is lowered again causing switch one to open, switch two to close, and the output pulse signal to switch low. The error signal between ground and the reference voltage causes the integrating amp to integrate upward toward the source voltage.

Because the comparator has hysteresis the integration will continue upward past the voltage reference. Once the output voltage ofthe integrating amplifier exceeds the hysteresis ofthe comparator the output will go high and the conversion is complete. The completion of conversion opens switch two and closes switch one and switch three.

The time for the first integration remains constant for all conversions. The error signal between ground and the reference voltage also remains constant resulting in the integration slope during the second integration to remain constant. The error signal between Vx and the reference voltage however changes with the different voltage to be measured which varies the slope ofthe integration during the first integration time.

Because the slope during the first integration time varies with user input voltages, the output voltage ofthe integration amp will be different at the end ofthe first integration as a function of Vx. This difference in voltage at the end ofthe first integration changes the starting point for the upward integration during the second integration. The output pulse width of the second integration will therefore vary in direct proportion to the V _x .

BRIEF DESCRIPTION OF THE DRAWING Figure 1 is the schematic diagram ofthe preferred embodiment. Figure 2 is the timing diagram for the preferred embodiment. Figure 3 is the truth table for the preferred embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENT

The dual slope A/D of figure 1 comprises an integrating amp 10, comparator 20 with hysteresis, and logic to control the three phases ofthe conversion which are initialization, integration toward ground, and integration toward supply voltage Vcc. Note that the hysteresis of comparator 20 in figure 2 has been exaggerated for clarity. Integrating amp 10 further comprises capacitor 12 and resistor 14. Comparator

20 further comprises resistors 22 and 24. The output of comparator 20 is supplied to Nor gate 26. The output of nor gate 26 is supplied to transistor 28 which provides the output ofthe system.

Before a conversion begins the START pin is held low. If the output ofthe comparator 20 is high then switch 9 is closed and all charge is removed from capacitor

12. In this condition the output of integrating amp 10 is held at the reference voltage Vref. This is the steady state condition ofthe converter which is state number 1 ofthe

truth table shown in figure 3. If the comparator output was low before a conversion began the integrator would be initialized and integrate from state number zero toward Vcc until state number one is achieved. At the start of a conversion the START pin is raised high moving the converter from state number one to state number three which causes integrating amp 10 to integrate toward ground. Integrating amp 10 will continue to integrate toward ground allowing the voltage at the output of integrating amp 10 to drop below the hysteresis of comparator 20 which causes comparator 20 to switch from high to low. The switching of comparator 20 moves the converter from state number three to state number two which allows integrating amp 10 to continue the integration toward ground.

Before integrating amp 10 drops below its output swing range the start pulse needs to be changed again from high to low. This moves the converter from state number two to state number zero which switches the output from high to low and begins integration toward Vcc. It should be noted that the length of time the START pin is held high is called Tl . The length of Tl is determined by the user and is typically selected to be a multiple ofthe line frequency such as 1/60 Hz = 16.666 msec.

Integration will continue toward Vcc until the integration amp 10 output exceeds the hysteresis of comparator 20 at a voltage above the reference voltage Vref which causes comparator 20 to change from low to high. The conversion then moves from state number zero to state number one causing the output to change to high and completing the conversion. The length of time the output pin OUT is low is measured by the user and is defined as T2.