Title:
DUTY CYCLE CONTROL BUFFER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/071153
Kind Code:
A3
Abstract:
Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit generally includes a first clock-generation stage comprising first cascode-connected transistors the first cascode-connected transistors having gates coupled to a first input clock node. The multi-stage clock generation circuit may also include a second clock-generation stage comprising second cascode-connected transistors, the second cascode-connected transistors having gates coupled to a second input clock node. A first transistor may be coupled to the second cascode-connected transistors, the first transistor having a gate coupled to drains of the first cascode-connected transistors.
Inventors:
PAUL ANIMESH (US)
CHEN XINHUA (US)
CHEN XINHUA (US)
Application Number:
PCT/US2017/052739
Publication Date:
May 31, 2018
Filing Date:
September 21, 2017
Export Citation:
Assignee:
QUALCOMM INC (US)
International Classes:
H03K5/156; H03K5/00
Foreign References:
| US5235219A | 1993-08-10 | |||
| US20070285144A1 | 2007-12-13 | |||
| GB2314473A | 1997-12-24 | |||
| US20130169330A1 | 2013-07-04 | |||
| US20100109725A1 | 2010-05-06 | |||
| US20140125390A1 | 2014-05-08 |
Attorney, Agent or Firm:
ROBERTS, Steven E. et al. (US)
Download PDF: