Title:
DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL, DRAM DEVICE AND STORAGE METHOD
Document Type and Number:
WIPO Patent Application WO/2019/110015
Kind Code:
A1
Abstract:
A DRAM cell includes a transistor, a first diode and a second diode. The transistor has a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder. The bit line is coupled to a power supply voltage. An anode and a cathode of the first diode are coupled to a cathode and an anode of the second diode, respectively. Each of the first diode and the second diode is coupled at a first end to a source of the transistor at a first node, and at a second end to a node voltage at the second node. A DRAM device includes an address decoder and DRAM cells. A storage method for a DRAM device includes writing data into the DRAM cells and reading data from the DRAM cells.
Inventors:
HUNG KEI KANG (CN)
XU QI-AN (CN)
XU QI-AN (CN)
Application Number:
PCT/CN2018/119917
Publication Date:
June 13, 2019
Filing Date:
December 07, 2018
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/401
Foreign References:
| CN108053854A | 2018-05-18 | |||
| US6944051B1 | 2005-09-13 | |||
| US6005801A | 1999-12-21 | |||
| US20070195626A1 | 2007-08-23 | |||
| JPH06326272A | 1994-11-25 |
Attorney, Agent or Firm:
SHANGHAI SAVVY INTELLECTUAL PROPERTY AGENCY (CN)
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