Title:
DYNAMIC REGISTER WITH IDDQ TESTING CAPABILITY
Document Type and Number:
WIPO Patent Application WO2000029860
Kind Code:
A3
Abstract:
The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.
More Like This:
| JP2002040098 | TESTING DEVICE |
Inventors:
HATAMIAN MEHDI (US)
Application Number:
PCT/US1999/027057
Publication Date:
May 30, 2002
Filing Date:
November 12, 1999
Export Citation:
Assignee:
BROADCOM CORP (US)
HATAMIAN MEHDI (US)
HATAMIAN MEHDI (US)
International Classes:
G01R31/30; G01R31/317; G01R31/3185; H04B3/23; H04B3/32; H04L1/00; H04L1/24; H04L7/02; H04L7/033; H04L25/03; H04L25/06; H04L25/14; H04L25/49; H04L25/497; (IPC1-7): G01R31/30; G01R31/3185
Foreign References:
| US5515302A | 1996-05-07 | |||
| EP0811850A2 | 1997-12-10 | |||
| EP0386804A2 | 1990-09-12 |
Other References:
See also references of EP 1145024A2
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