Title:
DYNAMIC VOLTAGE SCALING SYSTEM
Document Type and Number:
WIPO Patent Application WO2005107428
Kind Code:
A3
Abstract:
Methods and apparatus for implementing a Dynamic Voltage Scaling (DVS) system are presented herein. In one embodiment, an embedded delay checker (EDC) cell is used to measure the actual activity and delay of a critical path within a microprocessor core, which is the basis for dynamically altering the voltage to the core. In another embodiment, a slaved ring oscillator (SRO) cell is placed adjacent to the microprocessor core and is used along with EDC cells to provide redundancy to a DVS system.
Inventors:
HENDERSON ERIC LEE (US)
DROP MICHAEL (US)
KAZI TAUSEEF (US)
DROP MICHAEL (US)
KAZI TAUSEEF (US)
Application Number:
PCT/US2005/016095
Publication Date:
April 13, 2006
Filing Date:
May 05, 2005
Export Citation:
Assignee:
QUALCOMM INC (US)
HENDERSON ERIC LEE (US)
DROP MICHAEL (US)
KAZI TAUSEEF (US)
HENDERSON ERIC LEE (US)
DROP MICHAEL (US)
KAZI TAUSEEF (US)
International Classes:
G06F1/32; H04L7/00; (IPC1-7): G06F1/32
Foreign References:
| US6157247A | 2000-12-05 | |||
| US6601177B1 | 2003-07-29 | |||
| US20040049703A1 | 2004-03-11 |
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