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Title:
E-TSPC STRUCTURE-BASED LOW-POWER-CONSUMPTION 2/3 FREQUENCY DIVIDER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/084217
Kind Code:
A1
Abstract:
An E-TSPC structure-based low-power-consumption 2/3 frequency divider circuit comprises a first-stage D trigger DFF1, a second-stage D trigger DFF2, and an inter-stage embedded gate circuit. A clock signal Clk serves as a clock signal to be subjected to frequency division, a positive clock signal Q and a negative clock signal QN serve as clock signals after the frequency division. A 2-frequency-division mode or a 3-frequency-division mode is selected by means of a mode control signal Mc: when the mode control signal Mc is at a low level, the frequency divider circuit works at the 3-frequency-division mode, and when the mode control signal input end Mc is at a high level, the frequency divider circuit works at the 2-frequency-division mode. Compared with a conventional frequency divider having a TSPC structure, the frequency division circuit has a higher working efficiency; and compared with a conventional 2/3 frequency division circuit having an E-TSPC structure, the frequency division circuit has lower power consumption, so that a very-low-power consumption 2/3 frequency division circuit capable of working at a gigahertz frequency is achieved.

Inventors:
WU, Jianhui (No.2 Sipailou, XuanwuNanjing, Jiangsu 6, 210096, CN)
CHEN, Huaihao (No.2 Sipailou, XuanwuNanjing, Jiangsu 6, 210096, CN)
CHEN, Chao (No.2 Sipailou, XuanwuNanjing, Jiangsu 6, 210096, CN)
LI, Hong (No.2 Sipailou, XuanwuNanjing, Jiangsu 6, 210096, CN)
HUANG, Cheng (No.2 Sipailou, XuanwuNanjing, Jiangsu 6, 210096, CN)
ZHANG, Meng (No.2 Sipailou, XuanwuNanjing, Jiangsu 6, 210096, CN)
Application Number:
CN2016/073910
Publication Date:
May 26, 2017
Filing Date:
February 17, 2016
Export Citation:
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Assignee:
SOUTHEAST UNIVERSITY (No.2 Sipailou, XuanwuNanjing, Jiangsu 6, 210096, CN)
International Classes:
H03K23/00
Foreign References:
CN102497201A2012-06-13
CN102916695A2013-02-06
US7248665B22007-07-24
US20110254605A12011-10-20
Other References:
YU , XIAOPENG ET AL.: "Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler", IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 54, no. 11, 30 November 2006 (2006-11-30), XP055383080
KRISSHNA, M.V. ET AL.: "Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEM-I, vol. 57, no. 1, 31 January 2010 (2010-01-31), XP011333592
ZHU, KAI ET AL.: "6 GHz 831 µA Divide by 10/11 Prescaler", ELECTRONIC MEASUREMENT TECHNOLOGY, vol. 32, no. 2, 28 February 2009 (2009-02-28)
Attorney, Agent or Firm:
JIANGSU AIXIN LAW FIRM (18th Fl.-E, Jinyinghanzhongxincheng Building No. 1 Hanzhongmen main streetNanjing, Jiangsu 9, 210029, CN)
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