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Title:
EDGE DETECTING FILTERS
Document Type and Number:
WIPO Patent Application WO/2007/003055
Kind Code:
A2
Abstract:
This invention relates to an edge detecting filter (EDF) for recovering data carrying edges from a noisy received signal by dense over-sampling of the received signal and by detecting edge phases and edge amplitude limits wherein recovered signal amplitudes at sampling instance defining said edge phase are determined by said edge amplitude limits while recovered amplitudes assumed at sampling instances following the last edge detected are those implementing an ideal signal shape determined by the last edge. The EDF comprises a system for adaptive noise filtering which analyzes captured unfiltered portions of the over-sampled waveform in order to compensate predictable and/or random signal distortions and interferencies.

Inventors:
BOGDAN JOHN W (CA)
Application Number:
PCT/CA2006/001101
Publication Date:
January 11, 2007
Filing Date:
July 06, 2006
Export Citation:
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Assignee:
BOGDAN JOHN W (CA)
International Classes:
H03K5/1252; G01R29/02; H04B1/10; H04B15/00; H04L1/00
Foreign References:
US20040066864A1
US20060008040A1
US6999544B2
US20060109942A1
Download PDF:
Claims:
24

CLAIMS

While the invention has been described with reference to particular example embodiments, further modifications and improvements which will occur to those skilled in the art, may be made within the purview of the appended claims, without departing from the scope of the invention in its broader aspect.

Numerous modification and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

What is claimed is:

1. An edge detecting filter (EDF) for recovering data carrying edges from a noisy received signal by dense over-sampling of the received signal and by detecting edge phases and edge amplitude limits wherein recovered signal amplitudes at sampling instance defining said edge phase are determined by said edge amplitude limits while recovered amplitudes assumed at sampling instances following the last edge detected are those implementing an ideal signal shape determined by the last edge; the edge detecting filter comprising: a wave capturing circuit for such over-sampling of the received signal and for capturing a waveform sampled; a wave-form processor estimating correlations between a set of wave-form samples surrounding an analyzed consecutive sample and their counterparts from an edge mask, and for combining such estimates of individual bits correlations into a correlation integral characterizing level of similarity between the surrounding set of samples and the edge mask; the wave-form processor analyzing such correlation integrals in order to decide if there is an edge at the analyzed consecutive sample and to detect edge phase and edge amplitude limits if said edge does occur.

2. An EDF as claimed in claim 1 , wherein the waveform processor comprises: parallel processors for simultaneous calculation of correlation integrals for a multiplicity of waveform samples belonging a captured waveform interval in which said data carrying edge is expected.

25

3. An EDF as claimed in claim 1 using a method and system for synchronous sequential processing (SSP), which multiplies processing speed by splitting complex signal processing operation into a sequence of singular micro-cycles, for implementing the functions of the wave capturing circuit and the waveform processor; wherein the SSP comprises: multiple serially connected sequential stages clocked by reference sub-clocks generated by a reference propagation circuit built with serially connected gates which a reference clock is propagated through, wherein every such serially connected stage is designated to perform a basic logical or arithmetical operation during such consecutive singular micro-cycle of the complex operation; a configuration of parallel processing stages of the received signal, wherein multiple processing stages are driven by the same sub-clock which is applied simultaneously to inputs of output registers of all the parallel stages.

4. An EDF as claimed in claim 1 further including adaptive noise filtering using a programmable control unit (PCU) for an adaptive compensation of the received signal noise by analyzing selected intervals of the captured waveform and by modifying said edge masks and/or by reprogramming functions performed by said waveform processor; the EDF further comprising: a waveform screening and capturing circuit (WFSC) for accessing and buffering of pre-selected intervals of said captured waveform; the programmable control unit for said analysis of noise and/or distortions occurring in said preselected intervals; and for implementing adaptive noise compensation algorithms by said modifications of the edge masks and/or by said reprogramming of the waveform processor.

5. An EDF as claimed in claim 1 further including preliminary filtering of the captured waveform before said correlation estimates and correlation integrals are calculated; the EDF comprising: the wave-form processor filtering the captured wave-form with an amplitude averaging filter; and/or the waveform processor characterizing said consecutive analyzed samples by calculating an amplitude change rate over an area surrounding the consecutive analyzed sample and by assigning such amplitude change rates to the corresponding consecutive analyzed samples.

6. An edge detecting filter (EDF) for recovering data carrying edges from a noisy received signal by dense over-sampling of the received signal and by detecting edge phases and edge amplitude limits wherein recovered signal amplitudes at sampling instance defining said

26 edge phase are determined by said edge amplitude limits while recovered amplitudes assumed at sampling instances following the last edge detected are those implementing an ideal signal shape determined by the last edge; the edge detecting filter comprising: a wave capturing circuit for such over-sampling of the received signal and for capturing a waveform sampled; a wave-form processor estimating correlations between a set of wave-form samples surrounding an analyzed consecutive sample and their counterparts from an edge mask, and for combining such estimates of individual bits correlations into a correlation integral characterizing level of similarity between the surrounding set of samples and the edge mask; the wave-form processor analyzing such correlation integrals in order to decide if there is an edge at the analyzed consecutive sample and to detect edge phase and edge amplitude limits if said edge does occur, wherein said analysis includes finding an extreme of said correlation integrals in a waveform area expected to comprise a valid data carrying edge wherein such sampling instant which has such extreme correlation integral defines the edge phase recovered and the edge mask used defines the edge amplitude limits.

7. An edge detecting filter (EDF) for recovering data carrying edges from a noisy received signal by dense over-sampling of the received signal and by detecting edge phases and edge amplitude limits wherein recovered signal amplitudes at sampling instance defining said edge phase are determined by said edge amplitude limits while recovered amplitudes assumed at sampling instances following the last edge detected are those implementing an ideal signal shape determined by the last edge, wherein correlation integrals, between waveform intervals surrounding analyzed consecutive samples and intervals representing ideal edges applied as edge masks, are used for recovering said edge phases and amplitude limits; the edge detecting filter comprising: a wave capturing circuit for such over-sampling of the received signal and for capturing a waveform sampled; a wave-form processor estimating correlations between a set of wave-form samples surrounding an analyzed consecutive sample and their counterparts from an edge mask, and for combining such estimates of individual bits correlations into said correlation integral characterizing level of similarity between the surrounding set of samples and the edge mask; the wave-form processor defining a waveform transition area by comparing such correlation integrals with an edge threshold defining an edge proximity area, wherein a set of waveform samples, which has said correlation integrals contained within such proximity area, is defined as the waveform transition area;

27 the wave-form processor detecting said edge phase and amplitude limits by finding the most extreme correlation integral in such waveform transition area, wherein such sampling instant which has such most extreme correlation integral defines the edge phase recovered and the edge mask used defines the edge amplitude limits.

8. An edge detecting filter (EDF) for recovering data carrying edges from a noisy received signal by dense over-sampling of the received signal and by detecting edge phases and edge amplitude limits wherein recovered signal amplitudes at sampling instance defining said edge phase are determined by said edge amplitude limits while recovered amplitudes assumed at sampling instances following the last edge detected are those implementing an ideal signal shape determined by the last edge, wherein such EDF includes selection of an edge mask, offering best resemblance to a wave-form interval centered around a closest data carrying edge, from a wide variety of edge masks enabling reception of multilevel PAM signals and/or compensation of incoming signal distortions including line loads or inter- symbol interference; the edge detecting filter comprising: a wave capturing circuit for such over-sampling of the received signal and for capturing a waveform sampled; a wave-form processor performing preliminary analysis of an surrounding of an analyzed consecutive sample which may include preceding and/or following waveform regions, and using such analysis results for selecting said edge mask which is most suitable to detect phase of said data carrying edge anticipated by these results and/or to provide compensation for signal distortions; the wave-form processor estimating correlations between a set of wave-form samples surrounding said analyzed consecutive sample and their counterparts from such selected edge mask, and for combining such estimates of individual bits correlations into said correlation integral characterizing level of similarity between the surrounding set of samples and the edge mask; the wave-form processor defining a waveform transition area by comparing such correlation integrals with an edge threshold defining an edge proximity area, wherein a set of waveform samples, which has said correlation integrals contained within such proximity area, is defined as the waveform transition area; the wave-form processor detecting said edge phase and amplitude limits by finding the most extreme correlation integral in such waveform transition area, wherein such sampling instant which has such most extreme correlation integral defines the edge phase recovered and the edge mask used defines the edge amplitude limits.

28

9. An edge detecting filter (EDF) using time domain processing for recovering phases and amplitude ranges of data carrying edges from a noisy received signal while amplitudes occurring between the recovered edges are assumed to equal those implementing a known ideal signal shape determined by the last edge recovered, instead of spending processing resources on calculating every recovered amplitude and recovering data carrying edges from such incomplete amplitude oriented results deprived already of relevant phase/time related information; the edge detecting filter characterized in that: the received signal is densely over-sampled and resulting over-sampled waveform is captured; said phases and amplitude ranges of data carrying edges are recovered by time domain processing of the over-sampled waveform; data transmitted is recovered from the phases and amplitude ranges of recovered edges; or an entire signal transmitted originally is recovered by defining it's amplitudes as equal to those defined by said amplitude ranges at sampling instances defining said edges phrses, and by defining it's amplitudes as equal to those implementing known ideal signal shape determined by the last recovered edge at sampling instances located between the last and next edges.

10. An edge detecting filter (EDF) for recovering data carrying edges from a noisy received signal by dense over-sampling of the received signal and by detecting edge phases and edge amplitude limits wherein recovered signal amplitudes at sampling instance defining said edge phase are determined by said edge amplitude limits while recovered amplitudes assumed at sampling instances following the last edge detected are those implementing an ideal signal shape determined by the last edge; the edge detecting filter comprising: a wave capturing circuit for such over-sampling of the received signal and for capturing a waveform sampled; a wave-form processor for estimating mutual correlations between wave-form samples belonging to a waveform region surrounding an analyzed consecutive sample, and for combining such estimates of mutual bits correlations into an amplitude change rate characterizing level of similarity between the surrounding set of samples and an edge mask characterized by an amplitude change factor; an edge detecting circuit for detecting said edge phase and amplitude limits by analyzing such amplitude change rates and such amplitude change factors.

Description:

Edge Detecting Filters

BACKGROUND OF THE INVENTION

1. Field of the invention

This invention is directed to providing low co3t high resolution edge detecting filters (EDF) for precise recovering of wave-form edges from noisy signals.

This invention defines digital means for programmable noise filtering from over sampled waveforms consisting of variable lengths pulse3 carrying data ratc3 ranging to 1 /2 of teehnology'3 maximum clock frequency.

The edge detecting filters are directed to signal and data recovery in wireless, optical , or wireline transmission systems and measurement 3y3tem3.

The EDF3 shall be particularly advantageous in system on chip (SOC) implementations of signal processing 3ystem3.

This invention is directed to noise filters for serial data link receivers including all receivers for copper/optical/wireless links for local and remote data transmissions.

More particularly, this invention provides low cost high resolution edge detecting noise filters (EDF) for precise recovery of wave-form edges from noisy signals.

This invention comprises systems and methods for programmable noise filtering from over- sampled wave-forms, carrying variable lengths data encoding pulses, which transfer data rates ranging up to 1 /2 of technology's maximum clock frequency.

The EDFs shall be particularly advantageous in system on chip (SOC) implementations of signal processing systems.

2. Background art

Prior art U3es frequency domain filters for recovering data from serially transmitted pulses. Since serially transmitted pul3C3 must have widely variable lengths and frequencies, 3uch frequency domain filters can not eliminate high frequency phase jitter and attenuate useful part of signal while filtering high frequency noise.

Thi3 CDF invention eliminates both deficiencies mentioned above, as it is further explained uCIO'W.

Previous art noise filters calculate all output signal amplitudes corresponding to all digital sampling (or analog sensing^ instances of input signals, in order to produce filtered output signals.

Since prior art filters spent their signal sampling (or sensing^) resources and signal processing resources on calculating all reconstructed signal amplitudes, prior art filters for serial links shall be named as amplitude noise filters.

Such amplitude filtering approach originated from AM domination in early communication era. It was appropriate one for data transmissions methods which use signal amplitudes as the main means for encoding transmitted data.

However: contemporary communication methods are based on FM. PM. or NRZ/PAM over copper/fiber which use signal transitions between limited set of discrete levels and transitions phases as the means for data encoding.

All digitally transmitted data can be recovered entirely when such signal transmitting transitions and their phases are known. Since all original signal amplitudes between two transitions shall be expected to be equal to the final level reached bv the last transition, there is no need to calculate filtered signal amplitude for every time instance occurring between transitions- While prior art frequency domain signal processing is insufficient for identifying phase transients- prior art time domain signal processing requires by one order higher sampling rates and by several orders greater processing resources which cause it to be unaffordable for high speed data links.

Furthermore, prior art uses frequency domain filters for recovering data from serially transmitted pulses. Since serially transmitted pulses must have widely variable lengths and frequencies, such frequency domain filters have to attenuate significant useful part of such signal in order to eliminate high frequency phase jitter and high frequency amplitude glitches from such data carrying signal.

The above limitations of prior art amplitude noise filters are alleviated by this invention's edge detecting noise filters (EDF); which use new time domain methods focused entirely on improving recovery of signal transients relevant to transmitted data, while avoiding said spending resources on calculations of predictable intermediate amplitudes.

SUMMARY OF THE INVENTION

i ' his invention eliminates said fundamental contradiction of using amplitude noise filters for recovering phase modulations being the main data carrier, by using phase noise filters (named EDF) instead. Therefore this invention enables inexpensive SOC implementations of serial data link receivers multiplying distances and/or data rates on copper/optical/wireless links for local and remote data transmissions.

Such phase noise filters focus on recovery of input signal phase which is defined by the timing of signal waveform transitions. A typical EDF keeps testing consecutive waveform samples: by verifying if there is a waveform transition, having sufficient steepness and sufficient amplitude span, in a waveform region surrounding a particular tested waveform sample. Insufficient waveform fluctuations are discarded by assigning recovered signal amplitude as being equal to the final amplitude reached by the last previously detected transition. However if such waveform transition is detected: sampling time instance of the tested sample defines recovered phase of the signal, and recovered signal amplitude is adjusted to the final amplitude reached by that transition.

Consequently this invention comprises edge detecting noise filter TEDF) and edge noise filtering method (EFM). characterized below. The edge noise filtering method (EFM) performs processing of a set of adjacent samples surrounding a currently tested sampling time instant, in order to detect if a filtered signal transition actually occurs at the currently tested sampling instant and to define a final level of such signal transition. If such transition did occur, filtered signal phase is defined as equal to the tested time instant and filtered signal amplitude at the tested time instant is made compliant to said final level. If such transition did not occur, the amplitude of filtered signal for the newly tested instant is made compliant to the amplitude assumed for the previous tested instant: After such edge occurrence testing for the current time instant, the EFM applies the same testing routine to the next sampling instant-

edge phases (measured in time delays between edges ' ) and edge spans (defined with limiting them original and final amplitudes), comprise all the information needed to recover data encoded

within said contemporary FM. PM. or NRZ/PAM communication systems.

Said EFM's processing of adjacent samples further comprises: « calculating amplitude differences between said adjacent samples, and estimating if a transition is occurring at the tested sampling instant: •_ or calculating a correlation integral between samples belonging to said set of adjacent samples and their counterparts belonging to an edge mask comprising a set of nominal values for said adjacent samples expected if transition is occurring at the tested sample, and estimating if said transition is occurring at the tested sampling instant: •_ if such transition does occur, calculating and/or defining said time delay between the preceding transition and the present transition (inter-edge pulse length * ) and calculating and/or defining said final amplitude of said present transition: « digitization of said inter-edge pulse length fin order to determine number of symbol intervals comprised in such inter-edge pulse * ), and digitization of inter-edge amplitude (in order to identify data symbols encoded in said symbol intervals).

Furthermore this invention comprises instant and comprehensive compensation of incoming signal distortions (including those caused by line loads or inter-symbol interference), by combining: ultra fast front end processing of oversampled waveforms implemented with a synchronous sequential processor (SSP). with a programmable background processing implemented with a programmable control unit (PCU).

This invention's SSP multiplies processing speed by splitting complex signal processing operation into a sequence of singular processing micro-cycles performed between re-loadings of incoming oversampled data into consecutive SSP registers working as first in first out configuration.

Such SSP based front end performs processing of incoming said surrounding regions and corresponding to them edge masks, wherein edge mask selection circuits enable selections of different masks (preprogrammed by PCU) dependent on waveform levels sampled before and after the tested sampling instant.

In addition to said preprogramming of the edge masks: PCU controls SSP operations by preloading SSP control registers with appropriate control data.

This invention includes a waveform screening and capturing circuit (WFSC) for capturing preselected intervals of incoming oversampled waveform.

This invention includes using PCU: for analyzing noise and distortions occurring in said preselected intervals, for selecting adaptive noise compensation algorithms, and for implementing such algorithms bv said ore-programming of said edge masks and said SSP control

registers.

This invention includes ability: «__ to anticipate hundreds of instantly changing uncertainties (such as dozens of possible transitions between PAM levels multiplied by multiple different line loads etcV wherein each such uncertainty would require different edge mask to be used for calculating edge detecting correlation integral: •__ and to use such anticipation for selecting the most suitable mask able to address and/or compensate all such uncertainties, instead of calculating correlation integrals for hundreds of masks needed otherwise.

This invention achieves that by comprising: preliminary analysis of immediate surrounding of the the tested sample including both preceding and following waveform regions: instant use of such analysis results for selecting edge mask which is most suitable to detect phase of the transition anticipated by these results and provides best compensation for signal distortions anticipated by the results (such as line load and/or inter-symbol interference!

Consequently this invention enables inexpensive SOC receivers for serial data links comprising: digital filtering of waveform pulses transmitting serial streams of data symbols with data rates reaching '/2 of maximum clock frequency of IC technology: continues waveform over-sampling with sampling frequencies several times higher than the maximum clock frequency, and elimination of phase jitter from edges of the pulses and amplitude glitches from insides of the puises wherein such removal eliminates prior art band limiting low-pass filter attenuating received signal by two times: adaptive noise filtering utilizing analysis of captured unfiltered portions of the over-sampled waveform, in order to provide conclusively better compensation of serial link signal distortions: bv one order (~1 Ox) more accurate detection of data encoding phases of serial link signals.

GENERAL DESCRIPTION OF THE INVENTION

The EDF enables comprises:

continues waveform over-sampling with sampling frequencies >10 times higher than the maximum frequency of data carrying serial pulses; elimination of phase jitter from edges of the pulses and elimination of amplitude glitches from insides of the pulses as well; and a system for adaptive noise filtering based on analysis of captured unfiltered portions of the over-sampled waveform.

The EDF invention provides an implementation of programmable algorithms for noise filtering for a very wide range of low and high frequency wave-forms. The EDF enables >10 times faster sampling and processing than prior art digital filters.

The EDF configuration uses: a synchronous sequential processor (SSP) for capturing and real time processing of an incoming waveform (see the end of this section); a wave-from screening & capturing circuit (WFSC) (see the end of this section); a programmable control unit (PCU) for supporting adaptive noise filtering and edge detection algorithms.

The EDF produces a correlation integral, between a captured set of binary values surrounding a particular bit of a captured waveform and an edge mask comprising a programmed set of binary values. Such correlation integral serves as an indicator of proximity between the surrounded bit and an expected edge of the waveform. Therefore the correlation integral is also named edge proximity figure (EPF). Such EPFs are further used to define edge timing.

Producing the correlation integral and defining edge timing comprise: performing logical and/or arithmetic operation on any bit of the captured set and its counterpart from the edge mask; integrating results of said operations performed on all the bits of the captured set, in order to estimate the EPF for the surrounded bit; defining a waveform transition area by comparing the EPF with an edge threshold, wherein a set of bits having EPFs exceeding located outside a stable amplitude area, excluded by the threshold, defines the waveform transition area where an edge is expected.

Finding the most extreme EPF by comparing all the EPFs belonging to the same waveform transition area, wherein such EPF identifies a bit position localizing a filtered edge.

The EDF further comprises:

modulating locations of detected rising and/or falling waveform edges by an edge modulating factor (EMF) used to modify edge thresholds which are subtracted from the EPFs, wherein such reduced EPFs are used for finding edge location; using an edge modulation control register (EMCR) programmed by the PCU, for defining function transforming said EMFs into said modifications of edge thresholds.

The EDF still further comprises displacing detected edges by a preset number of bits, in order to compensate for inter-symbol interference ISI or other duty cycle distortions.

The EDF invention further includes: using the WFSC for programmable screening of the over-sampled unfiltered wave-form, and for capturing screened out wave-form intervals, and for communicating said captured intervals and other results to the PCU; programmable waveform analysis and adaptive noise filtering algorithms; edge mask registers for providing said edge masks used for detecting rising and/or falling waveform edges; edge threshold registers for providing said edge thresholds used for detecting rising and/or falling waveform edges; edge displacement registers for providing said edge displacement numbers used for shifting detected rising and/or falling edges by a programmable number of bits of waveform processing registers; filter control registers which control; said logical and/or arithmetic operations conducting the comparison of captured waveform bits with the edge mask, and said edge displacements in the processed waveforms; using the PCU for calculating and loading said edge mask registers and/or said edge threshold registers and/or said edge displacement registers and/or said filter control registers; using the PCU for controlling said calculations of the EMF by presetting the EMCR in accordance with adaptive noise filtering algorithms, using the PCU for controlling and using the WFSC operations for implementing adaptive filters by controlling noise filtering edge detection stages of the SSP.

More complete definition of the EDF invention is provided below.

The EDF invention comprises:

a wave capturing circuit for capturing an incoming wave-form sampled by sub-clocks produced by the outputs of the delay line which the sampling clock is propagated through; a circuit performing logical or arithmetic operations on particular samples of the edge mask and their counterparts from the wave-form samples surrounding the consecutive analyzed sample of the captured wave-form; using the results of said operations for defining a filtered location of an edge of the waveform. Such EDF further comprises: a filter arithmometer for comparing the edge mask with the captured wave-form in order to introduce noise filtering corrections of the edges of the filtered wave-form; a filter mask register providing the edge mask which is compared with the captured wave-form of an input signal and/or filter control register which provides code for controlling operations of said filter arithmometer in order to provide said corrections of the filtered wave- form.

The EDF compares said edge mask samples of the expected edge pattern with samples from a consecutive processed region of the captured wave-form. Consequently the EDF comprises: accessing any said consecutive processed region of the captured wave-form and using such region as comprising samples corresponding to the edge mask samples; selection of a consecutive sample from the edge mask and simultaneous selection of a corresponding consecutive sample from the processed region of the captured wave-form; calculating a correlation component between such selected samples by performing an arithmetical or logical operation on said selected samples; calculating a digital correlation integral by adding said correlation components calculated for single samples of the edge mask.

The EDF includes calculating correlation integrals for said consecutive processed regions uniformly spread over all the captured wave-form, wherein the calculated correlation integrals are further analyzed and locations of their maximums or minimums are used to produce said filtered locations of said edges of the filtered wave-form;

Such EDF operations comprise: moving said processed region by a programmable number of samples positions of the captured wave-form; storing and comparison of said correlation integrals calculated for different processed regions, in order to identify said maximums or minimums and their locations;

using said locations of said maximums or minimums for producing the filtered locations of the edges of the filtered wave- from.

In addition to the off-line analysis of unfiltered samples, collected by the WFSC, and adaptive filtering provided by the PCU; the EDF offers unique ability to analyze currently incoming waveform and to provide instant predictive compensation to presently appearing combinations of noise with line-load and other factors. Such EDF utilizes plurality of different edge masks providing wide variety of compensations responding to past, present and future wave-form conditions. Such predictive EDF further comprises: a means circuit for continuos time domain analysis of a rate of amplitude change of the over- sampled waveform; a means circuit for producing quantitative estimates of the change rates; a means circuit for using said rates estimates for identifying transition areas of the waveform wherein said transition areas define time intervals when pulse amplitude is switching between different levels; a mean 3 circuit for using such rate estimate for instant selection of this one of multiple edge masks which is most effective in filtering out noise from the transition area characterized by the rate estimate.

The predictive EDF further includes stabilizing said predictive response by using a pre-filtered waveform, improving noise immunity, for producing said rates estimates; wherein the EDF comprises: using averaging filters to produce the pre-filtered waveform, which is used for the analysis producing said rates estimates; identifying transition areas by comparing rates estimates with a threshold of transition area

(TTA); defining the transition areas as time intervals where said rate estimates exceed +/- TTA range; selecting the most extreme value of the rate estimates occurring in the transition area and using the such extreme value for choosing one of the edge masks; identifying an initial or final pulse amplitude for the present transition area and using it as additional factor in choosing the edge mask; and/or identifying pulse amplitudes surrounding past and/or future transition areas and using them as additional factors in choosing the edge mask;

and/or selecting the most extreme value of the rate estimates occurring in the past and future transition areas and using the selected values as additional factors in choosing the edge mask. using an address encoder for edge masks memory (AEEMM) for transforming a set of the mask choosing factors, mentioned above, into an effective mask address.

The EDF further comprises using the PCU and the WFSC for slower off-line adaptive programming of the masks memory with most effective set of edge masks.

The EDF invention still further comprises parallel processing of correlated edges of over- sampled signal (PPCE) which continuously over-samples an incoming signal by capturing samples occurring in time instances defined by outputs of a delay line of a sampling clock, performs parallel calculations of correlation integrals for multiple consecutive time instances by integrating deviations between a set of said captured samples surrounding any such time instance and a set of samples expected at an edge occurrence defined by an edge mask, defines waveform transition area as time interval having said correlation integrals greater than an edge threshold, and identifies positioning of a filtered edge as equal to a position of most extreme correlation integral in the transition area; wherein the PPCE comprises: parallel correlation integral processors (ClPs) for producing said correlation integrals, wherein one said PCA dedicated to one said time instance produces correlation integral relating to that time instance by integrating all said deviations between the captured set of samples surrounding that time instance and the expected set defined by the edge mask wherein any such deviation is calculated as an estimate of a difference between a sample from said surrounding area and a corresponding element from the edge mask; parallel threshold comparators (PTCs) for comparing said correlation integrals with preprogrammed edge thresholds and for defining transition area as containing correlation integrals exceeding said thresholds; an extreme value selector (EVS) for finding most extreme value of correlation integral within the transition area, wherein a time instance having the most extreme correlation integral defines position of a filtered edge of the waveform; a pulse lengths processor (PLP) for defining precise lengths of pulses representing constant amplitude of a filtered signal based on timing of the detected edges, and for extracting data

transmitted by the signal or for analysis of other signal properties by processing said lengths of the pulses; whereby by using multiple said CIPs for producing multiple correlation integrals relating to said time instances and by using multiple said PTCs and the EVS for said edges detections, locations of filtered signal edges are identified and said edges locations enable the PLP to define the lengths of signal pulses and to perform data extraction or other signal analysis functions.

The EDF includes means a system for correcting pulse lengths distortions caused by variations of transmission line load resulting from varying past levels of transmitted signal wherein estimates of a present line load are produced during said processing of said pulse lengths and such line load estimates are further used for correcting a final pulse lengths; the PPCE further comprising: means a circuit for producing said line load estimate while current pulse lengths is processed following the detection of a leading edge of the pulse; means a circuit for using such line load estimate for correcting positioning of the trailing detected edge of the current pulse in order to compensate said expected pulse length distortion caused by past variations of incoming signal levels.

The EDF further includes a system providing corrections of the current pulse length taking into account an impact of previous pulses lengths on said positioning of the trailing edge of the current pulse in addition to the impact of said current pulse length; the EDF further comprises: means a circuit for accumulating properly weighted said line load estimates of previously processed pulses of the signal; means a circuit for combining such accumulated load estimates with the line estimate produced for the current pulse of the signal; means a circuit for using such combined line load estimate for correcting positioning of the trailing detected edge of the current pulse in order to compensate said expected pulse lengths distortion caused by the past variations of incoming signal levels.

The EDF includes compensation of inter-symbol interference (ISI) or other predictable noise by adding a programmable displacement to said filtered location of the edge of the wave-form. Therefore the EDF comprises:

programmable amendment of the filtered location of the wave-form edge by presetting said programmable displacement with a new content; using such newly preset displacement for shifting the filtered location of the next detected edge.

The EDF includes compensation of periodical predictable noise with programmable modulations of said filtered locations of the wave-form edges by using an edge modulating factor (EMF) for a periodical diversification of said edge thresholds corresponding to different said regions of the wave-form; wherein the EDF comprises: modulation of the filtered locations of the wave-form edges by using the edge modulating factor (EMF) for modulating said edge thresholds; subtracting such modulated thresholds from the correlation integrals calculated in said different wave-form regions; using such reduced correlation integrals for locating said maximums defining locations of filtered edges. whereby said EMF provides such modulation of the edge thresholds, that predictable noise introduced to consecutive wave-form samples by known external or internal sources, is compensated.

The EDF further includes: using an edge modulation control register (EMCR) programmed by the PCU, for said modulation of the edge thresholds.

The EDF comprises: sequential processing stages configured into a sequential synchronous pipeline driven synchronously with said sampling clock. The EDF further comprises parallel processing phases implemented with said synchronous sequential pipelines; wherein: said parallel processing phases are driven by clocks having two or more times lower frequencies than said sampling clock; consecutive parallel phases are driven by clocks which are shifted in time by one or more periods of said sampling clock;

The EDF comprises using multiple noise filtering sequential stages in every parallel processing phase for extending said wave-form filtering beyond a boundary of a single phase.

Such EDF further includes an over-sampled capturing of consecutive wave-form phases in corresponding phases wave registers which are further rewritten to wave buffers with

overlaps which are sufficient for providing all wave samples needed for a uniform filtering of any edge detection despite crossing boundaries of the wave buffers which are loaded and used during different said phases; wherein the EDF comprises: rewriting the entire wave register belonging to one phase into the wave buffer of the same phase and rewriting an end part of said wave register into a front part of the next phase wave buffer, while the remaining part of the next wave buffer is loaded from the wave register belonging to the next phase; whereby every wave buffer contains entire said wave-form regions needed for calculating said

EPF's corresponding to the samples belonging to the phase covered by this buffer.

The EDF includes: merging of said parallel processing phases, wherein multiple said parallel processing phases are merged into a smaller number of parallel phases or into a single processing phase, when passing from one said sequential processing stage to the next sequential stage. splitting of said parallel processing phases, wherein one said processing phase is split into multiple parallel processing phases or multiple parallel processing phases are split into even more parallel phases, when passing from one said sequential processing stage to the next sequential stage.

The EDF includes said PCU for analyzing results of said real time signal processing form the SSP and for controlling operations of the SSP; wherein the PCU comprises: means a circuit and program for reading results of captured signal processing from the SSP; mean3 a circuit and subroutine for programming the filter mask register and/or the filter control register and/or said presetting of the programmable displacement and/or the edge modulating factor, which are applied for achieving said filtering of the captured wave-forms.

The EDF includes a wave-form screening and capturing circuit (WFSC) for capturing preselected intervals of unfiltered over-sampled wave-form; wherein the WFSC comprises: using programmable screening masks and/or programmable control codes for verifying incoming wave-form captures for compliance with said programmable screening masks. buffering captured wave-form for which the pre-programmed compliance or non-compliance has been detected, or for counting a number of said detections; communicating said buffered wave-form and a detections counter to the PCU.

The PCU reads resulting captured signals from the WFSC and controls operations of the WFSC; wherein the PCU comprises: programming the screening masks and/or the control codes for performing said verification of captured wave-forms compliance or non-compliance with said screening patterns; reading verification results and/or reading captured wave-forms which correspond to the preprogrammed verification criteria.

The EDF includes using said PCU for adaptive noise filtering; wherein the PCU comprises: means a subroutine for programmable waveform analysis; means a circuit and subroutine for loading edge mask registers which provide said edge masks used for detecting rising and/or falling wave-form edges; or means a circuit and subroutine for loading edge threshold registers which provide said edge thresholds used for detecting rising and/or falling waveform edges; or means a circuit and subroutine for loading edge displacement registers which provide said edge displacements used for shifting detected rising and/or falling edges by a programmable number of samples positions of the captured wave-form; or means a circuit and subroutine for loading filter control registers which control said logical and/or arithmetic operations conducting the comparison of captured wave-form samples with the edge mask, and said edge displacements in the processed wave-forms; or means a circuit and subroutine for controlling said EMF by presetting the EMCR in accordance with adaptive noise filtering algorithms.

General definition of the SSP is provided below.

The SSP includes real time capturing and processing of in-coming wave-form and a programmable computing unit (PCU) for controlling SSP operations and supporting adaptive signal analysis algorithms.

Said SSP comprises an over-sampling of incoming wave-form level by using a locally generated sampling clock and its sub-clocks generated by the outputs of serially connected gates which the sampling clock is propagated through. If an active edge of the wave-form is detected by capturing a change in a wave-form level, the position of the captured signal change represents an edge skew between the wave-form edge and an edge of the sampling clock.

Every said edge skew amounts to a fraction of a sampling clock period.

The SSP invention comprises measuring time intervals between active wave form edges, as being composed of said edge skew of a front edge of the incoming waveform, an integer number of sampling clock periods between the front edge and an end edge, and said edge skew of the end edge of the wave-form.

The SSP passes incoming signal through multiple serially connected processing stages with every stage being fed by data from the previous stage which are clocked-in by a clock which is synchronous with the referencing clock. Since every consecutive stage is driven by a clock which is synchronous to the same reference clock, all the stages are driven by clocks which are mutually synchronous but may have some constant phase displacements versus each other.

The synchronous sequential processor (SSP) multiplies processing speed by splitting complex signal processing operation into a sequence of singular micro-cycles, wherein: every consecutive micro-cycle of the complex operation is performed by a separate logical or arithmetical processing stage during a corresponding consecutive time slot synchronous with a reference clock providing a fundamental timing for a synthesized said processing of the captured waveform; serially connected sequential stages are connected to a programmable control unit (PCU), wherein the sequential stages are clocked by reference sub-clocks generated by a reference propagation circuit built with serially connected gates which the reference clock is propagated through; whereby inputs from the PCU are programming control registers used for modifying SSP operations, in order to implement adaptive noise filtering algorithms, are processed into a phase delay between a next edge of the synthesized wave-form versus a previous edge and a position of the next edge is calculated by adding the phase delay to a position of the previous edge, wherein the positions of wave-form edges arc provided by a last of the sequential stages and 3aid positions arc expressed a3 numbers identifying reference sub-clocks needed for generating said wave-form edges.

The above defined SSP can be implemented by processing said inputs from the PCU into a phase modification 3tep which is added to a period of the reference clock in order to calculate the phase delay.

Furthermore this invention includes the SSP circuit upgraded into a parallel multiphase processor (PMP) by extending the time slot allowed for the micro-cycles of the synchronous sequential processor by a factor of P, wherein:

2-P stages are added to the original sequential stage and every one of the resulting 1 -P parallel multiphase stages is clocked with a corresponding 1-P phase sub-clock, wherein such 1 -P phase sub-clock begins during the corresponding to that phase 1-P cycle of the reference clock and has a cycle which is P times longer than the reference clock cycle; whereby consecutive 1 -P parallel multiphase stages have processing cycles overlapping by I cycle of the reference clock wherein every 1 -P parallel processing stage has P times longer cycle time equal to the cycle time of the corresponding 1 -P phase sub-clock used for timing that stage.

The parallel multiphase processor further comprises: a parallel processing phase 2-P built with plurality of 2-P parallel multiphase stages which are connected serially and are driven by the phase sub-clocks belonging to the same 2-P phase.

The SSP invention further comprises a parallel multiphase processing of incoming signal by assigning consecutive parallel phases for the capturing of edge skews and/or processing of other incoming wave-form data with clocks which correspond to consecutive sampling clocks. Consequently the SSP invention comprises using I to N parallel phases which are assigned for processing incoming signal data with clocks corresponding to sampling clock periods numbered from 1 to N, as it is further described below: circuits of phase 1 process edge skews or phase skews or other incoming signal data with a clock which corresponds to the sampling clock period number 1 ; circuits of phase2 process edge skews or phase skews or other incoming signal data with a clock which corresponds to the sampling clock period number 2; finally circuits of phase N process edge skews or phase skews or other incoming signal data with a clock which corresponds to the sampling clock period number N. Said parallel multiphase processing allows N times longer capturing and/or processing times for said multiphase stages, compared with a single phase solution.

The SSP invention includes parallel stage processing of incoming signal by providing multiple processing stages which are driven by the same clock which is applied simultaneously to inputs of output registers of all the parallel stages.

The SSP further application for the edge noise filtering comprises a synchronous sequential processing of incoming signal by using multiple serially connected processing stages with every stage being fed by data from the previous stage which are clocked-in by a clock which is synchronous with the sampling clock.

Since every consecutive stage is driven by a clock which is synchronous to the same sampling clock, all the stages are driven by clocks which are mutually synchronous but may have some constant phase displacements versus each other.

The SSP further comprises: merging of processing phases which occurs if multiple parallel processing phases are merged into a smaller number of parallel phases or into a single processing phase, when passing from a one processing stage to a next processing stage; splitting of processing phases which occurs if one processing phase is split into multiple processing phases or multiple processing stages are split into even more processing stages, when passing from a one processing stage to a next processing stage.

The SSP invention includes a sequential clock generation (SCG) circuit which provides clock selectors for said sub-clocks which are mutually overlapping. Such selected sub-clocks are further used; to generate SSP clocks which drive said parallel phases and said sequential stages, and to generate phase selection signals for said merging and splitting of processing phases. The SSP invention includes time sharing of said parallel phases: which is based on assigning a task of processing of a newly began wave-form pulse to a next available parallel processing phase. The SSP comprises a sequential phase control (SPC) circuit, which uses results of a wave edge decoding and said SSP clocks, for performing said time sharing phase assignments and for further control of operations of an already assigned phase. The SSP comprises passing outputs of a one parallel phase to a next parallel phase, in order to use said passed outputs for processing conducted by a following stage of the next parallel phase.

The outputs passing is performed: by re-timing output register bits of the one phase by clocking them into an output register of the next parallel phase simultaneously with processing results of the next parallel phase. The SSP further comprises all the possible combinations of the above defined: parallel multiphase processing, parallel stage processing, synchronous sequential processing, merging of processing phases, splitting of processing phases, and outputs passing. The SSP invention includes processing stage configurations using selectors, arithmometers, and output registers, which are arranged as it is defined below: input selectors select constant values or outputs of previous stages or outputs of parallel stages or an output of the same stage to provide arithmometer inputs, and arithmometer output is clocked-in to an output register by a clock which is synchronous to the sampling clock; multiple arithmometers are fed with constant values or outputs of previous stages or outputs of parallel stages or an output of the same stage, and an output selector selects an arithmometer output to be clocked-in to an output register by a clock synchronous to the sampling clock; the above defined configuration as being supplemented by using an output of an output selector of a parallel processing stage for controlling output selector functions.

Proper arrangements of said parallel and sequential combinations and said stages configurations provide real time processing capabilities for very wide ranges of signal frequencies and enable a wide coverage of very diversified application areas.

General Description of the WFSC is provided below.

The wave-form screening and capturing circuits (WFSC) comprises: using programmable data masks and programmable control codes for verifying incoming waveform captures for compliance or non-compliance with a pre-programmed screening patterns; buffering captured data for which the pre-programmed compliance or non-compliance have been detected; counting a number of the above mentioned detections; communicating both the buffered captured data and the number of detections, to an internal control unit and/or to an external unit; using programmable time slot selection circuits for selecting a time interval for which waveform captures shall be buffered and communicated to the PCU.

Said PCU comprises implementation of the functions listed below: programming of verification functions and patterns for checking captured wave-forms for compliance or non-compliance with the patterns; reading verification results and reading captured wave-forms which correspond to the preprogrammed verification criteria; reading captured wave-forms which can be pre-selected by the PCU arbitrarily or based on other inputs from the SSP; programming of noise filtering functions and noise filtering masks for filtering captured waveforms; reading results of real-time wave-form processing from the SSP, processing the results and providing control codes and parameters for further real-time wave-form processing in the

SSP, in accordance with adaptive signal processing algorithms; reading output data from the SSP, interpreting the data, and communicating the data to external units.

The WFSC allows the PCU to screen signal quality of incoming wave form, by applying programmable screening functions using programmable data masks, as it is listed beiow: content of said wave buffers can be verified for compliance or non compliance with a mask provided by the PCU, based on verification functions and verification tolerances which are programmed by the PCU; if any wave buffer verification detects preset by PCU screening out criteria to be met, the corresponding content of a wave buffer is captured and made available for PCU for further analysis; in addition to the wave buffer capturing, a number of said screened out results will be counted and communicated to the PCU as well.

In addition to the above mentioned screening; the WFSC allows also the PCU to select arbitrarily a content of any of the wave buffers during any particular time slot; for being captured and made available for analysis by the PCU.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The preferred embodiment implements the above defined general components of the EDF in a configuration particularly useful for receivers of PAM (Pulse Amplitude Modulation) signals belonging to the very mainstream of the present Ethernet technology.

Said EDF comprises over-sampling and capturing of consecutive wave-form intervals in specifically dedicated consecutive wave registers, wherein odd intervals are written into the wave register I WR and even intervals are written into the wave register 2WR (see FIG.3 and FIG.4). Therefore; incoming stream of samples is split into the two parallel processing phases (sometimes named as parallel synchronous pipelines), and such splitting is necessary in order to avoid an overriding of already captured data with next samples captured with continuously overlapping series of sub-clocks of a sampling clock. Furthermore, such splitting into 2 parallel phases obviously doubles cycle time available in the sequential stages following the register 1 WR and in the stages following the 2WR as well.

The first processing phase begins in the wave register 1 WR and the second begins in the register 2WR. A sequential clock generation circuit (see SCG in FIG. l ) includes clock selectors further used for splitting a steady stream of mutually overlapping sub-clocks spaced by a gate delay only into sub-sets of sub-clocks active during their dedicated phases only and non-active during all other phases. Such subsets are obviously used for providing timing for their dedicated phases, as it is shown in the FIG.5-FIG.9.

Generation of such selected sub-clocks is shown in FIG.3 and FIG.4.

The sampling clock period is selected to be equal to 1 /4 of a symbol period of a data stream received in the incoming waveform.

FIG.2 shows 8 interleaved A/D converters producing 16 samples / symbol. A/Ds outputs are captured: in the 1 WR during original 4 cycles of the sampling clock (see l ClkO-4Clkl 2 in FIG.3), and in the 2WR during the next 4 cycles (see 5ClkO-8Clkl 2 in

FIG.4). fn order to implement said pre-filtering; an amplitude averaging filter is implemented as shown in FIG5. The averaging filter of phase 1. calculates arithmetic averages for all 16 samples long sequences of captured samples. Since the phase 1 buffer 1BUF2 and retimed phase2

buffer 1RB2 provide 2x16 samples, the averaging filter of phase 1 can only calculate averages for the 16 samples sequences centered around bits contained in the first half of the 1BUF2 and in the second half of the 1 BUF2. therefore resulting averages specified in the 1 AR4 are shifted ahead of the WRl by 8 samples.

Phase2 is identical to the phase 1 but is shifted in time by 1 symbol period corresponding to 4 cycles of the sampling clock.

Said definition of transition areas for phase 1 is shown in FlG.6.

Previous symbol averages; are re-timed from the phase2 averaging register 2AR4 into the phase I re-timing buffer 1 ARB4, and are subtracted from the phase 1 averages from the 1 AR4. Resulting differences represent said estimates of amplitude change rates per last sampling period. The differences are loaded into the difference register 1 DR5 and compared with said threshold for transition area (TTA). Positive comparison results reload said differences in parallel into the transition area register ITAR6, while negative results reset their corresponding positions in the ITAR6.

Next two sequential stages conduct selection of extreme differences (i.e. extreme rate estimates) and identification of their locations inside the 1DR5 or inside its predecessor from phase2 i.e. 2DR5. As there may be 2 transition areas, two sets of pointers to the extreme differences are provided by the phasel extreme's locations register 1 ELR8 named LEDl and LED2 (see FIG.6).

Edge masks selection is shown in FlG.8. This embodiment selects edge mask with set of pointers comprising: an amplitude average at the point having extreme difference detected (see the 1 AB8 in FlG.8 and in FIG.7); a difference between said point's average and an average of a parallel point occurring one period earlier (see 1 DB8 in FIG.8 and in FIG.7); an averages difference between said parallel point occurring one period earlier and a parallel point occurring two periods earlier than the extreme point (see 1 DRB8 in FIG.8 and notice that the 2DB8 / 2DRB8 are phase2 equivalents of the 1 DB8 / 1 DRB8 shifted in time by one symbol period). Since the extreme's point may occur anywhere between the beginning of the present symbol and the end of the earlier symbol, said extreme's average may belong to the present symbol or to the earlier one.

The selected extreme's average and differences represent the set of mask choosing factors which is provided to the address encoder for edge mask memory (AEEMM) which produces memory address loaded to the maskl/mask2 address registers (IMl AR/1M2AR). This embodiment is based on the assumptions that the TTA; prevents transition areas from being longer than 8 samples, and causes gaps, between said areas, to be longer than 2 samples.

Circuits calculating correlation integrals are shown in the FIG.9.

While said pre-filtering allowed stable immune to noise selection of edge masks, nevertheless it may cause changes to the original unfiltered signal which may compromise quality mask based noise filtering. Therefore unfiltered wave-form samples are used for calculating said correlation integrals in the stage 10 (they are carried through all the buffering stages from the 1 SB3 to 1 SB9 shown in

FIG.7). All needed samples are loaded in the buffers 1 SRPB 10 / 1 SRB 10 /SB 10 and both masks are loaded in the registers I MlR and 1M2R, and mask selector encoder uses mask 2 pointers

SDR2 and EDP2 to encode mask selection signals which are loaded to the mask 2 selection register M2SR 10. Said mask selection signals re-timed by M2SR10 are named Se32-Sel and are used for controlling application of the mask 2 to a second transition area defined by the mask 2 pointers. For every wave-form sample Sk, the correlation integral processors perform basic operations explained below:

Surrounding elements Sk+ι of every samples buffer element Sk, are defined by 1 ranging from -7 to 8. For every such S k a deviation DS k +i from a corresponding mask element Mi is calculated as

Modulus of (S k +ι-Mi) .

Consequently for every such samples buffer element the correlation integral is calculated as equal to:

∑ S k+l -M, l=-7