EDGE INSPECTION AND METROLOGY Background

Over the past several decades, semiconductor-driven technologies have grown exponentially and have revolutionized our society. Manufacturers of semiconductors have made vast improvements in production, resulting in improved end product quality, speed, and performance. However, there continues to be demand for faster, more reliable, and higher performing semiconductors. To assist with these demands, better inspection systems and methods are desirable. Semiconductors are often manufactured in wafer format. For reference, wafers are typically manufactured with multiple layers and include a notch manufactured on the wafer edge for wafer alignment purposes throughout various stages of manufacture. During semiconductor wafer production, masking layers or resist layers are applied to a wafer such that the semiconductor wafer is able to be patterned according to subsequent processing. Typically, a desired amount of liquid resist is applied to a top surface of a wafer while the wafer is being rotated. As the wafer is rotated, the resist material spreads outward radially from the center of the wafer and toward the semiconductor edge such that the wafer is substantially coated with a layer of resist. Excess amounts of resist can accumulate and form a mound or bead of resist on the outer edge of the semiconductor wafer. In order to illuminate the "edge bead" of resist, a coating system known as an edge bead removal (EBR) unit can be employed.

Chemical EBR units include a nozzle, which dispenses a solvent referred to as EBR fluid, onto the resist of the semiconductor wafer. The solvent dissolves or develops away the resist and allows for easy removal of the resist from the edge of the semiconductor wafer. In an optical EBR unit, the resist at or near the edge of the semiconductor wafer is exposed to light. During subsequent development processes, the exposed resist is removed. If the wafer is not centered during EBR removal, the remaining resist layer will not be centered relative to the wafer. Also, variability in an amount of resist removed can contribute to variations in a distance of the resist edge from the wafer edge.

Different EBR units and/or multiple EBR processes, for example, can result in a non-uniform stacking of substrate layers at or near the edge of

semiconductor wafer. Regardless, several undesirable effects can arise as a result of resist layer offset of the wafer. For example, the random or unevenly stacked substrate layers can lift and detrimentally re-deposit onto the semiconductor wafer. The re-deposited substrate material can contaminate the semiconductor wafer and cause defects in the integrated circuit devices formed on the wafer.

Brief Description of the Drawings

Figure 1 is a schematic, top view of an embodiment semiconductor wafer having an edge bead removed in accordance with principles of the present invention.

Figure 2 is a schematic, sectional view of the wafer of Figure 1 along line 2-2 and a schematic view of a portion of an embodiment edge inspection system in accordance with principles of the present invention. Figure 3 is a top, schematic view illustrating an embodiment edge inspection system in accordance with principles of the present invention.

Figure 4 is a schematic, top view of a portion of the wafer of Figure 1.

Figure 5 is a schematic, generalized view of a wafer image in accordance with principles the present invention. Figure 6 is a schematic, generalized view of the wafer image of Figure 5 following image compression in accordance with principles of the present invention.

Figure 7-19 illustrate and describe embodiment features of image compression and wafer edge metrology/inspection accordance with principles of the present invention.

Figure 20 is a flow diagram illustrating one embodiment of an edge bead removal measurement method;

Figure 21 is a flow diagram illustrating one embodiment of a method to determine the edge location of a wafer; Figure 22 is a flow diagram illustrating one embodiment of a method for determining a location of a notch on a wafer edge;

Figure 23 is a flow diagram illustrating one embodiment of a method for determining the location of the center of the wafer;

Figure 24 is a flow diagram illustrating one embodiment of a method for determining the distance from a wafer edge to an edge bead removal location about the circumference of the wafer; and

Figure 25 is a top view of a wafer having multiple layers of resist.

Detailed Description

Wafer edge inspection and metrology is important for a number of reasons. For example, process engineers need to be able to measure the EBR lines to ensure that their processes are proceedingly correctly. For example, the EBR lines are created by flowing resist across the surface of the wafer. The bead formed by the resist at the edge of the wafer is removed over the edge exclusion zone. After patterning and etching, the resist is removed, leaving behind the EBR line or lines, depending on the process or processes undertaken. By measuring these lines in relation to the geometry of the wafer and the wafer edge, such process engineers can ensure that their fabrication processes are operating appropriately, for example.

Thus, in general terms, edge feature measurement systems and methods in accordance with principles of the present invention are used to characterize resist layer outer boundaries proximate an edge of a wafer, as well as other wafer features proximate the wafer edge as desired. Some embodiments include finding a relative distance from an edge of a semiconductor wafer to a resist layer edge, for example where resist was removed about a circumference of the wafer. For reference, resist edges are referred to herein as "EBR lines," although it should be understood that principles of the present invention apply to resist edges formed via a variety of wafer fabrication processes, inclusive of, but not limited to, edge bead removal (EBR) processes. In some embodiments, multiple edge features, such as a wafer edge, a wafer notch or flat, and one or more EBR lines are located. Methods also include finding a center of the wafer and/or a center of one or more resist layers, and, if desired, a relative offset between the wafer center and centers of the one or more resist layers.

As an aid for understanding the discussion that follows, it is noted that some embodiment edge feature measurement systems and methods include acquiring a series of digital images about an edge of a wafer, for example with a

digital inspection camera positioned at a radial offset from a center of a rotating stage. In some embodiments, an entire outer circumference of the wafer is imaged in a continuous and/or stepwise fashion. Wafer notch locations, wafer centers, resist layer centers, EBR line locations, wafer edge locations, and other features are optionally extracted from such image data.

For example, relative locations of the wafer center, a resist layer center, an inspection camera coordinate system, and/or the wafer notch are optionally determined. As will be described in greater detail below, images of the wafer edge are compressed and evaluated cumulatively in order to better evaluate various features. In some embodiments, the distance from the edge of the wafer to the EBR line where resist has been removed is evaluated about the entire circumference of the wafer using such compression. As alluded to above, any number of resist layers may be present on the wafer, each resist layer having an edge bead removed and defining an EBR line. Thus, where applicable, a plurality of EBR lines of interest are identified or tracked in some embodiments.

Additionally, it is contemplated that information obtained by imaging the wafer edge, such as a computed wafer center location, can be used in related inspection processes and systems. For example, wafer center location can be used for reporting and analyzing wafer defects or for allowing an inspection camera positioned to image a profile or side of the wafer edge ("normal edge") to track the normal edge and permit the camera to maintain proper focal distance from the normal edge of the wafer. Thus, in some embodiments, information collected with the EBR inspection systems and methods is used as part of a larger, more detailed wafer characterization system or inspection methodology. With reference to the figures, FIG. 1 illustrates a top view of semiconductor wafer 50. Wafer 50 defines an edge region 100 and includes wafer edge 102, wafer center 104, wafer notch 106, a layer of resist 108, wafer area 110 having the resist removed, resist center 112, resist edge 114, distance 116 between the center edge 102 and the resist edge 114, wafer area 118 where resist should be present, but has been removed, and wafer area 120 with resist present which should have been removed.

FIG. 1 illustrates resist center 112 at offset from wafer center 104. This inconsistency is often due to operator or mechanical error during formation of

the resist 108 and/or removal of portions the resist 108. As previously alluded to, a location of a center of rotation of wafer 50 during fabrication affects the location of resist 108 relative to the wafer center 104. For example, in some embodiments, during various automated fabrication steps wafer 50 is secured on a chuck (not shown). However, due to automation or other errors, the center of rotation is misaligned from wafer center 104 at times. When center of rotation is not aligned with wafer center 104 resist layers, such as the layer of resist 108, are eccentrically positioned relative to wafer 50.

FIG. 1 illustrates resist center 112 being at an exaggerated offset from wafer center 104, such that the misalignment between the two centers 104, 112 is readily discernable. However, it is noted that in practice, misalignment (i.e., deviation from a desired degree of alignment) between centers 104, 112 is often difficult to observe with the naked human eye. With this in mind, it should also be noted that the distance 116 between wafer edge 102 and resist edge 114 is not consistent about the circumference of the wafer 50. Also of note, defective areas such as wafer area 118, which should include resist but do not, can also arise during wafer fabrication. For example, in some manufacturing processes, resist 108 is removed at wafer area 118 as a result of a number of causes, including a variety of fabrication or processing inconsistencies. In some embodiments, defective areas or potentially defective areas such as wafer area 118 are also identified during an edge inspection process. Likewise, areas such as wafer area 120 which include resist, but should not, are optionally identified. For reference, wafer area 120 may also be generated as a product of fabrication errors or processing inconsistencies, for example. FIG. 2 is an enlarged view of edge region 100 along line 2-2 as indicated in FIG. 1. Edge region 100 includes resist edge 114, exposed top region 130 which is substantially free of resist 108, wafer edge 102, and wafer bottom region 134 which is also optionally substantially free of a resist layer, such as resist 108. Wafer edge 102 defines top bevel 136, wafer edge normal 138, and bottom bevel 140.

FIG. 3 is a schematic diagram of an edge inspection system 150 in accordance with principles of the present invention. Edge inspection system 150 includes a top edge sensor 152, a bottom edge sensor 154, a normal edge sensor

156, a controller 158, a base 160, and a stage assembly 162. Top edge sensor 152 includes a camera 164, normal edge sensor 156 includes a camera 166, and bottom edge sensor 154 includes a camera 168. Stage assembly 162 includes a motor 170, an encoder 172, and a support plate 174. Motor 170 is coupled to encoder 172 and support plate 174, such that motor 170 is adapted to rotate support plate 174. Encoder 172 provides counts for controlling the position of motor 170. Support plate 174 supports wafer 50 during rotation and imaging of wafer 50. Controller 158 is electrically coupled to top edge sensor 152 through communication link 176, normal edge sensor 156 is through communication link 178, bottom edge sensor 154 through communication link 180, and staging 130 through communication link 182. Controller 158 controls top edge sensor 152, normal edge sensor 156, bottom edge sensor 154, and stage assembly 162 through communication links 176, 178, 180, and 182 for inspection of edge region 100. In some embodiments, edge region 100 is inspected with edge inspection system 150 from the top, normal, and bottom directions, although other directions/angles of inspection are also contemplated. In general terms, edge inspection system 150 performs edge inspection of the top of edge region 100 (Fig. 2) via top edge sensor 152, the bottom of edge region 100 of wafer 50 via bottom edge sensor 154, and normal to edge region 100 via normal edge sensor 156. Edge inspection system 150 inspects and/or measures along edge region 100 of wafer 50 including resist edge 114, exposed top region 144, and wafer edge 102. In some embodiments, edge inspection system also inspects and/or measures top bevel 136, wafer edge normal 138, and bottom bevel 140 of wafer edge 102.

With reference to FIG. 2, edge top sensor 152 has an inspection area 184, edge normal sensor 156 has an inspection area 186, and edge bottom sensor 154 has an inspection area 188. Thus, in some embodiments, edge inspection system 150 inspects and/or measures along edge region 100 of wafer 122 including resist 108, resist edge 114, exposed top region 130, top bevel 136, edge normal 138, bottom bevel 140, and wafer bottom region 134 as desired. In some embodiments, darkfield and/or brightfield illumination is utilized for inspecting

wafer features, such as for evaluating a location of the resist edge 114 about the circumference of wafer 50.

With reference to FIGS. 4-19 some embodiments of edge inspection according to principles of the present invention include acquiring a plurality of images about a wafer edge region 100 with each image being a pixel array 190 having a first dimension X and a second dimension Y, compressing each pixel array 190 in the first dimension X, stitching the compressed pixel arrays 190 into an edge map, and analyzing the edge map to identify one or more edge features, such as resist edge 108 and wafer edge 102. FIG. 4 illustrates a portion of wafer 50 during acquisition of images about the edge region 100 with the edge inspection system 150. In particular, top edge sensor 152 measures about edge region 100 with wafer 60 being rotated, for example in rotational direction R, such that images about the edge region 100 are acquired. In some embodiments, images are taken about an entirety of the edge region 100. If desired, images are taken at an overlap in order to help ensure complete edge region 100 coverage or increase an amount of image information acquired for greater resolution, as will be described in greater detail below, although non-overlapping images, separated images, and combinations thereof are also contemplated. In one embodiment, for a 200 mm magnification configuration, 128 digital images are secured to ensure 360 degree coverage of images about the wafer 50. However, the top edge inspection camera 152 optionally acquires more numerous frames or less numerous frames as desired, such as up to 360 frames or more, in order to secure images about the entire circumference of the wafer 50 being inspected or a higher resolution edge map. In some embodiments, the top edge inspection camera 152 has a resolution up to 7 micrometers. It should be noted that greater magnification requires additional images, while less magnification requires fewer images in order to fully image the edge region 100. Thus, other combinations of magnification and number of images are contemplated.

FIG. 5 is generally representative of pixel array 190 corresponding to image data from inspection area 184 taken with the top edge sensor 152. In some embodiments, similar data/processes are undertaken using the bottom edge

sensor 156 to image and characterize the bottom of the wafer 50. Regardless, the pixel array 190 optionally includes brightness data relating to the location of the wafer edge 102, the top bevel 136, and the resist edge 114, for example. Pixel array 190 defines a first dimension X and a second dimension Y. As shown, dimension X is substantially tangential to wafer 50, and in particular wafer edge 102, with dimension Y being substantially aligned radially to wafer 50, although other orientations of pixel array 190 are also contemplated. Pixel array 190 includes grayscale brightness information, although other types of information, color data, for example, are also contemplated in some embodiments. During image acquisition, a plurality of pixel arrays 190 are obtained, with each pixel of the pixel arrays 190 having a brightness value. As described below, each of the pixel arrays 190 are sequentially stitched together either prior to compression or following compression in order to properly align the plurality of pixel arrays 190 to form an image map of the edge region 100. In one embodiment, each digital image corresponds to a pixel array 190, also described as an image map, having 1,600 horizontal pixels across the first dimension X and 1,200 vertical pixels across the second dimension Y. Although other pixel arrays are contemplated, for example the pixel array 190 is optionally 1,920 pixels across the first dimension X and 1,078 pixels across the second dimension Y. In some embodiments, the 1,600 x 1,200 array corresponds to a 200 mm image magnification configuration. However, it is understood that if a larger magnification is used, such as a 300 mm configuration, a larger number of digital images are required to fully image the edge region 100 about the circumference of the wafer 50. Similarly, if a smaller magnification is used, such as 100 mm, a smaller number of digital images are required to fully image the edge region 100 about the circumference of the wafer 50.

In some embodiments, one or two full passes around the circumference of wafer 50 are completed with data collected substantially continuously and/or in a stepwise fashion. In some embodiments with two passes, the first pass is brightfield data, while the second pass is darkfield data. If desired, wafer 106 is spun more than a single revolution or more than two revolutions such as 1.1 revolutions, 2.1 revolutions, or other numbers of revolutions as desired in order

to help ensure some overlap at a beginning and end of image acquisition and/or secure a desired amount of image information.

FIG. 6 is a generalized illustration of a compressed image 192 generated by compressing pixel array 190 across first dimension X. In some embodiments, compression is achieved in first dimension X alone, with the second dimension Y not being compressed. Compression across the first dimension X is accomplished via a variety of methods. In some embodiments, pixel array 190 is compressed by averaging the brightness values corresponding to the pixel array 190 across the first dimension X to generate a single column of pixel brightness values in the second dimension Y. Although it is contemplated that the pixel array 190 will be compressed to more columns of pixels in some embodiments. Regardless, via compression across the first dimension X, aberrations in brightness, random variations in brightness, variations in brightness induced by wafer patterning, as well as other undesirable image data effects can be reduced. Thus, in some embodiments, each image is compressed by average pixel rows, in other words, across the first dimension X, resulting in a multitude of images that are full depth in the second dimension Y, but only one pixel wide in the first dimension X. In this manner, variations (such as random image variations or wafer patterning) across the first dimension can be reduced to highlight regular features substantially extending along the first dimension X. Thus, image compression along the first dimension X is used to perform noise and/or undesirable edge suppression, for example.

Various additional features of image compression and wafer edge metrology/inspection in accordance with principles of the present invention are illustrated and described in FIGS. 7-19. In general terms image compression assists in removing or reducing image information relating to wafer patterning, random variations in image data, or other undesirable image information. Such patterns or other random variations can otherwise cause difficulties in finding the resist edge 114 and other EBR lines, as well as other edge features. In some embodiments, following image capture and compression, the images are concatenated, for example via a stitching operation, into a single composite image, also described as an image map, edge map, or EBR map of the compressed images.

With reference to FIGS. 7 and 8, in some embodiments, the wafer edge 102 and top edge bevel 136 are located in the composite image and the composite image is normalized based on the found wafer edge 102 such that the found wafer edge 102 of the composite image can be displayed as a straight line. If need be, the wafer notch 106 or a flat, which appears as a discontinuity in the composite image in some embodiments, can be centered in the composite image by shifting the edges to one side of the composite image, or the other as the images are of a circular, continuous object, i.e., the wafer 50.

In some embodiments, an edge finding algorithm/method is the carried out to locate the EBR lines. In some embodiments, a Canny edge detector and a Sobel edge detector are applied. Based on a starting pixel characteristic and edge threshold condition (contrast in some instances), line segments are "grown" by adding pixels to a segment grouping if they meet selected edge threshold conditions. In some embodiments, a user is allowed to adjust upper and lower edge gradient thresholds, edge strength (e.g., average line segment edge gradient) threshold, and/or segment size thresholds to disregard or highlight particular segment groupings. Accordingly, in some embodiments, only segments of a particular size/edge strength/gradient are processed in subsequent steps. In some embodiments, the segment intensity cross section is analyzed to determine the segment's profile which can be indicative of an EBR line and/or noise and can allow bad segments to be discarded before or during edge fitting. A first segment is selected and a curve is fit to it. In some embodiments, EBR lines are well represented by sinusoidal lines. As such, a sinusoidal curve is selected to fit to the segments. However, other types of curves or lines may be chosen for this fitting process.

In some embodiments, subsequent segments are identified and segment distance (average, median or and/or absolute) from a first curve fit is calculated to see if they would be a good fit with the first fit curve. Where the subsequent segments are a good fit, that segment is concatenated with the first segment and a subsequent curve is fit. This process continues iteratively until an EBR line is characterized. Where segments are too far form an EBR line being formed (as determined by another threshold level), a new curve can be fit to a selected

segment with the process will continue until a desired number of segments or image frames are represented, for example, substantially all image frames, are included in a fitted curve.

With reference to FIG. 19, two, intersecting EBR lines are present. In some embodiments, six line segments A-F are identified, with line segments A-C being merged and segments D-F being merged to result in two, best sinusoidal fits according to the six line segments A-F. Where there is an intersection such as that shown in FIG. 19, resist "overhang" is evaluated, measured, or otherwise characterized in some embodiments. In some embodiments, there will be leftover segments which may or may not be incorporated into one of the generated EBR lines. Once one or more curves have been fitted, non-fitted, borderline, and/or fitted line segments are reviewed and incorporated into one or more fitted curves as desired, such as by reevaluating the line segments according to more forgiving length or edge strength requirements, for example, in view of their proximity to a curve fit selected by a user, of a particular strength, relevance, most fully characterized or otherwise selected.

Once the EBR lines have been generated, various metrics/characteristics of the wafer being inspected are calculated. For example, such metrics/characteristics include: shape of the perimeter formed by the EBR lines, an offset of the center/centroid of shape defined by the EBR lines from the center/centroid of the wafer (R, THETA coordinates and/or DELTAX, DELTAY coordinates), whether the location of the EBR lines are within a specified or other tolerance(s), perimeter information such as the minimum and maximum distances from the centroid of the resist or patterned area defined by the EBR line to the EBR line in question, a roughness measurement or standard deviation number representative of how jagged or smooth the EBR line is can also be generated, a basic shape of the perimeter EBR line can be determined (e.g., circular, elliptical, etc.), "criss-cross" or intersections of multiple EBR lines, mean bevel width, bevel width standard deviation, and others.

In some embodiments, a "golden EBR" image model is created from the compressed EBR images. After a statistically significant number of wafers have been inspected and their images compressed, the compressed images are

combined into a statistical model. Subsequent compressed images are analyzed in light of the model. Image subtraction takes place and the remaining "differences," for example a "difference image," between the "golden EBR" image and the inspection image are analyzed. A pass/fail analysis optionally ensues or an edge finding algorithm is run to obtain EBR information as described above. For example, differences, such as via a difference image, are analyzed for defective EBR lines or other features that are sufficiently different from the "golden EBR" image standard.

With reference to FIGS. 20-25 related methods of identifying, measuring, or otherwise characterizing edge and wafer features are described. It should be understood that those embodiments are to be read cumulatively with embodiments previously described, with features interchanged or added between embodiments as appropriate.

With the above in mind, FIG. 20 is a flow diagram illustrating edge bead removal measurement method 200. At 202, wafer edge 102 of wafer 50 is determined in each of a series of acquired digital images. At 204, notch 104 on wafer edge 102 is determined. At 206, the location of wafer center 104 is determined. At 208, EBR distance 116 from wafer edge 102 to resist edge 114 is determined around the circumference of wafer 50. Each of method steps 202 - 208 will be further described with reference to FIGS. 21-24.

FIG. 21 is a flow diagram illustrating step 202 of FIG. 20 wherein wafer edge 102 of wafer 50 is determined in each of a series of acquired digital images. At 220, a set of digital images is acquired of the wafer region 100 being inspected. The top edge inspection sensor 152 can be utilized to acquire image data around the entire circumference of the wafer 50 at the edge region 100. In some embodiments, the top edge inspection sensor 152 has a resolution up to 7 micrometers. The top edge inspection sensor 152 acquires numerous frames, such as up to 360 frames or more, in order to secure images about the entire circumference of the wafer 50 at the edge region 100. At 222, on the first digital image or frame, a vertical projection is taken.

Utilizing an array of 1,600 horizontal pixels and 1,200 vertical pixels, an array having 1,600 elements is generated. Information from all of the 1,600 elements are added up and the average projection is determined, thereby generating the

vertical projection. At 224, a Canny -type edge detection or other acceptable edge detection routine/filter, such as a LOG routine, is used to find the maximum image gradient in the vertical image projection. At 226, once the location of the maximum image gradient is found from the peak detection of the output of an edge detection filter, a wafer edge tracking routine is configured.

At 228, the wafer edge tracking routine identifies and clusters a given number of pixels behind or after the found peak and a given number of pixels in front or before the peak on each row of the image being processed into a subset. At 230, the subset of pixels is converted from a bayer color image to a green color palette for processing. At 232, a Canny-type edge detector or other acceptable edge detection routine/filter is used to find the maximum gradient in the line region of interest (ROI) of pixels. At 234, the tracking process continues for each row of pixels in each digital image or frame collected. At 236, the last wafer edge location found is used for the center position in the new process line ROI.

The process of finding the wafer notch (step 204 of FIG. 20) is illustrated in greater detail in FIG. 22. As shown in FIG. 22, at 240, the direction of the gradient vector is measured at each pixel location. At 242, digital images which contain pixels that have a gradient vector in one of two predefined ranges are identified. At 244, pixel locations (x, y) are fit to an equation a straight line y = m x + b for each of the two predefined regions. A recursive routine is utilized to eliminate or dropout noise or inconsistencies that are improperly biasing the straight line equations. At 246, points of high noise are dropped out from the line fit equations for each of the two defined regions. At 248, the intersections of the two lines are found which is the location of the wafer notch.

The process of determining the location of the wafer center (step 206 of FIG. 20) is illustrated in greater detail in FIG. 23. At 260, edge location sample points are determined. At 262, the edge location sample points are analyzed via a Fast Fourier Transform routine. At step 264, the magnitude and phase angle of the harmonics of the Fast Fourier Transform routine are analyzed, thereby determining the location of the wafer center.

Once the wafer edge, wafer notch, and wafer center are identified, the resist line EBR line or measurement is determined (step 208 of FIG. 20). This

determination is illustrated in greater detail in FIG. 24. For an EBR location measurement, at 270, a processing ROI is defined by using the wafer edge and a target EBR line along with an EBR search tolerance. The method for finding the EBR line continues at 272 where the process area ROI in each collected digital image or frame is converted from a bayer color image to a green color palette for processing. At 274, a vertical image projection is taken in the processing ROI, similar to the vertical image discussed with reference to step 222. At 276, a Canny-type or other acceptable edge detection routine/filter is run on the vertical projection. At 278, locations of peaks in the filter output that are in a specified range are stored in an edge histogram for that digital image or frame. Generally, the edge histogram is a counter which identifies edge locations with respect to a predetermined threshold. The true edge of the histogram is the location having the largest number of counts. At 280, after all images or frames are processed, the edge histogram of each frame is used to create a complete wafer edge histogram by adding up each image or frame edge histogram. At 282, where the wafer edge histogram is filtered and a control loop determines a value nearest to the target EBR location above a given threshold is chosen to start as the target location for the first EBR edge on the next digital image or frame. In other words, the difference between the last identified edge location on a digital image and the first edge on the next digital image is split or halved, thereby narrowing in on the true edge location. At 284, the target EBR value is compared with each image or frame EBR edge histogram. At 286, the nearest value in the image or frame EBR edge histogram is chosen as the EBR edge location for that frame. At 288, the difference between the target EBR edge location and the found EBR edge location is multiplied by a constant. At 290, the multiplied difference value is added to the old target EBR edge location, which results in the new target EBR edge location for the next image or frame where this is done via a simple servo control loop with gain only. At 292, the above process is repeated until all digital images or frames are processed. At 294, after the digital image or frame EBR edge locations are found, a refinement step can take place were the roughness of each EBR line can be measured from the image or frame EBR value.

A variation in the above procedure is to filter the green buffer data with the Canny-type edge detector or other acceptable edge detection routine/filter.

The output of detector/filter is threasholded. The projection of the treasholded data can then be utilized. This allows counting the number of edge pixels in the EBR line to observe if the EBR line is valid.

Once the above process is complete, the EBR location data is then compared against known process tolerances to make a wafer pass/fail decision. A failed wafer can be stripped and re- worked saving fab manufacturing costs.

FIG. 25 is a top view of wafer 300 having multiple layers of resist. Wafer 300 includes wafer edge 301, wafer notch 304, resist layers 306 and 307, wafer area 308 having resist removed, resist edge 309 of layer 306, resist edge 311 of resist layer 307, edge bead removal distance 312 of resist layer 306 and edge bead removal distance 313 of resist layer 307. During fabrication of wafer 300, multiple layers of resist can be developed upon wafer 300. In such cases, it is sometimes important to determine many EBR lines about the circumference of wafer 300, each EBR line associated with a particular resist layer. The method of process steps shown and described can be utilized to gather separate information on each EBR line of interest. Therefore, all defects or unwanted specification deviations, such as wafer area 118 where resist should be present, but has been removed, or wafer area 120 with resist present which should have been removed, can be identified, regardless of the resist layer from which the defect is attributed. By repeating the process or method steps shown and described, separate and distinct EBR line files can be accumulated for a single wafer. In the foregoing description, certain terms have been used for brevity, clearness and understanding; but no unnecessary limitations are to be implied therefrom beyond the requirement of the prior art, because such terms are used for descriptive purposes and are intended to be broadly construed.

Moreover, the invention's description and illustration is by way of example, and the invention's scope is not limited to the exact details shown or described.

Having now described the features, discoveries and principles of the invention, the manner in which it is constructed and used, the characteristics of

the construction, and the advantageous, new and useful results obtained; the new and useful structures, devices, elements, arrangements, parts and combinations, are set forth in the appended claims.