BACKGROUND

[0001] Resonators are components or systems that oscillate at certain frequencies, known as resonant frequencies, with greater amplitude than at other, often undesired, frequencies, known as spurious modes. One type of resonator, that consists of a piezoelectric material sandwiched between two electrodes and acoustically isolated from the surrounding medium, is a thin-film bulk acoustic resonator (FBAR). FBAR devices may use piezoelectric films with a thickness of as low as fractions of a micrometer and resonate at frequencies from about 100 MHz to 10 GHz. Some applications of FBARs include radio frequency (RF) filters used in wireless communication devices, such as smartphones, in which many radios operating at different frequencies may be integrated. For designing RF band pass filters (Resonator circuits), this spurious mode can cause a spike response in pass band of the filter which deteriorates the filtering function. Also, spurious mode frequencies from one radio may interfere with communications of another radio. Therefore, there is a need for effective spurious mode suppression.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Figs. 1A&1B illustrate cross-sectional views of a resonator suitable for implementing edge patterning, according to some embodiments,

[0004] Figs. 2A-2H illustrate cross-sectional views of manufacturing steps of edge patterning for resonator spurious mode suppression, according to some embodiments,

[0005] Figs. 3A-3H illustrate cross-sectional views of manufacturing steps of edge patterning for resonator spurious mode suppression, according to some embodiments,

[0006] Fig. 4 illustrates an overhead view of an example resonator circuit suitable for implementing edge patterning, according to some embodiments,

[0007] Fig. 5 illustrates a block diagram of an example integrated circuit device with resonator edge patterning, according to some embodiments, [0008] Fig. 6 illustrates a flowchart of a method of forming a resonator with edge patterning, according to some embodiments,

[0009] Fig. 7 illustrates a flowchart of a method of forming a resonator with edge patterning, according to some embodiments, and

[0010] Fig. 8 illustrates a smart device or a computer system or a SoC (System-on-Chip) which includes an integrated circuit device with resonator edge patterning, according to some embodiments.

DETAILED DESCRIPTION

[0011] Edge patterning for resonator spurious mode suppression is generally presented.

In this regard, embodiments of the present invention enable resonators with tapered edges that may be designed to vibrate at a particular frequency while suppressing undesired resonant modes. One skilled in the art would appreciate that these resonators may enable greater integration of smaller and more numerous radios into devices where spurious mode interference may be particularly problematic.

[0012] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0013] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0014] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0015] Unless otherwise specified the use of the ordinal adjectives "first," "second," and

"third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0016] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "left," "right," "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0017] Figs. 1A&1B illustrate cross-sectional views of a resonator suitable for implementing edge patterning, according to some embodiments. As shown, resonator 100 includes substrate 102, supports 104, void region 106, lower electrode 108, piezoelectric material 1 10, upper electrode 1 12, and tapered edges 1 14. While shown as an FBAR, resonator 100 may be some other type of resonator, such as a solidly mounted resonator (SMR) or another type of bulk acoustic wave (BAW) resonator for example, while still incorporating teachings of the present invention. Additionally, resonator 100 may be an FBAR with a different topology, such as without supports 104 or with piezoelectric material 1 10 completely suspended at opposite edges over void region 106, for example.

[0018] Substrate 102 may be a semiconductor substrate. In some embodiments, substrate

102 is silicon. In other embodiments, substrate 102 is gallium arsenide or another semiconductor material. Supports 104 may be included to provide mechanical support and hold the resonating components of resonator 100 over void region 106. In some embodiments, supports 104 comprise silicon dioxide, though other materials may be used. In some embodiments, supports 104 may include a thin diaphragm that extends over void region 106. Electrodes 108 and 1 12 may be conductive materials, for example metals such as Al, Au, W, Pt, Mo, etc. Electrodes 108 and 1 12 may be part of an electrical circuit to excite piezoelectric material 1 10 and communicate a resulting signal response.

[0019] Piezoelectric material 1 10 may include one or more materials with piezoelectric properties. In one embodiment, piezoelectric material 1 10 comprises aluminum nitride. In another embodiment, piezoelectric material 1 10 comprises multiple layers, parallel to a surface of substrate 102, of different piezoelectric materials. In one embodiment, piezoelectric material 1 10 includes alternating layers of A1N and AlInN, in part so that selective etching may be utilized to control depths of tapered steps 1 14.

[0020] As seen in Fig. IB, which represents a cross-sectional view of resonator 100 from the perspective of A- A, piezoelectric material 1 10 includes substantially orthogonal tapered steps 1 14, whereby piezoelectric material 1 10 has disparate widths between opposite surfaces parallel to substrate 102. In some embodiments, tapered steps 1 14 are sloped steps instead of orthogonal steps. While shown as having a narrower width on the surface further away from substrate 102, piezoelectric material 1 10 may instead have a narrower width on the surface closer to substrate 102. Tapered steps 1 14 may be formed using methods described hereinafter or may be formed by other methods that may occur to one skilled in the art. In some embodiments, tapered steps 1 14 are symmetrical on both sides of piezoelectric material 1 10.

[0021] Figs. 2A-2H illustrate cross-sectional views of manufacturing steps of edge patterning for resonator spurious mode suppression, according to some embodiments. As shown in Fig. 2A, assembly 200 includes substrate 202, sacrificial layer 204, lower electrode 206, piezoelectric material 208, piezoelectric material surface 212, and hard mask 214. Sacrificial layer 204 may represent one or more layers of dielectric that have been built up on substrate 202 for later removal as part of a void region creation. Hard mask 214 may have been formed and patterned on piezoelectric material surface 212 to protect a central portion of piezoelectric material surface 212 from subsequent etching steps. In some embodiments, hard mask 214 may represent a previously or subsequently formed upper electrode.

[0022] Fig. 2B shows assembly 210, which may include sets of spacers 216 and 218 deposited on piezoelectric material surface 212 outside of hard mask 214. In some embodiments, spacers 216 and 218 are different materials that can be selectively removed by different processes. While shown as including two sets of spacers, any number of spacers may be utilized of distinct or alternatingly repeating materials. For example, where three sets of spacers are utilized, the spacers may be three distinct materials or a first material spacer adjacent a second material spacer adjacent another first material spacer.

[0023] As shown in Fig. 2C, assembly 220 has had piezoelectric material 208 etched on both sides of piezoelectric surface 212 outside of spacers 218, forming step surfaces 222. In some embodiments, etching of piezoelectric material 208 includes a selective etch process to stop at change of material in a multi -material layered piezoelectric material. In some

embodiments, a depth of step surfaces 222 is determined as part of tapered resonator design based on a desired resonant frequency.

[0024] Turning now to Fig. 2D, assembly 230 may have had spacers 218 selectively etched, without removing spacers 216, to expose piezoelectric material surfaces 232. Spacers 218 may be etched using a selective chemical etch or by some other method known in the art.

[0025] Fig. 2E shows assembly 240, which may have had piezoelectric material 208 etched through piezoelectric material surfaces 232 outside of spacers 216, forming step surfaces 242. In some embodiments, etching of piezoelectric material 208 includes a selective etch process to stop at change of material in a multi -material layered piezoelectric material. In some embodiments, an etching to form step surfaces 242 is proportionally shallower than step surfaces 222 as part of tapered resonator design based on a desired resonant frequency.

[0026] As shown in Fig. 2F, assembly 250 may have had spacers 216 selectively etched, without removing hard mask 214, to expose piezoelectric material surfaces 252. Spacers 216 may be etched using a selective chemical etch or by some other method known in the art.

[0027] Fig. 2G shows assembly 260, which may have had piezoelectric material 208 etched through piezoelectric material surfaces 252 outside of hard mask 214, forming step surfaces 262. In some embodiments, etching of piezoelectric material 208 includes a selective etch process to stop at change of material in a multi -material layered piezoelectric material. In some embodiments, step surfaces 262, 242 and 222 are symmetrical along an imaginary midline of piezoelectric material 208.

[0028] As shown in Fig. 2H, assembly 270 may have had sacrificial layer 204 removed to form void region 272. Additional steps, such as removing hard mask 214 and forming an upper electrode in its place, may be performed to form a resonator, such as resonator 100, for example.

[0029] Figs. 3A-3H illustrate cross-sectional views of manufacturing steps of edge patterning for resonator spurious mode suppression, according to some embodiments. As shown in Fig. 3A, assembly 300 includes substrate 302, sacrificial layer 304, lower electrode 306, interlayer dielectric 308, dielectric surface 309, hard mask 312, and sets of spacers 314 and 316. Interlay er dielectric 308 may be an epoxy or other dielectric material.

[0030] Fig. 3B shows assembly 310, which may have had cavity 318 formed in interlayer dielectric 308 between spacers 316. In some embodiments, cavity 318 is formed by etching interlayer dielectric 308 from dielectric surface 309 through to electrode surface 319. While shown as having a same width as lower electrode 306, cavity 318 may have a greater or lesser width than lower electrode 306.

[0031] As shown in Fig. 3C, assembly 320 has had spacers 316 selectively etched, without removing spacers 314, to expose dielectric surfaces 322. Spacers 316 may be etched using a selective chemical etch or by some other method known in the art.

[0032] Turning now to Fig. 3D, assembly 330 may have had dielectric surfaces 322 etched down to a depth above electrode surface 319 to form etched surfaces 332. In some embodiments, an etching to form etched surfaces 332 is proportionally shallower than electrode surface 319 as part of tapered resonator design based on a desired resonant frequency.

[0033] Fig. 3E shows assembly 340, which may have had spacers 314 selectively etched, without removing hard mask 312, to expose dielectric surfaces 342. Spacers 314 may be etched using a selective chemical etch or by some other method known in the art.

[0034] As shown in Fig. 3F, assembly 350 may have had dielectric surfaces 342 etched down to a depth above etched surfaces 332 to form etched surfaces 352. In some embodiments, etched surfaces 332 and 352 may be symmetrical about an imaginary midline of cavity 318.

[0035] Fig. 3G shows assembly 360, which may have had piezoelectric material 362 deposited into and above cavity 318. In some embodiments, hard mask 312 is still present and piezoelectric material 362 extends above hard mask 312. In other embodiments, hard mask 312 may have been previously removed or piezoelectric material 362 may not extend above hard mask 312. Piezoelectric material 362 may be a single material or combination of materials. In some embodiments, piezoelectric material 362 includes a Ill-nitride superlattice, such as A1N. [0036] As shown in Fig. 3H, assembly 370 may have had piezoelectric material 362 planarized down to surface 372. In some embodiments, surface 372 may correspond to dielectric surface 309. In some embodiments, mechanical polishing is utilized to planarize piezoelectric material 362. In some embodiments, further steps, such as removing interlayer dielectric 308 and sacrificial layer 304, as well as forming an upper electrode on surface 372, would subsequently occur as part of the resonator manufacturing.

[0037] Fig. 4 illustrates an overhead view of an example resonator circuit suitable for implementing edge patterning, according to some embodiments. As shown, resonator circuit 400 includes substrate 402, resonators 404, electrodes 406, piezoelectric material 408, void regions 410 and interconnects 412. While shown as being arranged in a half-ladder configuration, resonator circuit 400 may include any number of resonators 404 in a full-ladder configuration or any other configuration known to one skilled in the art.

[0038] Fig. 5 illustrates a block diagram of an example integrated circuit device with resonator metal meshed framing, according to some embodiments. As shown, device 500 includes resonator circuit 400, control circuit 502, transceiver 504, application processor 506, switch 508 and antenna path 510. In some embodiments, resonator circuit 400 is coupled to control circuit 502 by electrodes 406 and interconnects 412. In some embodiments, transceiver 504 is configured to produce an excitation signal that is applied to electrodes 406. The excitation signal may have an alternating current (AC) component that causes piezoelectric material 408 to vibrate. Resonators 404 may have a characteristic frequency response, that manifests itself in variable electrical characteristics, based on their physical characteristics. In some embodiments, the electrical characteristics of resonators 404 are measured by application processor 506. In some embodiments, device 500 may be a filter, a sensor, or some other device that may benefit from the use of resonators.

[0039] In some embodiments, switch 508, which may be a solid state RF switch, may couple resonator circuit 400 with an antenna through antenna path 510. In some embodiments, resonator circuit 400 may function as an RF bandpass filter in cellular, wi-fi, or other wireless communication circuits to allow a specific band of frequencies to be transmitted along antenna path 510. While shown as being included within a single device 500, the components of device 500 may be included in separate devices, combined into other components, or included to greater or lesser extents. [0040] Fig. 6 illustrates a flowchart of a method of forming a resonator with edge patterning, in accordance with some embodiments. Although the blocks in the flowchart with reference to Fig. 6 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 6 are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

[0041] Method 600 begins with forming (602) piezoelectric material of a resonator, for example piezoelectric material 208 may be formed on lower electrode 206. The piezoelectric material may be a single material or multiple layers of different, or alternating, materials. Next, a hard mask and sets of spacers are formed (604) on a surface of the piezoelectric material. For example hard mask 214 may be centrally formed on piezoelectric material surface 212, with sets of spacers 216 and 218 formed outside of hard mask 214.

[0042] Then, the piezoelectric material may be etched (606) outside of the spacers to a predetermined depth. In some embodiments, step surfaces 222 has a depth designed for a desired resonant frequency. Next, spacers are selectively removed from a surface of, and tapered steps are etched (608) into, the piezoelectric material. In some embodiments, two or three sets of spacers are iteratively removed, however any number of spacers may be used. In some embodiments, step surfaces 222, 242 and 262 are spaced an equidistance apart, while in other embodiments, the step intervals may vary between step surfaces.

[0043] The method continues with removing (610) the hard mask from the piezoelectric material surface. In some embodiments, a mechanical polishing is used. Next, sacrificial material between the lower electrode and substrate may be removed (612), for example by a wet etch process, to form a void region. Finally, an upper electrode may be formed (614) over the piezoelectric material. Further processing steps may be taken to add additional interconnect layers and contacts, for example, to complete the resonator device.

[0044] Fig. 7 illustrates a flowchart of a method of forming a resonator with edge patterning, in accordance with some embodiments. Although the blocks in the flowchart with reference to Fig. 7 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 7 are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur. Additionally, operations from the various flows may be utilized in a variety of combinations.

[0045] Method 700 begins with forming (702) sets of spacers on opposite ends of a surface of a dielectric material over a conductive material, for example sets of spacers 314 and 316 (and hard mask 312) may be formed on dielectric surface 309. Next, the dielectric material is etched (704) between the spacers down to an electrode surface. For example, cavity 318 may be centrally formed over lower electrode 306.

[0046] Then, spacers are selectively removed from a surface of, and tapered steps are etched (706) into, the dielectric material. In some embodiments, two or more symmetrical tapered steps may be iteratively formed in interlay er dielectric 308. Next, piezoelectric material may be deposited (708) in the cavity formed in the dielectric material. In some embodiments, piezoelectric material 362 may extend above interlay er dielectric 308.

[0047] The method continues with planarizing (710) the piezoelectric material. In some embodiments, mechanical polishing planarized piezoelectric material 362 and removes hard mask 312. Next, sacrificial material between the lower electrode and substrate may be removed (712), for example by a wet etch process, to form a void region. Finally, an upper electrode may be formed (714) over the piezoelectric material. Further processing steps may be taken to add additional interconnect layers and contacts, for example, to complete the resonator device.

[0048] Fig. 8 illustrates a smart device or a computer system or a SoC (System-on-Chip)

800 which includes an integrated circuit device with resonator edge patterning, according to some embodiments. In some embodiments, computing device 800 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless- enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 800. In some embodiments, one or more components of computing device 800, for example processor 810 and/or connectivity 870, include an integrated circuit device with resonator edge patterning as described above. [0049] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon

Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

[0050] In some embodiments, computing device 800 includes a first processor 810. The various embodiments of the present disclosure may also comprise a network interface within 870 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0051] In one embodiment, processor 810 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 810 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O

(input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 800 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[0052] In one embodiment, computing device 800 includes audio subsystem 820, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 800, or connected to the computing device 800. In one embodiment, a user interacts with the computing device 800 by providing audio commands that are received and processed by processor 810. [0053] Display subsystem 830 represents hardware (e.g., display devices) and software

(e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 800. Display subsystem 830 includes display interface 832, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 832 includes logic separate from processor 810 to perform at least some processing related to the display. In one embodiment, display subsystem 830 includes a touch screen (or touch pad) device that provides both output and input to a user.

[0054] I/O controller 840 represents hardware devices and software components related to interaction with a user. I/O controller 840 is operable to manage hardware that is part of audio subsystem 820 and/or display subsystem 830. Additionally, I/O controller 840 illustrates a connection point for additional devices that connect to computing device 800 through which a user might interact with the system. For example, devices that can be attached to the computing device 800 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[0055] As mentioned above, I/O controller 840 can interact with audio subsystem 820 and/or display subsystem 830. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 800. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 830 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 840. There can also be additional buttons or switches on the computing device 800 to provide I/O functions managed by I/O controller 840.

[0056] In one embodiment, I/O controller 840 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 800. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[0057] In one embodiment, computing device 800 includes power management 850 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 860 includes memory devices for storing information in computing device 800. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 860 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 800.

[0058] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 860) for storing the computer-executable instructions. The machine-readable medium (e.g., memory 860) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[0059] Connectivity 870 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 800 to communicate with external devices. The computing device 800 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[0060] Connectivity 870 can include multiple different types of connectivity. To generalize, the computing device 800 is illustrated with cellular connectivity 872 and wireless connectivity 874. Cellular connectivity 872 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile

communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 874 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication. [0061] Peripheral connections 880 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 800 could both be a peripheral device ("to" 882) to other computing devices, as well as have peripheral devices ("from" 884) connected to it. The computing device 800 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 800. Additionally, a docking connector can allow computing device 800 to connect to certain peripherals that allow the computing device 800 to control content output, for example, to audiovisual or other systems.

[0062] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 800 can make peripheral connections 880 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[0063] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or

characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an

embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[0064] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive [0065] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[0066] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[0067] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0068] In one example, an apparatus is provided comprising: a substrate; a piezoelectric resonator separated from a surface of the substrate by a void region; a first electrode coupled to a first surface of the piezoelectric resonator parallel to the substrate surface; and a second electrode coupled to a second surface of the piezoelectric resonator parallel to the substrate surface, wherein the first and second surfaces of the piezoelectric resonator comprise disparate widths, and wherein the piezoelectric resonator comprises a plurality of substantially orthogonal tapering steps between the first and second surfaces.

[0069] In some embodiments, the first surface of the piezoelectric resonator comprises a narrower width, and is closer to the substrate surface, than the second surface of the piezoelectric resonator. In some embodiments, the first surface of the piezoelectric resonator comprises a narrower width, and is further from the substrate surface, than the second surface of the piezoelectric resonator. In some embodiments, the piezoelectric resonator comprises aluminum nitride. In some embodiments, the piezoelectric resonator comprises alternating layers of discrete materials. In some embodiments, the piezoelectric resonator comprises symmetrical tapering steps.

[0070] In another example, a system is provided comprising: a display subsystem; a wireless communication interface; and an integrated circuit device, the integrated circuit device comprising a film bulk acoustic resonator (FBAR) comprising: a substrate; a piezoelectric resonator separated from a surface of the substrate by a void region; a first electrode coupled to a first surface of the piezoelectric resonator parallel to the substrate surface; and a second electrode coupled to a second surface of the piezoelectric resonator parallel to the substrate surface, wherein the first and second surfaces of the piezoelectric resonator comprise disparate widths, and wherein the piezoelectric resonator comprises a plurality of substantially orthogonal tapering steps between the first and second surfaces.

[0071] In some embodiments, the piezoelectric resonator comprises aluminum nitride. In some embodiments, the piezoelectric resonator comprises symmetrical tapering steps. In some embodiments, the first surface of the piezoelectric resonator comprises a narrower width, and is further from the substrate surface, than the second surface of the piezoelectric resonator. In some embodiments, the piezoelectric resonator comprises alternating layers of discrete materials. Some embodiments also include a plurality of FBARs communicatively coupled with each other.

[0072] In another example, a method is provided comprising: forming first and second sets of spacers on a surface of a piezoelectric resonator; removing the first set of spacers; etching the surface of the piezoelectric resonator exposed by removing the first set of spacers down to a first depth; removing the second set of spacers; and etching the surface of the piezoelectric resonator exposed by removing the second set of spacers down to a second depth.

[0073] Some embodiments also include etching an uncovered portion of the surface of the piezoelectric resonator down to a third depth. In some embodiments, the first and second sets of spacers comprise disparate materials. In some embodiments, removing the first set of spacers comprises performing a selective etch that does not remove the second spacers. In some embodiments, etching the piezoelectric resonator comprises performing a selective etch that removes a first material but not a second material of a multi -layer piezoelectric material. Some embodiments also include forming an electrode on the surface of the piezoelectric resonator. [0074] In another example, a method is provided comprising: depositing dielectric material on a metal film; forming first and second sets of spacers on a surface of the dielectric material; etching the surface of the dielectric material between the first and second sets of spacers down to the metal film; removing the first set of spacers; etching the surface of the dielectric material exposed by removing the first set of spacers down to a first depth; removing the second set of spacers; etching the surface of the dielectric material exposed by removing the second set of spacers down to a second depth; and depositing piezoelectric material in a cavity formed from etching the dielectric material.

[0075] In some embodiments, the first and second sets of spacers comprise disparate materials. In some embodiments, removing the first set of spacers comprises performing a selective etch that does not remove the second spacers. Some embodiments also include planarizing the piezoelectric material down to the surface of the dielectric material. Some embodiments also include forming a metal layer on a planarized surface of the piezoelectric material. Some embodiments also include removing the dielectric material surrounding the piezoelectric material. Some embodiments also include removing a sacrificial material between the metal film and a substrate to create a void region.

[0076] In another example, a bulk acoustic wave (BAW) resonator is provided comprising: means for supporting a piezoelectric resonator body over a void region; means for conducting electrical signals generated by the piezoelectric resonator body; and means for suppressing spurious modes of the BAW resonator within the resonator body.

[0077] In some embodiments, the means for suppressing spurious modes comprises a plurality of substantially orthogonal tapering steps between first and second surfaces of the resonator body. In some embodiments, the means for suppressing spurious modes comprises symmetrical tapering steps. In some embodiments, the piezoelectric resonator body comprises aluminum nitride. In some embodiments, the piezoelectric resonator comprises alternating layers of discrete materials. In some embodiments, the means for suppressing spurious modes comprises a first surface of the piezoelectric body comprising a narrower width, and is further from a substrate surface, than a second surface of the piezoelectric body. Some embodiments also include a plurality of BAW resonators communicatively coupled with each other.

[0078] In another example, a wireless communication system is provided comprising: a processor; a display subsystem; and a wireless communication interface, the wireless communication interface comprising an antenna and a film bulk acoustic resonator (FBAR) coupled with the antenna to provide bandpass filtering, the FBAR comprising: a substrate; a piezoelectric resonator separated from a surface of the substrate by a void region; a first electrode coupled to a first surface of the piezoelectric resonator parallel to the substrate surface; and a second electrode coupled to a second surface of the piezoelectric resonator parallel to the substrate surface, wherein the first and second surfaces of the piezoelectric resonator comprise disparate widths, and wherein the piezoelectric resonator comprises a plurality of substantially orthogonal tapering steps between the first and second surfaces.

[0079] In some embodiments, the first surface of the piezoelectric resonator comprises a narrower width, and is closer to the substrate surface, than the second surface of the piezoelectric resonator. In some embodiments, the first surface of the piezoelectric resonator comprises a narrower width, and is further from the substrate surface, than the second surface of the piezoelectric resonator. In some embodiments, the piezoelectric resonator comprises aluminum nitride. In some embodiments, the piezoelectric resonator comprises alternating layers of discrete materials. In some embodiments, the piezoelectric resonator comprises symmetrical tapering steps. Some embodiments also include a plurality of FBARs communicatively coupled with each other.

[0080] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.