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Patent Searching and Data


Title:
EFFICIENT ADDRESS TRANSLATION
Document Type and Number:
WIPO Patent Application WO/2016/154795
Kind Code:
A1
Abstract:
One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

Inventors:
ZHONG XUELIANG (CN)
WU YONG (CN)
JIN YIHUA (CN)
LI JIANHUI (CN)
LIN XIAODONG (CN)
Application Number:
PCT/CN2015/075219
Publication Date:
October 06, 2016
Filing Date:
March 27, 2015
Export Citation:
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Assignee:
INTEL CORP (US)
ZHONG XUELIANG (CN)
WU YONG (CN)
JIN YIHUA (CN)
LI JIANHUI (CN)
LIN XIAODONG (CN)
International Classes:
G06F9/45
Foreign References:
US20140379955A12014-12-25
US8402248B22013-03-19
US20140317374A12014-10-23
US20140122781A12014-05-01
US20110320663A12011-12-29
Other References:
JIANJUN LI ET AL., DYNAMIC REGISTER PROMOTION OF STACK VARIABLES
See also references of EP 3274824A4
Attorney, Agent or Firm:
CHINA PATENT AGENT (H.K.) LTD. (Great Eagle Center23 Harbour Road,Wanchai, Hong Kong, CN)
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