Title:
ELECTRIC CIRCUIT AND SIGNAL PROCESSING METHOD
Document Type and Number:
WIPO Patent Application WO/2010/029644
Kind Code:
A1
Abstract:
In an electric circuit including a plurality of circuit blocks that operate with different clocks, a noise generated by a first circuit that operates with a first clock at an output of a second circuit that operates with a second clock whose frequency is different from that of the first clock is reduced. For this object, the electric circuit comprises a synchronization detection circuit for detecting synchronization between the first clock and the second clock, a storage circuit for storing an output noise pattern of the second circuit according to the synchronization detection of the synchronization detection circuit, and a correction circuit. The correction circuit corrects the output of the second circuit by using the output noise pattern.
More Like This:
WO/2013/064980 | POWER REGULATION IN INTER-BAND CARRIER AGGREGATION |
JPS54144115 | METHOD OF AND DEVICE FOR ELIMINATING RADIO NOISE |
Inventors:
SATO TOMIO (JP)
Application Number:
PCT/JP2008/066595
Publication Date:
March 18, 2010
Filing Date:
September 12, 2008
Export Citation:
Assignee:
FUJITSU LTD (JP)
SATO TOMIO (JP)
SATO TOMIO (JP)
International Classes:
H04B15/02
Foreign References:
JPH06225185A | 1994-08-12 | |||
JP2005027004A | 2005-01-27 | |||
JPH09135213A | 1997-05-20 | |||
JP2005341278A | 2005-12-08 | |||
JPH0228707A | 1990-01-30 |
Attorney, Agent or Firm:
AOKI, Atsushi et al. (JP)
Aoki 篤 (JP)
Aoki 篤 (JP)
Download PDF: