Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
ELECTRIC CIRCUIT WITH LOW VOLTAGE DROP
Document Type and Number:
WIPO Patent Application WO/2018/097794
Kind Code:
A1
Abstract:
An electric circuit (2) for connection to an electric equipment (1 ) and to a polarity dependent unit (3), the electric system being arranged to receive an input signal from the electric equipment (1 ) and to return an output signal in response to an impedance signal from the polarity dependent unit (3), wherein the electric circuit (2) comprises: a first input terminal (4) and a second input terminal (5) which are connectable to opposite poles of the electric equipment (1 ), and a positive output terminal (6) and a negative output terminal (7) which are connectable to a positive and a negative pole, respectively, of the polarity dependent unit (3). The electric circuit (2) further comprises: a polarity probe (8), and at least four transistor units (T1, T2, T3, T4) and where the polarity probe is arranged to provide an indication of the polarity between the first and second input terminals (4, 5) and where the transistor units (T1, T3) and the transistor units (T2, T4) are set in either a conducting or a non-conducting mode in response to the indicated polarity.

Inventors:
BORG, Henrik (Klövervägen 10, Norsborg, 145 67, SE)
JOHANSSON, Jan (Framnäsbacken 6, Solna, 171 66, SE)
Application Number:
SE2017/051174
Publication Date:
May 31, 2018
Filing Date:
November 27, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MANETOS AB (Linnégatan 18, STOCKHOLM, 114 47, SE)
International Classes:
H02M7/219; H02H11/00; H02M1/10; H03K17/06
Domestic Patent References:
WO2016105267A12016-06-30
WO2016105267A12016-06-30
Foreign References:
US6181588B12001-01-30
US20140268956A12014-09-18
US20130200874A12013-08-08
US20100046264A12010-02-25
US6181588B12001-01-30
US20140268956A12014-09-18
US20130200874A12013-08-08
US20100046264A12010-02-25
Other References:
MOSFET-H-BRIDGE, 2016, Retrieved from the Internet
Attorney, Agent or Firm:
EHRNER & DELMAR PATENTBYRÅ AB (Drottninggatan 33, plan 4, Stockholm, 111 51, SE)
Download PDF:
Claims:
An electric circuit (2) for connection of a polarity dependent unit (3) to an electric equipment (1 ), which electric circuit (2) comprises:

a first input terminal (4) and a second input terminal (5) which are connectable to opposite poles of the electric equipment (1 ), and

a positive output terminal (6) and a negative output terminal (7) which are connectable to a positive and a negative pole, respectively, of the polarity dependent unit (3),

a first input path over a first transistor unit (T1 ) connecting the first input terminal (4) to the positive output terminal (6), and a first output path over a third transistor unit (T3) connecting the negative output terminal (7) to the second input terminal (5), and

a second input path over a second transistor unit (T2) connecting the second input terminal (5) to the positive output terminal (6), and a second output path over a fourth transistor unit (T4) connecting the negative output terminal (7) to the first input terminal (5), wherein the first and third transistor units (T1 ,T3) are set in a conducting mode and the second and fourth transistor units (T2,T4) are set in a non-conducting mode in response to a positive polarity between the first input terminal (4) and the second input terminal (5), and the first and third transistor units (T1 ,T3) are set in a non-conducting mode and the second and fourth transistor unit (T2,T4) are set in a conducting mode in response to a negative polarity between the first input terminal (4) and the second input terminal (5), the electric circuit (2) further comprising a polarity probe (8) arranged to provide an indication of the polarity between the first input terminal (4) and the second input terminal (5) and

wherein a first output (Out_A) of the polarity probe (8) controls the first and third transistor units (T1 ,T3), and wherein a second output (Out_B) of the polarity probe (8), which is inverted with respect to the first output (Out_A), controls the second and fourth transistor units (T2,T4), wherein the first transistor unit (T1 ) and the second transistor unit (T2) each include a voltage pull-up system to pull up a positive control voltage of either the first or second output (Out_A, Out_B) of the polarity probe (8), so that the first or second transistor unit are set in a conducting mode in response to a positive control voltage regardless of the magnitude of a potential difference between the first input terminal (4) and the second input terminal (5),

wherein the voltage pull-up system of the first transistor unit (T1 ) comprises a first resistor (R1 ) and a first transistor (T1 1 ) connected in series either between the positive output terminal (6) and the negative output terminal (7) or between the second input terminal (5) and the positive output terminal (6), wherein the first transistor (T1 1 ) is a N-MOS transistor controlled between a conducting and nonconducting mode by the first output (Out_A) of the polarity probe (8) and which, when in conducting mode, connects either the negative output terminal (7) or the second input terminal (5) via the first resistor (R1 ) to the positive output terminal (6) and to a control input of a second transistor (T12), not via said first resistor (R1 ), to thereby transmit a low voltage to said control input of the second transistor (T12), and wherein the second transistor (T12) is a P-MOS transistor that is set in a conducting mode in response to a low control voltage and which, when in conducting mode, connects the first input terminal (4) to the positive output terminal (6); and wherein the voltage pull- up system of the second transistor unit (T2) comprises a second resistor (R2) and a first transistor (T21 ) connected in series between either the positive output terminal (6) and the negative output terminal (7) or between the first input terminal (4) and the positive output terminal (6), and wherein the first transistor (T21 ) is a N-MOS transistor controlled between a conducting and non-conducting mode by the second output (Out_B) of the polarity probe (8) and which, when in conducting mode, connects either the negative output terminal (7) or the first input terminal (4) via the first resistor (R1 ) to the positive output terminal (6) and to a control input of a second transistor (T22) , not via said second resistor (R2), to thereby transmit a low voltage to said control input of the second transistor (T22), and wherein the second transistor

(T22) is a P-MOS transistor that is set in in conducting mode in response to a low control voltage and which, when in conducting mode, connects the second input terminal (5) to the positive output terminal (6),

wherein the first transistor unit (T1 ) comprises a third transistor (T13), which is a N- MOS transistor controlled by the first output (Out_A) of the polarity probe (8) and which is arranged in parallel to the second transistor (T12) thereby also connecting the first input terminal (4) to the positive output terminal (6) when in conducting mode, and wherein the second transistor unit (T2) comprises a third transistor (T23), which is a N-MOS transistor controlled by the second output (Out_B) of the polarity probe (8) and which is arranged in parallel with the second transistor (T22) thereby also connecting the second input terminal (4) to the positive output terminal (6) when in conducting mode,

characterised in that the first transistor unit (T1 ) comprises a fourth transistor (T14), which is a P-MOS transistor arranged in parallel to the first resistor (R1 ) of the first transistor unit (T1 ) and the second transistor unit (T2) comprises a fourth transistor

(T24), which is a P-MOS transistor arranged in parallel to the second resistor (R2) of the second transistor unit (T2), wherein the fourth transistor (T14) of the first transistor unit (T1 ) is controlled by a control signal based on the voltage between the first transistor (21 ) and the second resistor (R2) of the second transistor unit (T2) and the fourth transistor (T24) of the second transistor unit (T2) is controlled by a control signal based on the voltage between the first transistor (T1 1 ) and the first resistor (R1 ) of the first transistor unit (T1 ).

The electric circuit (2) according to claim 1 , wherein the polarity probe (8) is a comparator connected to indicate the polarity between the first input terminal (4) and the second input terminal (5).

The electric circuit (2) according to claim 1 , wherein the polarity probe (8) is a logical circuit.

Description:
ELECTRIC CIRCUIT WITH LOW VOLTAGE DROP

TECHNICAL FIELD

[0001 ] The invention relates to an electric circuit with a low voltage drop. Specifically, the invention relates to a circuit for providing the same output polarity for either input polarity. Further, the circuit is adapted to deliver a voltage output that has substantially no voltage drop regardless of the magnitude of the input voltage.

BACKGROUND

[0002] In many applications it is desired to deliver the same output polarity for either input polarity. A typical way of achieving this is by using a diode bridge. A diode bridge is however adapted to function as an ac/dc converter, i.e. to rectify an alternating current and voltage into a direct current and dc-voltage. The invention is not intended for alternating voltage applications, it is intended for applications with continuous voltages, i.e. dc-voltages. A disadvantage of a diode bridge in the application of providing the same output polarity for either input polarity of direct current would be that it involves a relatively constant voltage drop. In some applications, a voltage drop, even a constant one, is not acceptable. One such application is the connection of an equipment to the thermistor line of a heat control system, in which a circuit is arranged to deliver an output signal from an input signal received from an electric heat equipment in order to control said equipment.

[0003] In WO 2016/105267 a system is disclosed in which an electric circuit comprising two equivalent impedance networks is used as a substitute means for providing an alternative impedance signal instead of a signal from a basic impedance means, such as a temperature sensor. The circuit in WO 2016/105267 functions well, but has a disadvantage in that it involves two separate impedance networks of which only one is used at a time, depending on the input polarity. [0004] Hence there is a need of an electric circuit that provides the same output polarity for either input polarity but that includes less components than prior art circuit.

SUMMARY OF THE INVENTION

[0005] It is an object of the present invention to provide an electric circuit that provides the same output polarity for either input polarity without a voltage drop and, preferably with a limited number of components. [0006] The invention relates to an electric circuit for connection of a polarity dependent unit to an electric equipment, wherein the electric circuit comprises:

a first input terminal and a second input terminal which are connectable to opposite poles of the electric equipment, and

- a positive output terminal and a negative output terminal which are connectable to a positive and a negative pole, respectively, of the polarity dependent unit. The electric circuit further comprises:

a first input path over a first transistor unit connecting the first input terminal to the positive output terminal, and a first output path over a third transistor unit connecting the negative output terminal to the second input terminal, and

a second input path over a second transistor unit connecting the second input terminal to the positive output terminal, and a second output path over a fourth transistor unit connecting the negative output terminal to the first input terminal, wherein the first and third transistor units are set in a conducting mode and the second and fourth transistor units are set in a non-conducting mode in response to a positive polarity between the first input terminal and the second input terminal, and the first and third transistor units are set in a nonconducting mode and the second and fourth transistor unit are set in a conducting mode in response to a negative polarity between the first input terminal and the second input terminal.

[0007] In the inventive electric circuit, the output polarity will always be the same regardless of the input polarity. This is advantageous since it guarantees that the polarity dependent unit will receive a signal of correct polarity regardless of the polarity over the input terminals. Further, this is achieved with a minimum of losses. Namely, transistors, unlike diodes, may be free from voltage drops.

[0008] A polarity probe is arranged to provide an indication of the polarity between the first input terminal and the second input terminal, wherein a first output of the polarity probe controls the first and third transistor units, and wherein a second output of the polarity probe, which is inverted with respect to the first output, controls the second and fourth transistor units.

[0009] The first transistor unit and the second transistor unit each include a voltage pull-up system to pull up a positive control voltage of either the first or second output of the polarity probe, so that the first or second transistor unit may be set in a conducting mode in response to a positive control voltage regardless of the magnitude of a potential difference between the first input terminal and the second input terminal. [0010] The voltage pull-up system of the first transistor unit comprises a first resistor and a first transistor connected in series either between the positive output terminal and the negative output terminal or between the second input terminal and the positive output terminal 6, wherein the transistor is a N-MOS transistor controlled between a conducting and non-conducting mode by the first output of the polarity probe and which, when in conducting mode, connects either the negative output terminal or the second input terminal via the first resistor to the positive output terminal and to a control input of a second transistor, not via said first resistor, to thereby transmit a low voltage to said control input of the second transistor, and wherein the second transistor is a P-MOS transistor that is set in in conducting mode in response to a low control voltage and which, when in conducting mode, connects the first input terminal to the positive output terminal; wherein the voltage pull-up system of the second transistor unit comprises a second resistor and a first transistor connected in series between either the negative output terminal and the positive output terminal or between the first input terminal and the positive output terminal, wherein the transistor is a N-MOS transistor controlled between a conducting and non-conducting mode by the second output of the polarity probe and which, when in conducting mode, connects the negative output terminal or the first input terminal via the second resistor to the positive output terminal and to a control input of a second transistor, not via said second resistor, to thereby transmit a low voltage potential to said control input of the second transistor, and wherein the second transistor is a P-MOS transistor that is set in in conducting mode in response to a low control voltage potential and which, when in conducting mode, connects the second input terminal to the positive output terminal.

[001 1 ] Hence, when the first transistor is in a non-conducting mode, the second resistor pulls the control signal for the second transistor to a high potential voltage through the second transistors body diode making it possible to control the second transistor for higher voltages on the second input terminal than the output voltages on the polarity probe can provide for controlling the second transistor.

[0012] The first transistor unit comprises a third transistor, which is a N-MOS transistor controlled by the first output of the polarity probe and which is arranged in parallel with the second transistor thereby also connecting the first input terminal to the positive output terminal when in conducting mode, thereby overcoming the problem when the input voltage is too low to set the second transistor into a conducting mode; and wherein the second transistor unit comprises a third transistor, which is a N-MOS transistor controlled by the second output of the polarity probe and which is arranged in parallel with the second transistor thereby also connecting the second input terminal to the positive output terminal when in conducting mode.

[0013] The first transistor unit comprises a fourth transistor, which is a P-MOS transistor arranged in parallel to the first resistor of the first transistor unit and the second transistor unit comprises a fourth transistor, which is a P-MOS transistor arranged in parallel to the second resistor of the second transistor unit, wherein the fourth transistor of the first transistor unit is controlled by a control signal based on the voltage between the first transistor and the second resistor of the second transistor unit and the fourth transistor of the second transistor unit is controlled by a control signal based on the voltage between the first transistor and the first resistor of the first transistor unit.

[0014] The polarity probe may be a comparator connected to indicate the polarity between the first input terminal and the second input terminal, or it may be a logical circuit.

[0015] Other embodiments and advantages will be apparent from the detailed description and the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] Below, the invention will be described with reference to the appended drawings, of which;

Fig. 1 shows a circuit diagram according to a first embodiment of the invention,

Fig. 2 shows a circuit diagram according to a second embodiment of the invention, Fig. 3 shows a circuit diagram according to a third embodiment of the invention,

Fig. 4 shows a circuit diagram according to a fourth embodiment of the invention, and

Fig. 5 shows a circuit diagram according to a fifth embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

[0017] In Fig. 1 is a circuit diagram of a first embodiment of an electric circuit 2 for connection of a polarity dependent unit 3 to an electric equipment 1 . The electric circuit 2 may be arranged to receive an input signal from the electric equipment 1 and to return an output signal to the electric equipment 1 in response to an impedance signal from the polarity dependent unit 3. The electric circuit 2 comprises a first input terminal 4 and a second input terminal 5 which are connectable to opposite poles of the electric equipment 1 , and a positive output terminal 6 and a negative output terminal 7 which are connectable to a positive and a negative pole, respectively, of the polarity dependent unit 3.

[0018] Further, the electric circuit 2 of the first embodiment comprises a polarity probe 8, typically a comparator or a logical circuit, arranged to provide an indication of the polarity between the first input terminal 4 and the second input terminal 5. The first and third transistor units T1 ,T3 are controlled to a conducting mode and the second and fourth transistor unit T2,T4 are controlled to a non-conducting mode in response of a positive polarity between the first input terminal 4 and the second input terminal 5, and the first and third transistor units T1 ,T3 are controlled to a non-conducting mode and the second and fourth transistor unit T2,T4 are controlled to a conducting mode in response of a negative polarity between the first input terminal 4 and the second input terminal 5.

[0019] A transistor has three terminals. Throughout this specification these are defined as an input side, an output side and a control input. The transistor is arranged to conduct current from the input side to the output side depending on the voltage potential of the incoming control signal compared to the voltage potential at either the input side, or the output side. An N-MOS transistor is put into conducting mode when the voltage drop from the control signal to the voltage potential in the input side is sufficiently high and a P-MOS transistor is put into conducting mode when the voltage drop from the voltage potential on the output side to the voltage potential of the control signal is sufficiently high. Hence, as a general rule an N-MOS transistor is set in a conducting mode in response to a sufficiently high voltage control signal, and P-MOS transistor is set in a conducting mode in response to a sufficiently low voltage control signal.

[0020] The control signals are in the drawings indicated by dotted lines and conducting paths are indicated by un-broken lines. [0021 ] Hence, in response to a voltage where the first input terminal 4 has a higher potential than the second input terminal 5, typically 2 volt and 0 volt, respectively, the first transistor unit T1 and third transistor unit T3 will be controlled to a conducting mode, whereas the second transistor unit T2 and fourth transistor unit T4 will be controlled to a nonconducting mode, such that a first input path over the first transistor unit T1 connects the first input terminal 4 to the positive output terminal 6, and a first output path over the third transistor unit T3 connects the negative output terminal 7 to the second input terminal 5.

[0022] In the opposite case, i.e. where the second input terminal 5 has a higher potential than the first input terminal 4 a second input path over the second transistor unit T2 connects the second input terminal 5 to the positive output terminal 6, and a second output path over the fourth transistor unit T4 connects the negative output terminal 7 to the first input terminal 6. The first and third transistor units T1 ,T3 are in this case controlled to a nonconducting mode.

[0023] In the shown first embodiment all transistor units T1 -T4 are transistors of the N- MOS type, which are arranged in pairs where one pair at a time is set to a conducting mode in response to a relatively high control voltage from the polarity probe 8, resulting in a low potential difference over the transistor units of the corresponding pair. In the shown embodiments the first and third transistor units T1 and T3 constitute a first transistor pair and the second and fourth transistor units T2 and T4 constitute a second transistor pair. [0024] A prerequisite for the first and second transistor unit T1 and T2 to be in conducting mode is that the control signal, fed to them via the respective control line, from the polarity probe 8 has a greater potential than the voltage delivered from the corresponding input terminal (4 or 5) plus the required potential difference required to make T1 and T2 conductive without losses. This may be achieved in different ways as explained in the embodiments below.

[0025] In the embodiments below the construction the configuration of the first and second transistor units T1 and T2 is different between the different embodiments. However, for all embodiments, the first transistor unit T1 and the second transistor unit T2 are identical within that specific embodiment and have the same function, but only one of them at a time conducts current. The incoming polarity decides which one of them that is conducting.

Likewise, for all embodiments the third transistor unit T3 and the fourth transistor unit T4 are identical and have the same function, but only one of them at a time conducts current, depending on the incoming polarity.

[0026] A second embodiment is shown in figure 2. In this embodiment the first transistor unit T1 and the second transistor unit T2 are specified as involving two transistors each T1 1 ,T12 and T21 ,T22, respectively. Further each transistor unit T1 and T2 comprises a first resistor R1 and a second resistor R2, respectively, which are arranged to function as pull-up resistors to pull up the control voltage to the second transistors T12 and T22, respectively. This arrangement therefore allows for the second transistors T12 and T22 to handle higher voltages than the polarity probe 8 can output and therefore the circuit can handle higher voltages on the first and second inputs 4 and 5.

[0027] The arrangement allows the possibility of pulling up the voltage of the control signal delivered by the polarity probe 8 to the voltage level of the corresponding input terminal 4 or 5 so as to open the corresponding transistor unit T1 and T2 into a conducting mode regardless the magnitude of the input voltage.

[0028] The first transistor T1 1 of the first transistor unit T1 is an N-MOS transistor that is controlled to a conducting mode when receiving a high voltage control signal compared to the voltage on the input side. The second transistor T12 is P-MOS transistor that opens in response to high potential voltage difference between its control signal (gate) and output side (source), hence when it receives a low control signal compared to the potential on its output side. When the first transistor T1 1 is controlled to a conducting mode by a high voltage control signal it will transmit the low potential signal from the negative output terminal 7 to control the second transistor T12 of the first transistor unit T1 to a conducting mode so as to connect the first input terminal 4 to the positive output terminal 6 over the first transistor unit T1 .

[0029] Depending on the resistance over the first resistor R1 , the turn-off time of the second transistor T12 may be a problem. A high resistance will yield a low current through the first resistor R1 to the output side of the second transistor T12, which will result in a slow turn-off time. On the other hand, a low resistance will yield a big current through the first resistor R1 , indeed speeding up the turn-off/rise time, but also costing energy. Further, the resistance may also be reflected on the effective resistance generated on the positive and negative output 6 and 7. [0030] The first and second embodiment cannot handle signals on the input 4 and 5 that are lower than the required potential difference to make the second transistors T12 and T22 conducting without losses.

[0031 ] A third embodiment is shown in figure 3 in which the first transistor unit T1 and the second transistor unit T2 each comprises a third transistor T13 and T23, respectively. The purpose of this third transistor T13,T23 is to minimise the turn-off time of the second transistor T12 of the first transistor unit T1 and of the second transistor T22 of the second transistor unit T2, respectively, without incurring energy losses. This is needed because the first and second resistor R1 and R2 limits the current to deplete the energy in the parasitic capacitors inside the second transistors T12 and T22 which yields a higher turn-off time. The third transistor T13,T23 is therefore arranged to cross-circuit the second transistor T12,T22 and to present a loss-free current path from their respective control signal input (gate) to the positive output terminal 6.

[0032] The first transistor T1 1 (T21 ), the second transistor T12 (T22) and the third transistor T13 (T23) of the first (second) transistor unit T1 (T2) are all controlled to the conducting mode at the same time and to the non-conducting mode at the same time, except for the following instants: For low voltages the second transistor T12 (T22) will not be in conducting mode, because the potential difference between the incoming terminals will not be big enough to put the the second transistor T12 (T22) in a conducting mode. However, the third transistor T13 (T23) will provide a loss-free path for the current at low voltages. For high voltages, on the other hand, the third transistor T13 (T23) will come into a nonconducting mode due to that the control signal from the polarity probe 8 will not be high enough to reach the required potential difference to set the first and third transistor T1 1 (T31 ) and T13 (T33) in a conducting mode. For such instances the second transistor T12 (T22) will provide a loss-free path. For voltages in between high and low, both the second transistor T12 (T22) and the third transistor T13 (T23) will be in conducting mode providing two parallel loss-free paths.

[0033] A fourth embodiment is shown in figure 4. This fourth embodiment is advantageous over the third embodiment in that the turn-off time of the second transistor T12 (T22) is minimised. This is achieved by a fourth transistor T14 and T24, respectively, of the first and second transistor unit T1 and T2, respectively. The fourth transistor T14 and T24 of each transistor unit is a P-MOS transistor and is controlled by an incoming control signal from between the second transistor T12 (T22) and the fourth transistor T14 (T24) of the respective other transistor unit T1 or T2. [0034] The fourth transistor T14 of first transistor unit T1 is arranged in parallel to the first resistor R1 of the first transistor unit T1 and the fourth transistor T24 of the second transistor unit T2 is arranged in parallel to the second resistor R2 of the second transistor unit T2. The fourth transistor T14 of the first transistor unit T1 is controlled by a control signal based on the voltage potential between the first transistor 21 and the second resistor R2 of the second transistor unit T2 and the fourth transistor T24 of the second transistor unit T2 is controlled by a control signal based on the voltage potential between the first transistor T1 1 and the first resistor R1 of the first transistor unit T1 .

[0035] In an exemplary instant the polarity of the incoming voltage switches between the input terminals such that the first input terminal 4 switches from low to high, e.g. from 0 to 10 volts, and the second input terminal 5 switches from high to low. In this exemplary instant the second transistor T22 of the second transistor unit T2 will remain open until its inherent capacitors has been discharged. The first transistor T1 1 of the first transistor unit T1 will receive a high control signal and be put in a conductive mode, and thereby provide a low control signal to the fourth transistor T24 of the second transistor unit T2, which will thereby be set into a conducting mode to provide an instant path to discharge said second transistor T22 of the second transistor unit T2.

[0036] Hence, the specific embodiment shown in figure 4 is a control system adapted to provide an instant and loss-free path unipolar current regardless of the incoming polarity, voltage level, or current level.

[0037] In figure 5 a fifth embodiment is shown, which is an alternative of the embodiment shown in figure 4.

[0038] In the fifth embodiment, the first transistor T1 1 of the first transistor unit T1 and the first resistor R1 of the first transistor unit T1 are connected in series between the second input terminal 5 and the positive output terminal 6. As in the fourth embodiment of figure 4, the first transistor T1 1 is a N-MOS transistor controlled between a conducting and nonconducting mode by the first output Out_A of the polarity probe 8. When in conducting mode, the first transistor T1 1 of the first transistor unit T1 according to the fifth embodiment connects the second input terminal 5 via the first resistor R1 to the positive output terminal 6 and to a control input of the second transistor T12, not via said first resistor R1 , to thereby transmit a low voltage to said control input of the second transistor T12. The second transistor T12 is a P-MOS transistor that is set in a conducting mode in response to a low control voltage and which, when in conducting mode, connects the first input terminal 4 to the positive output terminal 6. [0039] Correspondingly, in the fifth embodiment, the first transistor T21 of the second transistor unit T2 and the second resistor R2 of the second transistor unit T2 are connected in series between the first input terminal 4 and the positive output terminal 6. The first transistor T21 is a N-MOS transistor controlled between a conducting and non-conducting mode by the second output Out_B of the polarity probe 8. When in conducting mode, the first transistor T21 of the second transistor unit T2 according to the fifth embodiment connects the first input terminal 4 via the second resistor R2 to the positive output terminal 6 and to a control input of the second transistor T22, not via said second resistor R2, to thereby transmit a low voltage to said control input of the second transistor T22. The second transistor T22 is a P-MOS transistor that is set in in conducting mode in response to a low control voltage and which, when in conducting mode, connects the second input terminal 5 to the positive output terminal 6.

[0040] The inventive circuit may be used in a wide variety of applications of different voltages where it is desired to provide the same output polarity irrespective of the input polarity. The inventive circuit is applicable to polarity dependent electronic devices, such as e.g. transistor radios, household appliances or the like which are battery driven and the inventive circuit offers a flexibility in the provision of batteries which may be inserted with the poles in either direction, wherein the inventive circuit will make sure that a correct polarity is provided to the polarity dependent electronic device. Further however, the inventive circuit may be used in high power applications such as for exchangeable car, bus or train batteries, which by means of the inventive circuit may be provided with the poles in either direction, wherein the inventive circuit will make sure that a correct polarity is provided to the polarity dependent high power application.

[0041 ] Above, the invention has been described with reference to specific

embodiments. It is obvious to a person skilled in the art that other embodiments are possible within the scope of the following claims.