Technical field

[0001] The present invention is related to an electric power converter. In particular, the present invention is related to a multi-level electric power converter overcoming problems related to dead-time of the transistor switches at low current levels. Electric power converters according to the present invention are particularly suitable for use as amplifiers for driving gradient coils in Magnetic Resonance Imaging (MRI) systems.

Background art

[0002] Gradient coils in an MRI system provide a magnetic field that is used for performing imaging measurements. These gradient coils require a high voltage and high current that must be controlled. The voltage is typically on the order of 2000 V and above. The required peak current is on the order of 600 A and above. The quality and resolution of the image depend on how precisely the magnetic fields are controlled. Therefore, a high accuracy on the currents is required to prevent image artifacts

[0003] Gradient amplifiers in MRI-scanners drive the gradient coils that typically have an inductance of several hundred mH to 1 mH. The gradient amplifier is constructed to drive this gradient coil to specific magnetic fields and typically comprises switching elements arranged in so called switching legs, together forming an H-bridge. The switching elements can be formed of IGBT switches with anti-parallel diodes, or any other electronically controlled switch with a parallel diode can be used instead. The switches are controlled with a pulse width modulation (PWM) scheme suitable for an H- bridge (for example unipolar or bipolar PWM).

[0004] In addition to ramping the current up and down fast, the gradient amplifier needs to generate a bidirectional high voltage and current. Because of this high voltage and current, high power components are used limiting the switching frequency. In order to switch the required voltage and current with a high frequency, it is known from US 2017/0045596 to use cascaded H-bridges. This allows to distribute the power demand over the H-bridges. Furthermore, the effective switching frequency is increased as well as the number of switching levels. It is further known from US 2018/0231623 to couple two stacks of cascaded H bridge inverters in parallel through a coupled inductor.

[0005] However, the H-bridge topology experiences dead-time (or blanking time) effects. The dead-time is a time where both top switches and bottom switches (in other words: all switches of one leg) are commanded to be off. This dead-time is added to prevent short circuiting the voltage source (shoot through) during a transition and create margin for cross-conduction due to the turn-on and turn-off delays of the switches. Due to the required margins on the dead-time, there is a moment where both the top and bottom switch of a single switching leg are off. During this time, the output voltage of the H-bridge is determined by the sign of the current in each switching leg, as this determines which parallel diodes will conduct. This current dependent output voltage has a negative effect on the converter output signal quality. The effect also generates a dead-band in the response of the output voltage/current on a changing control signal, specifically at low load currents. When using multiple H-bridge cells, the effect of the dead-time becomes larger as each H-bridge cell requires a certain dead-time. Because of the dead band at low output currents, the output current is difficult to control, providing a poor output quality with a large error between the load current and the reference signal.

[0006] US 2017/00445596 describes to overcome dead-time effects by injecting a bias current in the centre of the switching legs of the H-bridge. The injected bias current forces the direction of the current through the switches at low output current levels, resulting in a well-defined switching transition at these low currents. Consequently, the dead-time effect is shifted to higher positive and negative load current, the effect is reduced and compensated by the controller. A drawback of this method is that it requires additional auxiliary circuits for each half H-bridge. This increases the complexity of the hardware, the number of components, the probability of component failure and the cost of the amplifier.

Summary of the invention

[0007] It is an aim of the invention to provide an electric power converter which has at least equal and advantageously improved performance over electric power converters of the prior art, in particular at low output current levels. It is an aim of the invention to achieve this equal or improved performance with less hardware and/or at lower cost.

[0008] According to a first aspect of the invention, there is therefore provided an electric power converter as set out in the appended claims.

[0009] Electric power converters according to the invention comprise a first stack. The first stack comprises a plurality of controllable power switches arranged in one or more first H-bridges which are cascaded in series. The one or more first H-bridges can be at least one full H-bridge or a plurality of half H-bridges, or a combination of both.

[0010] According to the invention, the electric power converter comprises a second stack. The second stack comprises a plurality of controllable power switches arranged in one or more second H-bridges which are cascaded in series. The one or more second H-bridges can be at least one full H-bridge or a plurality of half H-bridges, or a combination of both. According to the invention, the first stack and the second stack are parallel connected through an inductive component. The inductive component can be implemented in various ways. In one particularly advantageous way, the inductive component comprises at least one coupling inductor.

[0011] Electric power converters according to the invention allow for further reducing the dead-time effects compared to the converter of US 2017/00445596 in that it can shift the dead-time effects of the power switches to even higher output current levels, where operation is less problematic. Additionally, the improved operational performance is obtained with less hardware and hence a reduced hardware complexity, which also lowers manufacturing cost.

[0012] The electric power converter comprises a controller operably coupled to the plurality of controllable power switches of the first stack and of the second stack. The controller is configured to operate the first full and/or half H-bridges and the second full and/or half H-bridges in an interleaved manner. This further allows to increase the number of voltage levels and the effective switching frequency, reducing ripple the controller is configured to operate the plurality of controllable power switches of the first stack and of the second stack through a pulse width modulation (PWM) scheme defining a modulation parameter setting a common mode voltage level of the first stack and of the second stack. The way of interleaving applied in electric power converters of the present invention is hence configured to adapt a modulation parameter, such as a duty cycle, applied to the first stack and the second stack as described herein. The modulation parameter is applied to the pulse width modulation control signal to adjust an output voltage of each H-bridge.

[0013] According to the invention, the PWM scheme implements an offset selectively adapting the modulation parameter in PWM control signals of the first and second full and/or half H-bridges allowing for controlling a differential mode current flowing between the first stack and the second stack. The PWM scheme is configured to selectively adapt the modulation parameter by alternating addition and subtraction of the offset between first and second full and/or half H-bridges arranged at corresponding locations in the first stack and in the second stack. Such a PWM scheme allows to generate a nonzero circulating current at switching events of the switches of the full and/or half H-bridges. As a result, dead time effects are eliminated or at least reduced at switching events and an improved soft switching behaviour of the electric power converter is obtained. [0014] According to a second aspect of the invention, there is provided a gradient amplifier for a magnetic resonance imaging apparatus comprising the electric power converter according to the first aspect.

[0015] According to a third aspect of the invention, there is provided a magnetic resonance imaging apparatus comprising a gradient coil and an electric power converter according to the first aspect. The electric power converter is operably coupled to the gradient coil.

[0016] According to a fourth aspect of the invention, there is provided a method of operating an electric power converter, as set out in the appended claims.

[0017] Further advantageous aspects are set out herein below and in the dependent claims.

Brief description of the figures

[0018] Aspects of the invention will now be described in more detail with reference to the appended drawings, wherein same reference numerals illustrate same features and wherein:

[0019] Figure 1 represents a topology of an electric power converter according to the present invention;

[0020] Figure 2 represents the topology of a power stack that is used in the electric power converter of Fig. 1 ;

[0021] Figure 3 represents a first embodiment of inductive coupling between two parallel power stacks according to the present invention;

[0022] Figure 4 represents an equivalent electric circuit of the topology of

Fig. 3 for the common mode current;

[0023] Figure 5 represents an equivalent electric circuit of the topology of

Fig. 3 for the differential mode current;

[0024] Figure 6 represents a second embodiment of inductive coupling between two parallel power stacks according to the present invention;

[0025] Figure 7 represents an equivalent electric circuit of the topology of

Fig. 6 for the common mode current;

[0026] Figure 8 represents an equivalent electric circuit of the topology of

Fig. 6 for the differential mode current;

[0027] Figure 9 represents a third embodiment of inductive coupling between two parallel power stacks according to the present invention using a coupling inductor;

[0028] Figure 10 represents a layout of the coupling inductor used in Fig. 9 realized with the aid of a transformer; [0029] Figure 1 1 represents the equivalent circuit of the coupling inductor of Fig. 10;

[0030] Figure 12 represents an equivalent electric circuit of the topology of

Fig. 9 for the common mode current;

[0031] Figure 13 represents an equivalent electric circuit of the topology of

Fig. 9 for the differential mode current;

[0032] Figure 14 represents another topology of an electric power converter according to the present invention;

[0033] Figure 15 represents a block diagram of the electric power converter of Fig. 14;

[0034] Figure 16 represents a diagram of the control structure for controlling the electric power converters of the present invention;

[0035] Figure 17 represents a block diagram of the power stacks of the electric power converter of Fig. 14;

[0036] Figure 18 represents a first PWM scheme implementation of the electric power converter of Fig. 14, showing the voltage levels of the H-bridges of the two power stacks, the output voltage and the differential mode current circulating between the power stacks;

[0037] Figure 19 represents a second PWM scheme implementation of the electric power converter of Fig. 14, showing the voltage levels of the H-bridges of the two power stacks, the output voltage and the differential mode current circulating between the power stacks;

[0038] Figure 20 represents a graphic visualization of the soft switching regions for rising and falling edges of PWM pulses in relation to the modulation parameter d _com for three system architectures (prior art with and without bias current injection as described in the background art section above and the architecture according to the present invention) in steady state. For simplicity the pulse lengths are not drawn to scale with respect to d _com , only the rising and falling edges.

Description of embodiments

[0039] Referring to Fig. 1 , one possible topology of the electric power converter according to the present invention comprises a power stage 11 and an output filter 12 coupled between the power stage 11 and a load 9. The power stage 11 comprises a pair of power stacks 131 , 132.

[0040] Referring in more detail to Fig. 2, each power stack 131 , 132 of the power stage 11 of Fig. 1 comprises a plurality of H-bridges 15. Each H-bridge 15 comprises power switches S1 to S4, such as IGBT switches, arranged in two switching legs 151 , 152. Each switching leg comprises two power switches in series. Diodes D1 to D4 are coupled in antiparallel with the respective switches S1-S4. Alternatively, half H- bridges can be used instead of the full H-bridges 15. Each H-bridge 15 is connected to a voltage source 16, in particular a DC voltage source, advantageously an isolating DC- DC converter which provides a stable bus voltage v¾ _us . A capacitor buffer 161 is advantageously coupled parallel to the voltage source 16 to counter sudden power demands. The switches S1-S4 are advantageously controlled with a pulse width modulation scheme suitable for an H-bridge (for example unipolar or bipolar PWM), as will be explained further below.

[0041] Each H-bridge 15 can switch its output voltage v _snH between -V _bUS ,

0V and +V _bUS · The H-bridges 15 within a power stack are cascaded such that the outputs of the H-bridges are connected in series, between the output terminals 133 and 134. Cascading the H-bridges 15 within a single power stack 131 , 132 combines the outputs V _snHi...n of all the H-bridges to one output voltage v _sni , V _s m of the power stack 131 , 132 respectively. The power stack output voltage v _sni , V _s m has an output range from -nv _bus to +nv _bus with increments of V _bUS , where n is the number of cascaded H-bridges.

[0042] Referring back to Fig. 1 , the two power stacks 131 , 132 are coupled in parallel by means of an inductive component 14. Each stack is advantageously configured to supply half of the output power, so the power components required to obtain the output power can be equally divided over the two stacks. During operation, the power stacks can sometimes have a same output voltage and sometimes a voltage difference. A difference in output voltage between the two power stacks 131 , 132 causes a circulating current i _diff (differential mode current) to flow between the two power stacks. In order to generate a controlled current and maintain this during switching, the inductive component 14 added between the power stacks 131 , 132 will limit the current rise and fall in case of a voltage difference between the power stacks. In addition, the common mode current i _DM is maintained when there is no voltage difference applied.

[0043] The inductive component 14 can be implemented in various ways.

A first possible implementation is shown in Fig. 3. The inductive component comprises two inductors 141 , 142, coupled symmetrically between the respective power stack 131 , 132 and the output terminal 1 11. The equivalent electric circuits for the common mode current and the differential mode current are represented in Fig. 4 and Fig. 5 respectively.

[0044] A second possible implementation is represented in Fig. 6. The inductive component of Fig. 6 differs from the one of Fig. 3 in that a third inductor 140 is coupled in parallel to the inductors 141 and 142. By so doing, the inductance is reduced from a differential mode perspective. The equivalent electric circuits for the common mode current and the differential mode current are represented in Fig. 7 and Fig. 8 respectively.

[0045] A third possible implementation is represented in Fig. 9, wherein the inductive component 14 is a coupling inductor. A coupling inductor generally refers to a pair of magnetically coupled inductors 141 , 142 which have one terminal that is short circuited between one another. Fig. 10 shows a possible implementation of the coupling inductor by means of a transformer. The inductor 141 forms the primary winding and the inductor 142 forms the secondary winding which are magnetically coupled through the transformer core 148. One terminal 144 of the primary winding 141 and one terminal 146 of the secondary winding 142 are electrically connected to each other and to an output terminal 147. Fig. 1 1 shows the equivalent electric circuit of the coupling inductor of Fig. 10, wherein L refers to the inductance of the primary winding, advantageously identical to the inductance of the secondary winding, and M = /cVIT = k. L refers to the mutual inductance. The equivalent electric circuits for the common mode current and the differential mode current are represented in Fig. 12 and Fig. 13 respectively. In common mode only the leakage inductance L _ieak occurs, whereas in differential mode only the magnetizing inductance L _ma is seen by the differential current.

[0046] By coupling the two power stacks in parallel through the inductive component, a topology is obtained able to circulate current through the power stacks without influencing the output current or voltage. Therefore, when the output current i _DM must become low, the current i _diff is’’circulated” between the power stacks 131 and 132 guaranteeing a well-defined switching transition. In addition, the number of switching levels can almost be doubled to 4n +1 by taking the average of v _snl and v _sn2 .

[0047] The operation of the power stacks 131 , 132 is furthermore advantageously interleaved, resulting in doubling the effective switching frequency of the output voltage v _sn .

[0048] Referring to Fig. 14, an alternative power stage 21 is depicted which differs from power stage 11 of Fig. 1 in that a second inductive component 24 is added in the loop of power stack 131 and power stack 132. The inductive component 14 is coupled between the upper output terminals of the power stacks 131 , 132, whereas the second inductive component 24 is coupled between the lower output terminals of the power stacks. In contrast, in Fig. 1 , the lower output terminals of the power stacks 131 , 132 are connected to ground. Inductive components 14 and 24 can be identical.

[0049] The output voltage v _sn applied at the output terminals 110 - 11 1 of the power stages 11 and 21 is advantageously filtered by an output filter 12 before applying to the load 9. The output filter 12 can be a passive second order LC-low pass filter. This results in a smoothed output voltage v _out that is applied to the load 9.

[0050] Referring to Fig. 15, the electric power converter 10 comprises a controller 17. Controller 17 is operably connected to the H-bridges 15 of each power stack 131 , 132. The power switches S1-S4 of each H-bridge are advantageously controllable power switches, and their operation is controlled by controller 17, advantageously implementing a PWM scheme, in particular through a unipolar PWM scheme. The controller can further be coupled to the output filter 12, e.g. for measuring an output current and/or output voltage of the power stage 1 1 , 21. Alternatively, or in addition, a voltage and/or current sensor 171 can be provided at the output of the electric power converter, and coupled to the controller 17.

[0051] The electric power converter 10 can comprise an AC to DC converter 18 which is coupled to an external power supply for receiving power. The AC to DC converter supplies power to the isolating DC-DC converters 16.

[0052] Controller 17 advantageously operates the power switches of the H- bridges 15 so as to interleave the outputs of the power stacks 131 and 132. This increases the number of switching levels and the effective switching frequency.

[0053] Controller 17 advantageously implements a PWM scheme for operating the power switches S1-S4 of the H-bridges 15. The PWM scheme is advantageously based on a unipolar pulse width modulation. Each H-bridge 15 of the power stacks 131 , 132 advantageously has its own PWM carrier. These PWM carriers may have the same waveform, but be phase-shifted. One advantageous PWM scheme implements modulation parameters d _A and d _B for the power stacks 131 , 132 respectively. The modulation parameters can refer to a duty cycle of the PWM scheme. This means that the output voltage of the power stacks 131 , 132 can respectively be defined as V _H1 = d _A nv _bus and V _H2 = d _B nv _bus with v _bus the output voltage of the DC-DC converters 16 and n the number of cascaded H-bridges 15 within a power stack, with n being an even number or advantageously an odd number.

[0054] In one possible control implementation of controller 17, the power stacks 131 , 132 are regarded as voltage sources, e.g. as described above in the preceding paragraph, which are integrated in a state space model of the power stage and output filter. Such a state space model may have the modulation parameters d _A and d _B as inputs and the currents i _load and i _diff as defined in Fig. 1 as outputs. In an alternative control implementation, the modulation parameters are redefined as d _A = d- _co m + d _di ff and d _B = d _com - d _diff . It can be shown that by so doing the modulation parameter d _com can be used to control the output current j _ioad , whereas d _diff can be used to control the circulating current (differential mode current) i _diff .

[0055] Referring to Fig. 16, controller 17 can implement control scheme

170, comprising a feedback loop controller 173 for controlling a reference current i _ref that is to be applied to the load 9, e.g. based on sensing of j _ioad through e.g. sensor 171. The feedback loop controller 173 advantageously provides a reference value for d _com .

[0056] Advantageously, control scheme 170 comprises a second controller

174 for controlling the circulating current i _diff through adjustment of the modulation parameter d _diff . The second controller 174 is configured to ensure that i _diff stays within bounds, preventing damage to the power stacks and to the inductive components. The second controller can use a classic control strategy based on a measured and/or estimated value of the circulating current i _diff . By way of example, the second controller 174 can determine an ideal value for the circulating current i _diff and adapt the modulation parameter d _diff accordingly.

[0057] The reference values for modulation parameters d _com and d _diff output from controllers 173, 174 are fed to PWM module 175 which generates the PWM control signals that are applied to the power switches S1-S4 of the H-bridges 15 of power stacks 131 , 132.

[0058] Through modulation parameter d _com , the voltage level of the output voltage v _sn is adjusted. By way of example, the modulation parameter d _com can for example be set to vary between -1 and +1. This means, when d _com is set to 0, v _sn will be 0 as well; when d _com is set to 0.5, v _sn will be set to half the maximum output voltage, etc.

[0059] Advantageously, the PWM module 175 implements an offset d _offset to d _com for each of the H-bridges 15 allowing for controlling the circulating current (differential mode current) i _diff flowing between the two power stacks 131 and 132 in addition to, or in the alternative of the modulation parameter d _diff .

[0060] Advantageously, the offset parameter d _offset has a fixed value.

Advantageously, d _offset = 1/(2*n), where n is the number of cascaded h-bridges. This allows for a desired amount of interleaving taking place.

[0061] Alternatively, the value of d _offset can be variable, e.g. it can depend on the value of the modulation parameter d _com , or it can depend on the amplitude of the circulating current. Advantageously, the magnitude of the offset d _offset is dependent on the modulation parameter d _com . By way of example, the offset d _offset is selected such that the sum of d _com and d _offset will never exceed 1 in absolute value. This is particularly relevant at the boundaries of d _com , e.g. in proximity of the range limits +1 and -1. At the range limits of d _com , e.g. at d _com = +1 and -1 , the offset d _offset is advantageously zero. By way of example, d _offset can have a constant value x while d _com is between -1+x and +1-x, and gradually decrease towards 0 in the d _com - range between -1 and -1 +x, and between +1-x and +1 , so that the sum of the two never exceeds 1 in absolute value. Advantageously, x= 1/(2*n), as defined above, allowing for doubling the effective switching frequency.

[0062] The value (magnitude) of d _offset can also be made to change between the H-bridges arranged at corresponding locations in the two power stacks 131 and 132 (referred to as an H-bridge pair), i.e. a different offset (in magnitude) is applied to the two H-bridges within an H-bridge pair. Alternatively, or in addition, the value (magnitude) of d _offset can also be made to change between the H-bridges of a same power stack 131 , 132.

[0063] Advantageously, the offset d _offset is applied to d _com in a time- varying manner. Advantageously, the offset d _offset is applied to corresponding H- bridges of the two power stacks 131 , 132 in an inversed way, in particular by adding d ₀ ff _set ^to d _com for one H-bridge and subtracting d _offset from d _com for the corresponding H-bridge of the other power stack. To this end, advantageously, each of the two power stacks comprises an equal and advantageously odd number of cascaded H-bridges. Alternatively, the offset d _offset can be applied to each H-bridge 15 depending on the PWM carrier wave. During ramp up of the PWM carrier wave, the offset d _offset can be positive, whereas the offset d _offset can be negative, though possibly equal in magnitude, during ramp down of the PWM carrier wave of the respective H-bridge.

[0064] In one example implementation, corresponding H-bridges 15 between the two power stacks 131 and 132 are considered to form H-bridge pairs as seen in Fig. 17. The H-bridges are schematically drawn as sources V _H11 - V _Hln for the first power stack 131 and V _H21 - V _H2n for the second power stack 132. The first H-bridges V _H11 and V _H21 are considered as a first pair, the second H-bridges V _H12 and V _H22 are considered as a second pair, etc. The offset d _offset is advantageously applied to each pair ( V _H11 , V _H21 ), ( V _H12 , V _H22 ),..., ( V _H1n , V _H2n ), in a complementary manner. By way of example, for V _H11 the offset d _offset is added to d _com , whereas in the other H-bridge V _H21 of the pair the offset d _offset is subtracted from d _com . Hence the resulting modulation parameter applied to V _H11 : d _VH11 = d _com + d _offset , and the resulting modulation parameter applied to V _H21 : d _VH21 = d _com - d _ofiset . Additionally, the offset d _offset is advantageously alternated between the different H-bridge pairs. Yet additionally, the offset is advantageously alternated between the H-bridges within a same pair after each cycle. This can be obtained when the PWM carrier waves are properly interleaved between H-bridges of a pair, such as when identical PWM carrier waves are used which are phase shifted by 180° between H-bridges of a pair, and the offset d _offset is positive or negative depending on whether the PWM carrier wave ramps up or down, respectively.

[0065] Figs. 18 and 19 show the outputs of the different H-bridges and resulting circulating current for two example implementations of the present invention. In Fig. 18, n 5, d _com 0 and d _offset 0.1. In Fig. 19, n 5, d _com 0.05 and d _offset 0.1. It can be seen from Fig. 18 that no voltage is applied on v _sn , while there is a circulating current i _diff which is circulated between the stacks. In Fig. 19 it can be seen that the effective switching frequency of v _sn is doubled with respect to the effective switching frequency of v _snl and v _sn2 , while there is a voltage ripple on v _sn equal to half the bus voltage.

[0066] One main advantage of the present invention now becomes clear from the figures. It can be seen from Figs. 18 and 19 that the circulating current (differential mode current) i _diff is large at low output voltage level. Furthermore, the circulating current i _diff is nonzero at the switching instants of the bridges. The switching instants are represented by the vertical dashed lines in Figs. 18 and 19 and it can be seen that these dashed lines intersect i _diff at a nonzero value. As a result, dead time effects are eliminated or at least reduced, in particular at low values of the output current. This allows to have a well-defined soft switching behaviour at these low output current levels. Another effect of the PWM scheme of the present invention is visible in Fig. 18 and 19, namely that i _diff is negative at rising slope of v _diff , and positive at falling slope

°f ^v diff-

[0067] The amplitude of the circulating current can further be influenced by the inductance L _ma of the coupling inductor. By appropriate choice of the inductance L _ma it can be obtained that the circulating current is large enough when the modulation parameter d _com is zero.

[0068] Applying the offset d _offset may render use of the modulation parameter d _diff superfluous, and this modulation parameter may not be implemented. Alternatively, the modulation parameter d _diff is advantageously set to 0 under‘normal’ operation conditions and adjusted only when a fault condition occurs, in particular when the circulating current drifts away during dynamic behaviour, e.g. an average value of the circulating current i _diff exceeds a predetermined threshold. The modulation parameter d _diff can be adapted to bring the average circulating current back to zero.

[0069] By implementing a PWM scheme as above, it was observed that well defined soft switching transitions occur, even when the modulation parameter d _com is 0 (see Fig. 18). Furthermore, the electric power converters of the present invention allow for reducing ripple on the output current and voltage due to the increase in effective switching frequency and the creation of additional switching levels due to the cascaded dual power stack topology.

[0070] Referring to Fig. 20, the soft switching behaviour of the PWM schemes according to the present invention is visually represented in comparison to two prior power converter art architectures: a first one, named Original’ is as described in US 2017/0045596 but without bias current injection, and a second one, named Original + BCI’ with bias current injection as described in US 2017/0045596. It can be seen that the well-defined soft switching behaviour occurs in a much wider output current range as the prior art architectures, but particularly, there is a well-defined soft switching of both rising and falling edge in the presently proposed PWM scheme at low output currents.

[0071] It will be convenient to note that the present invention contemplates electric power converters comprising more than two stacks which are coupled in parallel through inductive components, such as coupling inductors. In such case, the inductive component can comprise an inductive element for each of the stacks, and these inductive elements are inductively coupled with one another.