ELECTROMAGNETIC DELAY LINE INDUCTANCE ELEMENT

Title:

ELECTROMAGNETIC DELAY LINE INDUCTANCE ELEMENT

Document Type and Number:

WIPO Patent Application WO/2005/041406

Kind Code:

A1

Abstract:

[PROBLEMS] To provide an electromagnetic delay line inductance element which can be reduced in size like a chip shape, obtain a preferable coupling state, and easily obtain a desired delay characteristic. [MEANS FOR SOLVING THE PROBLEMS] Four inductors of spiral shape L0B, L2A, L2B, L4A are formed on one side of a first insulating substrate (15). The inductors L2A and L2B are connected in series. Four inductors of spiral shape L1A, L1B, L3A, L3B are formed on one side of a second insulating substrate (29). The inductors L1A and L1B are connected in series while the inductors L3A and L3B are connected in series. The first and the second insulating substrate (15, 29) are superimposed on each other so that the inductor L0B faces the inductor L1A, the inductor L1B faces the inductor L2A, the inductor L2B faces the inductor L3A, the inductor L3B faces the inductor L3A, and the inductor L3B faces the inductor L4A and they are respectively connected in series of positive connection. Each of the pairs of the inductors L1A and L1B, the inductors L2A and L2B, and the inductors L3A and L3B constitutes one-section inductor.

Inventors:

KAMEYA KAZUO (JP)

Application Number:

PCT/JP2004/015225

Publication Date:

May 06, 2005

Filing Date:

October 15, 2004

Export Citation:

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Assignee:

ELMEC CORP (JP)
KAMEYA KAZUO (JP)

International Classes:

H03H7/34; H01F17/00; (IPC1-7): H03H7/32; H01F17/00; H01F27/00

Foreign References:

JPS62173816U	1987-11-05
JPS5438860B2	1979-11-24
JPH06216689A	1994-08-05
JP2001036372A	2001-02-09