Title:
Electronic Assembly for Prognostics of Solder Joint
Document Type and Number:
WIPO Patent Application WO/2015/001583
Kind Code:
A1
Abstract:
The problem to be solved by the present invention is to provide a substrate for providing early warning of degradation in a semiconductor device. The problem is solved by providing a substrate comprising an actual device comprising a semiconductor component and a solder joint, and a dummy device closely placed to the actual device on the substrate and connected electrically in parallel circuit to the actual device, comprising a dummy semiconductor component and a solder joint comprising an outer solder joint part and an inner solder joint part, wherein the outer solder joint part has same characteristic to the solder joint of the actual device and the inner solder joint part accelerates the crack growth faster than the outer solder joint, and percentage area of outer solder joint part is smaller than the predetermined failure criterion of delamination percentage in actual device corresponding to the threshold value of electrical change.
Inventors:
DIGUNA LINA JAYA (JP)
OKAMOTO MASAHIDE (JP)
TAMAKI KENJI (JP)
OKAMOTO MASAHIDE (JP)
TAMAKI KENJI (JP)
Application Number:
PCT/JP2013/004081
Publication Date:
January 08, 2015
Filing Date:
July 01, 2013
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
G01R31/28; H01L21/52
Foreign References:
| JP2011209199A | 2011-10-20 | |||
| JP2008277457A | 2008-11-13 | |||
| JP2002122640A | 2002-04-26 |
Attorney, Agent or Firm:
TSUTSUI, Yamato (3F Shinjuku Gyoen Bldg., 3-10, Shinjuku 2-chome, Shinjuku-k, Tokyo 22, JP)
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