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Title:
ELECTRONIC COMPONENT MOUNTING METHOD, ELECTRONIC COMPONENT MOUNTING SYSTEM, AND SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2012/133760
Kind Code:
A1
Abstract:
Provided is a mounting technology of more easily mounting a plurality of electronic components on a substrate by planarly disposing the electronic components on the substrate. On a substrate (WA), a plurality of chips (CPi) of an ith layer are planarly disposed and laminated. When value i=2, firstly, a plurality of chips (CP2) of a second layer are planarly disposed in a face-up state, and temporarily fixed on a resin layer (RS2) formed on a temporary substrate (WT2). Then, the upper side and the lower side of the temporary substrate (WT2) are inverted, and the chips (CP2) of the second layer are held on the temporary substrate (WT2) in a face-down state. Each of the chips (CP2) of the second layer and each of the chips (CP1) of the first layer on the substrate (WA) are brought relatively close to each other by bringing the substrate (WA) and the temporary substrate (WT2) relatively close to each other, and the each of the chips (CP1) and each of the chips (CP2) are bonded to each other. Furthermore, the temporary substrate (WT2) is separated from the chips (CP2) of the second layer, while maintaining the state wherein each of the chips (CP2) is bonded to each of the chips (CP1).

Inventors:
YAMAUCHI AKIRA (JP)
Application Number:
PCT/JP2012/058567
Publication Date:
October 04, 2012
Filing Date:
March 30, 2012
Export Citation:
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Assignee:
BONDTECH CO LTD (JP)
YAMAUCHI AKIRA (JP)
International Classes:
H01L25/10; H01L25/065; H01L25/07; H01L25/11; H01L25/18
Domestic Patent References:
WO2006077739A12006-07-27
Foreign References:
JP2003209140A2003-07-25
JP2003218507A2003-07-31
JP2003204031A2003-07-18
JP2002299546A2002-10-11
JP2008227527A2008-09-25
JP2010219101A2010-09-30
JP2008182008A2008-08-07
JP2008218488A2008-09-18
JPH11274241A1999-10-08
Attorney, Agent or Firm:
NAKASHIMA, Ryou (JP)
Nakajima δΊ† (JP)
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