ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING AND MOUNTING THEREOF, AND CIRCUIT BOARD AND ELECTRONIC EQUIPMENT

WIPO Patent Application WO/1998/025297

A1

A semiconductor device whose package size is nearly the same as the size of a chip, which has a stress absorbing layer, which does not require a flexible substrate, and which can be manufactured in a large number at the same time. A method for manufacturing a semiconductor device includes a process wherein electrodes (12) are formed on a wafer (10), a process wherein a resin layer (14) is formed as a stress reducing layer on the wafer (10) except for the parts where the electrodes (12) are formed, a process wherein a chrome layer (16) is formed as an interconnect on the whole surface of the wafer (10) including the electrodes (12) and the resin layer (14), a process wherein solder balls are formed as external electrodes on parts of the chrome layer (16) which are formed on the resin layer (14), and a process wherein the wafer (10) is diced to semiconductor chips. In the processes for forming the chrome layer (16) and for forming the solder balls, a metal thin film deposition technology used in the wafer process of semiconductor manufacturing is employed.

HASHIMOTO NOBUAKI (JP)

PCT/JP1997/004437

June 11, 1998

December 04, 1997

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SEIKO EPSON CORP (JP)
HASHIMOTO NOBUAKI (JP)

H01L21/44; H01L21/48; H01L21/50; H01L21/60; H01L21/768; H01L23/31; H01L23/36; H01L23/485; H01L23/532; (IPC1-7): H01L21/3205; H01L21/60

JPS641257A	1989-01-05
JPH0263127A	1990-03-02
JPH03198342A	1991-08-29
JPH05291262A	1993-11-05
JPH0410429A	1992-01-14
JPH05226416A	1993-09-03
JPH0677283A	1994-03-18

Inoue, Hajime (2nd floor 26-13, Ogikubo 5-chom, Suginami-ku Tokyo 167, JP)

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