DESCRIPTION The invention relates to an electronic device comprising a carrier and a semiconductor chip. The invention further relates to a method for producing an electronic device.

The present patent application claims the priority of German patent application DE 10 2016 115 224.2, the disclosure con ^¬ tent of which is hereby incorporated by reference.

An electronic device may be realized in the form of a so- called chip-on-board module (COB) which comprises a carrier and one or several semiconductor chips arranged on the carri ^¬ er. An optoelectronic device for generating light radiation configured in this way may comprise radiation-emitting semi ^¬ conductor chips such as LED chips (light emitting diode) . Common COB devices comprise solder pads to which wires may be connected by means of soldering for electrical contacting. Another approach consists in using a secondary housing with mechanical contact structures. This approach is however asso ^¬ ciated with higher costs.

With respect to a COB device with solder pads, drawbacks may arise, as well. This is because the carrier may be designed in such a way that heat generated during operation of the electronic device may be efficiently removed. Using such a carrier therefore has the effect that a removal of heat also appears during a COB soldering process. As a consequence, it is difficult to provide and maintain an appropriate tempera ^¬ ture for the soldering in the area of the solder pads, thus making it difficult to control the soldering process and the achievable soldering quality.

For this reason, the soldering process is usually not con ^¬ ducted in an automated manner but instead in a manual way, wherein an operator with good skills is preferred for carrying out the soldering. Nevertheless, the soldering quality may be poor so that issues regarding the solder joint relia ^¬ bility may arise. It is for example possible that a solder joint comprises a void and/or is insecure.

In order to overcome these problems, a conventional approach consists in applying a hot plate for a COB soldering process so that an appropriate soldering temperature may be provided and maintained. This approach is however time-consuming.

It is an object of the present invention to provide an im ^¬ proved electronic device to which a wire may be connected by means of soldering without the above-identified problems. It is a further object of the present invention to provide a method for producing such an electronic device.

These objects are achieved by the features of the independent claims. Further preferred embodiments are disclosed in the dependent claims.

According to an aspect of the invention, an electronic device comprising a carrier and a semiconductor chip is provided. The carrier comprises a first dielectric layer and a second dielectric layer. A thermal conductivity of the first dielec ^¬ tric layer exceeds a thermal conductivity of the second die ^¬ lectric layer. The difference between the thermal conductivi ^¬ ties of the first and the second dielectric layer may be 5% or 10 % or more. The second dielectric layer is arranged on the first dielectric layer and partially covers the first di ^¬ electric layer. The first and/or the second dielectric layer are deposited by a printing process. Therefore the forming of the first and/or the second dielectric layer is fast and pro ^¬ vides sufficient quality for the first and/or the second die- lectric layer. The semiconductor chip is arranged on the carrier in a mounting area. The carrier comprises a solder terminal for electrical contacting. The solder terminal is ar ^¬ ranged on the second dielectric layer. The electronic device may be a so-called chip-on-board module (COB) . The electronic device comprises a carrier with a first and a second dielectric layer. The two dielectric layers com- prise different thermal conductivities. This configuration makes it possible to provide an effective removal of heat during operation of the electronic device as well as to pro ^¬ mote and enhance a soldering process carried out in order to contact the electronic device.

In this context, a semiconductor chip is arranged on the car ^¬ rier in a mounting area. The mounting area may be free of the first and second dielectric layer or in the mounting area the first dielectric layer may not be covered by the second die- lectric layer. Consequently, heat produced during operation of the semiconductor chip may be efficiently conducted away from the semiconductor chip via the first dielectric layer.

For the purpose of electrical contacting, the carrier com- prises a solder terminal to which a wire may be connected by means of soldering. The solder terminal is arranged on the second dielectric layer with the lower thermal conductivity. This makes it possible to reliably provide and maintain an appropriate soldering temperature in the area of the solder terminal because a removal of heat may be suppressed or, re ^¬ spectively, reduced in this area. Consequently, the soldering process may be carried out with a high process quality, and a reliable and stable solder joint may be formed. This has the effect that the yield and also the efficiency when operating the electronic device may be improved. The high soldering quality makes it furthermore possible to conduct the solder ^¬ ing process in an automated and therefore cost-efficient man ^¬ ner. Moreover, the application of a hot plate may be avoided. In the following, further possible embodiments of the elec ^¬ tronic device are described.

Each of the two dielectric layers may comprise or, respec ^¬ tively, be made of a respective dielectric material. An exam- pie is a composite material such as a resin based composite material .

In a further embodiment, the first electric layer has a thickness that is smaller than a thickness of the second die ^¬ lectric layer. Therefore, the stack of the dielectric layers has a small height with sufficient thermal blocking during the soldering process. In a further embodiment, the first dielectric layer has a thickness smaller than 25 ym, especially a thickness between 5ym and 15ym. The thickness is selected such that the first dielectric layer provides a sufficient voltage breakdown and also provides a good heat transfer to the base layer thermal.

In a further embodiment, the second dielectric layer has a thickness smaller than 50ym, especially a thickness between 10 ym and 40 ym. The thickness of the second dielectric layer is selected such that a sufficient heat isolation is at- tained.

In a further embodiment, the first and/or the second dielec ^¬ tric layer is embodied as a stack of at least two printed layers .

In a further embodiment of the electronic device, the second dielectric layer comprises an opening by means of which the mounting area is provided. This embodiment allows for a sym ^¬ metric configuration of the electronic device in which the opening and therefore the mounting area may be located cen ^¬ trally on the carrier.

In a further embodiment of the electronic device, the carrier comprises a metal base layer on which the first dielectric layer is arranged. In this way, the removal of heat during operation of the electronic device may be promoted because the metal base layer may act as a heat sink. Moreover, it is possible to arrange the electronic device or, respectively, the metal base layer of the carrier on an additional heat sink so that a heat transfer from the metal base layer to the additional heat sink may occur, thus further promoting the removal of heat during operation of the electronic device. The carrier comprising the metal base layer may be a so- called metal core printed circuit board (MCPCB) . The metal base layer may for example be an aluminum layer.

With regard to the solder terminal of the carrier, the fol- lowing embodiments may be considered. The solder terminal may be configured in the form of a layer or, respectively, solder pad. The solder terminal may comprise a metal such as copper. The solder terminal may furthermore comprise a metallic plat ^¬ ing .

In a further embodiment of the electronic device, the carrier comprises a contact layer arranged on the second dielectric layer and a covering layer arranged on the contact layer and partially covering the contact layer. The solder terminal is provided by a region of the contact layer which is not cov ^¬ ered by the covering layer. By means of the covering layer, an impairment of the contact layer such as corrosion may be suppressed. The covering layer may comprise an insulating ma ^¬ terial, and may constitute a solder mask located on the car- rier. The contact layer may comprise a metal such as copper. In the region which constitutes the solder terminal, the con ^¬ tact layer may additionally comprise a metallic plating.

The contact layer may comprise a further region which is not covered by the covering layer, and which may provide a con ^¬ tact area. An electrical connection structure such as a bond wire may be attached to the contact area and to the semicon ^¬ ductor chip. In this way, the semiconductor chip may be electrically connected to the solder terminal. In the region which constitutes the contact area, the contact layer may ad ^¬ ditionally comprise a metallic plating, as well. In another embodiment of the electronic device, the carrier comprises a further solder terminal arranged on the second dielectric layer for electrical contacting. In this way, the carrier may comprise two solder terminals arranged on the second dielectric layer to which wires may be connected by means of soldering. The arrangement of the two solder termi ^¬ nals on the second dielectric layer with the lower thermal conductivity makes it possible to provide and maintain an ap ^¬ propriate soldering temperature in the area of the solder terminals.

The two solder terminals may constitute a cathode terminal and an anode terminal of the electronic device, thus making it possible to supply electrical energy to the electronic de- vice for operating the same. The above-described embodiments relating to a solder terminal may correspondingly apply to the configuration with two solder terminals.

Accordingly, the two solder terminals may each be realized in the form of a solder pad. The carrier may comprise two sepa ^¬ rate contact layers arranged on the second dielectric layer. The carrier may either comprise a common covering layer or two separate covering layers assigned to the two contact lay ^¬ ers by means of which the two contact layers are partially covered. The two solder terminals may be provided by respec ^¬ tive regions of the two contact layers not covered by the covering layer (s) . Moreover, two contact areas may be provid ^¬ ed by further regions of the two contact layers not covered by the covering layer (s) . In the regions which constitute the solder terminals and the further regions which constitute the contact areas, the contact layers may comprise a metallic plating. Electrical connection structures such as bond wires may be attached to the two contact areas and to the semicon ^¬ ductor chip. In this way, the semiconductor chip may be elec- trically connected to the two contact areas. In a further embodiment, the electronic device is an optoe ^¬ lectronic device. In an embodiment like this, the semiconduc ^¬ tor chip is an optoelectronic semiconductor chip. It is furthermore possible that the electronic device is an optoelectronic device for generating light radiation. For this purpose, a radiation-emitting or, respectively, light- emitting semiconductor chip may be applied. In this regard, the above-mentioned mounting pad on which the semiconductor chip may be arranged may additionally provide an efficient reflection of light. The radiation-emitting semiconductor chip may for example be a LED chip (light emitting diode) . In this way, the electronic device may be a LED COB module. The semiconductor chip arranged on the carrier may be an un- packaged chip or, respectively, a bare die. The semiconductor chip may furthermore comprise two front-side contacts to which bond wires may be connected. Apart from the above-described components, the electronic de ^¬ vice may comprise further components. As an example, the car ^¬ rier may comprise a frame structure enclosing the mounting area, and the area enclosed by the frame structure may be filled up with an encapsulation or, respectively, embedding material. In this way, the semiconductor chip or the several semiconductor chips may be encapsulated.

The embedding material may be a transparent material. Alter ^¬ natively, the embedding material may comprise a transparent material and embedded conversion particles for at least par ^¬ tially converting light radiation generated by the semiconductor chip(s) . It is also possible that the semiconductor chip(s) comprise (s) a conversion layer for at least partially converting light radiation.

A further aspect of the invention relates to a method for producing an electronic device. The electronic device is con ^¬ figured as described above or, respectively, according to one or several of the above-described embodiments. In the method, a first dielectric layer and a second dielectric layer are provided. The first and/or the second electric layer are formed by a printing process. The printing process may be a screen printing process, a gravure printing process, a print ^¬ ing process with a flexible printing plate or an inkjet printing process for example.

A thermal conductivity of the first dielectric layer exceeds a thermal conductivity of the second dielectric layer for ex ^¬ ample more than 5%. The second dielectric layer is arranged on the first dielectric layer so that a carrier is produced, wherein the carrier comprises a mounting area in which the first dielectric layer is not covered by the second dielec- trie layer. The method further comprises providing a solder terminal arranged on the second dielectric layer, and arrang ^¬ ing a semiconductor chip on the carrier in the mounting area.

In the method, the above-mentioned steps may be carried out in the indicated order. The electronic device produced ac ^¬ cording to the method may provide an effective removal of heat during operation and may be reliably contacted by means of soldering. In this regard, the semiconductor chip is arranged on the carrier in the mounting area in which the first dielectric layer with the higher thermal conductivity is not covered by the second dielectric layer. Consequently, heat produced during operation of the semiconductor chip may be efficiently transferred away from the semiconductor chip via the first dielectric layer. The solder terminal to which a wire may be connected by means of soldering is arranged on the second dielectric layer with the lower thermal conductiv ^¬ ity. This makes it possible to provide and maintain an appro ^¬ priate soldering temperature in the area of the solder termi ^¬ nal. As a consequence, the soldering process may be carried out with a high soldering quality, and therefore in an auto ^¬ mated and cost-efficient manner. In the following, further possible embodiments of the produc ^¬ tion method are described. In this regard, it is pointed out that features and details described above with respect to the electronic device and its diverse embodiments may also apply to the method.

In an embodiment, the method further comprises forming an opening in the second dielectric layer by means of which the mounting area of the carrier is provided. For this purpose, a punching or, respectively, blanking process may be carried out. Forming the opening may be carried out before arranging the second dielectric layer on the first dielectric layer.

In a further embodiment of the method, the first dielectric layer is provided with a metallic layer arranged on the first dielectric layer. The metallic layer is structured so that a mounting pad arranged on the first dielectric layer is pro ^¬ vided. Furthermore, the semiconductor chip is arranged on the mounting pad. By means of the mounting pad, the semiconductor chip may be reliably attached to the carrier, and heat pro ^¬ duced when operating the semiconductor chip may be efficiently transferred from the semiconductor chip to the first die ^¬ lectric layer. Structuring the metallic layer located on the first dielec ^¬ tric layer in order to provide the mounting pad may be car ^¬ ried out before arranging the second dielectric layer on the first dielectric layer. In this respect, arranging the second dielectric layer on the first dielectric layer may be carried out in such a way that the mounting pad is not covered by the second dielectric layer. For the case that an opening is formed in the second dielectric layer as described above, the second dielectric layer may be arranged on the first dielec ^¬ tric layer in such a way that the mounting pad is located within the opening. The metallic layer arranged on the first dielectric layer may for example be a copper layer. It is furthermore possible to carry out a plating process, for ex ^¬ ample after arranging the second dielectric layer on the first dielectric layer. In this way, the mounting pad may be additionally provided with a metallic plating.

In a further embodiment of the method, the first dielectric layer is provided with a metal base layer on which the first dielectric layer is arranged. The metal base layer may act as a heat sink of the produced electronic device. It is further ^¬ more possible to arrange the electronic device or, respec ^¬ tively, the metal base layer of the same on an additional heat sink.

In a further embodiment of the method, the second dielectric layer is provided with a metallic layer arranged on the sec ^¬ ond dielectric layer. The metallic layer is structured so that a contact layer arranged on the second dielectric layer is provided. Moreover, a covering layer is formed which partially covers the contact layer so that the solder terminal is provided by a region of the contact layer which is not covered by the covering layer. By means of the covering lay- er, an impairment of the contact layer like for example cor ^¬ rosion may be suppressed.

For the case that an opening is formed in the second dielec ^¬ tric layer as described above, the opening may be also formed in the metallic layer arranged on the second dielectric lay ^¬ er .

The semiconductor chip may be electrically connected to the solder terminal in a suitable manner. In this respect, the covering layer may be formed in such a way that the contact layer comprises a further region which is not covered by the covering layer, and which may provide a contact area. Fur ^¬ thermore, a step of establishing an electrical connection be ^¬ tween the contact area and the semiconductor chip may be car- ried out. This may for example be realized by performing a wire bonding process in which a bond wire is applied and at ^¬ tached to the contact area and to the semiconductor chip. Structuring the metallic layer located on the second dielec ^¬ tric layer in order to provide the contact layer may be car ^¬ ried out before arranging the second dielectric layer on the first dielectric layer. Forming the covering layer may be carried out after arranging the second dielectric layer on the first dielectric layer. The metallic layer and thus the contact layer may for example be a copper layer. By means of the above-mentioned plating process, which may be carried out after arranging the second dielectric layer on the first die- lectric layer or, respectively, after forming the covering layer, it is furthermore possible to additionally provide the solder terminal and the contact area with a metallic plating.

In another embodiment of the method, a further solder termi- nal arranged on the second dielectric layer is provided. Con ^¬ sequently, the carrier of the electronic device produced in the method may comprise two solder terminals arranged on the second dielectric layer to which wires may be connected by means of soldering. The two solder terminals may constitute a cathode terminal and an anode terminal of the electronic de ^¬ vice .

Embodiments described above and relating to a solder terminal may correspondingly apply to the two solder terminals. Ac- cordingly, the second dielectric layer may be provided with a metallic layer arranged on the second dielectric layer, and the metallic layer may be structured so that two separate contact layers arranged on the second dielectric layer may be provided. By forming a common covering layer or two separate covering layers which partially cover (s) the two contact lay ^¬ ers, two solder terminals may be provided by respective un ^¬ covered regions of the contact layers. Moreover, two contact areas may be provided by other respective uncovered regions of the two contact layers. By means of the above-mentioned plating process, which may be carried out after forming the covering layer (s), the solder terminals and the contact areas may be additionally provided with a metallic plating. Fur ^¬ thermore, electrical connection structures such as bond wires may be attached to the two contact areas and to the semicon ^¬ ductor chip.

In a further embodiment, the electronic device produced in the method is an optoelectronic device, for example an optoe ^¬ lectronic device for generating light radiation. With respect to this, the semiconductor chip may correspondingly be an optoelectronic semiconductor chip or, respectively, a radia ^¬ tion-emitting semiconductor chip such as a LED chip.

It is furthermore possible to arrange several semiconductor chips, for example radiation-emitting semiconductor chips, on the carrier in the mounting area. In this regard, a mounting pad may be provided by structuring a metallic layer arranged on the first dielectric layer as described above, and the several semiconductor chips may be arranged on the mounting pad. It is also possible to structure a metallic layer ar ^¬ ranged on the first dielectric layer in such a way that sev ^¬ eral separate mounting pads are provided, and to arrange the several semiconductor chips on the several mounting pads. By carrying out a plating process, the mounting pad(s) may be additionally provided with a metallic plating. Moreover, two partially covered contact layers and therefore two solder terminals and two contact areas may be formed on the second dielectric layer and provided with a metallic plating as de ^¬ scribed above, and electrical connection structures such as bond wires may be attached to the two contact areas and to the semiconductor chips. The production method may comprise further method steps. It is for example possible to form a frame structure enclosing the mounting area on the carrier, and to fill up the area enclosed by the frame structure with an encapsulation or, re ^¬ spectively, embedding material. In this way, the semiconduc- tor chip or, respectively, the several semiconductor chips may be encapsulated. It is furthermore possible to carry out the method in such a way that an assemblage of several connected electronic devic ^¬ es is produced. Afterwards, the assemblage may be singular- ized into separate electronic devices. In this regard, layers and structures such as the first and the second dielectric layer, the solder terminals etc. may be provided and formed with dimensions and/or quantities matched with the several electronic devices to be produced. The configurations and features which are described above and/or which are disclosed in the dependent claims may be re ^¬ alized individually or in any combination, except for example cases of clear dependencies or contradicting alternatives. The accompanying schematic drawings are included in order to provide a further understanding of the present invention and are incorporated into and constitute a part of this specifi ^¬ cation. The drawings illustrate embodiments of the present invention and together with the description serve to explain principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they will be better understood by reference to the following detailed descrip ^¬ tion.

Figures 1 to 7 show the fabrication of a carrier of an electronic device, wherein the carrier comprises two dielectric layers with different thermal conductivities and two solder pads .

Figures 8 and 9 show the fabrication of an electronic device, wherein semiconductor chips are arranged on the carrier and an electrical wiring and an encapsulation are formed. Figure 10 shows the electronic device including wires con ^¬ nected to the solder pads. The following schematic figures serve to describe an elec ^¬ tronic device 100 and a corresponding method for producing the same. The electronic device 100 is realized in the form of a so-called chip-on-board module (COB) comprising a carri- er 105 and semiconductor chips 140 arranged on the same. The electronic device 100 may be an optoelectronic device for generating light radiation.

It is pointed out that the figures may not be true to scale. In this sense, components and structures shown in the figures may be scaled up or reduced in size in order to provide a better understanding.

Figures 1 to 9 show steps of a possible method for producing an electronic device 100. In the figures, the method is il ^¬ lustrated by means of sectional views. It is further pointed out that Figures 1 to 7 illustrate the fabrication of a re ^¬ spective carrier 105 of the electronic device 100, and that Figures 8 and 9 illustrate further processes carried out in order to fabricate the electronic device 100.

The method may be carried out in such a way that an assem ^¬ blage of several connected electronic devices 100 is produced and subsequently singularized into separate electronic devic- es 100. In this respect, it is pointed out that the figures may be regarded as showing conditions in the area of only one of the electronic devices 100 to be produced, and that the figures and the corresponding description may apply to all of the jointly produced electronic devices 100.

In the method, a first dielectric layer 110 or, respectively, a layer stack comprising the first dielectric layer 110 is printed as shown in Figure 1 on a base layer 112. Apart from the first dielectric layer 110, a metallic layer 114 is de- posited for example printed on the first dielectric layer 110. In the produced electronic device 100, the base layer 112 may act as a heat sink and may be embodied as a metal layer . The first dielectric layer 110 may comprise a dielectric ma ^¬ terial with a relatively high thermal conductivity. The ther ^¬ mal conductivity of the dielectric material of the first die- lectric layer 110 is higher than the thermal conductivity of a dielectric material of a second dielectric layer 120 also applied in the method, as described in more detail further below. The first dielectric layer 110 may for example com ^¬ prise epoxy material or silicone material filled with inor- ganic material or metal material. The inorganic material may for example be aluminum nitride. The metal material may be for example silver. Depending on the used embodiment also other materials may be used. The second dielectric layer 120 may comprise epoxy material or acrylic material or silicone material. Depending on the used embodiment also other materi ^¬ als may be used. The material for printing the first and/or the second dielectric layer may be in a liquid and/or pasty condition during the printing process. After printing the layer or layers a curing process is performed.

The metallic layer 114 located on the first dielectric layer 110 may for example be a copper layer. The metal base layer 112 may for example be an aluminum layer. As further shown in Figure 2, the metallic layer 114 is sub ^¬ sequently structured so that separate mounting pads 116 ar ^¬ ranged on the first dielectric layer 110 are provided. In a further embodiment, the separate mounting pads 116 may be printed on the first dielectric layer 110. Structuring the metallic layer 114 in order to form the mounting pads 116 may be carried out by means of an etching process in which an ap ^¬ propriate etching mask is applied (not depicted) .

On each of the mounting pads 116, a respective semiconductor chip 140 is arranged at a later stage of the fabrication method (see Figure 8) . Consequently, structuring the metallic layer 114 in order to form the mounting pads 116 is carried out in such a way that the number of the formed mounting pads 116 corresponds to the designated number of the semiconductor chips 140 provided for the electronic device 100. Apart from the two mounting pads 116 shown in the sectional view of Fig ^¬ ure 2, a different or, respectively, greater number of mount- ing pads 116 may be formed. The mounting pads 116 may be also referred to as die attach pads.

With respect to the fabrication of an assemblage of connected electronic devices 100, the layer stack shown in Figure 1 may be provided with appropriate lateral dimensions. Moreover, a respective number of mounting pads 116 may be formed for each of the jointly produced electronic devices 100 by structuring the metallic layer 114. The method furthermore comprises printing a second dielectric layer 120 or, respectively, printing a layer stack of second dielectric layers 120. Apart from the second dielectric layer 120, a metallic layer 124 is deposited for example printed on the second dielectric layer 120 as shown in Fig. 3.

The second dielectric layer 120 may comprise a dielectric ma ^¬ terial with a relatively low thermal conductivity. As indi ^¬ cated above, the thermal conductivity of the dielectric mate ^¬ rial of the second dielectric layer 120 is lower than the thermal conductivity of the dielectric material of the first dielectric layer 110. Similar to the first dielectric layer 110, the second dielectric layer 120 may for example comprise a resin-based composite material. The metallic layer 124 located on the second dielectric layer 120 may for example be a copper layer.

In a further method step, an opening 121 is formed in the second dielectric layer 120 or, respectively, in the layer stack comprising the second dielectric layer 120 and the me- tallic layer 124 as shown in Figure 4. The opening 121 may for example comprise a circular outline when viewed form above (not depicted) . In the produced carrier 105, the open ^¬ ing 121 provides a respective mounting area 107 for receiving and mounting semiconductor chips 140 (see Figures 7, 8) .

Forming the opening 121 may for example be carried out by means of a punching process. As further illustrated in Figure 5, the metallic layer 124 is subsequently structured so that two separate contact layers 125 arranged on the second dielectric layer 120 are provided. In a further embodiment, the two separate contact layers 125 may be printed on the second dielectric layer 120. By means of the contact layers 125, solder pads 126 and contact areas 127 are provided at a later stage of the production method (see Figure 7) . The contact layers 125 may, as the case may be, partially enclose the opening 121 when viewed from above (not depicted) . Structuring the metallic layer 124 in order to form the separate contact layers 125 may be carried out by means of an etching process in which an appropriate etching mask is applied (not depicted) .

With respect to the fabrication of an assemblage of connected electronic devices 100, the layer stack shown in Figure 3 may be provided with appropriate lateral dimensions. Moreover, punching and structuring the metallic layer 124 may be carried out in such a way that an opening 121 and two separate contact layers 125 are respectively formed for each of the jointly produced electronic devices 100.

It is pointed out that the above-described method steps car ^¬ ried out with respect to the second dielectric layer 120 may also be carried out in a reverse order. Consequently, it is possible to firstly form the contact layers 125 by structur ^¬ ing the metallic layer 124 and to subsequently form the open ^¬ ing ( s ) 121.

Fabricating the carrier 105 of the electronic device 100 fur- thermore comprises printing the first dielectric layer 110 on the base layer 112, printing the second dielectric layer 120 on the first dielectric layer 110 and printing or depositing the mounting pad 116 on the first dielectric layer 110 and printing or depositing the contact layer 125 on the second dielectric layer 120 as shown in Figure 2, Figure 5 and Fig ^¬ ure 6. In this way, the second dielectric layer 120 which partially covers the first dielectric layer 110 constitutes a top, and the first dielectric layer 110 constitutes a bottom dielectric layer of the carrier 105. Moreover, the opening 121 provides the above-mentioned mounting area 107. In the mounting area 107, the first dielectric layer 110 is not cov ^¬ ered by the second dielectric layer 120.

As also shown in Figure 6, the second dielectric layer 120 is arranged on the first dielectric layer 110 in such a way that the mounting pads 116 are located within the opening 121 and thus within the mounting area 107 constituted by the opening 121. The second dielectric layer 120 is furthermore arranged on the first dielectric layer 110 with a side opposite to a side on which the contact layers 125 are located.

It is furthermore possible to apply an additional adhesive in between the layers 110, 120 (not depicted) .

Fabricating the carrier 105 of the electronic device 100 fur ^¬ thermore comprises partially covering the two contact layers 125 as shown in Figure 7. This may be done by forming a com- mon covering layer 130 or two separate covering layers 130 assigned to the contact layers 125. Depending on the configu ^¬ ration, the covering layer (s) 130 may be arranged not only on the contact layers 125 as shown in the sectional view of Fig ^¬ ure 7, but also on the dielectric layer 120 (not depicted) . Moreover, the covering layer (s) 130 may, as the case may be, enclose or partially enclose the opening 121 and thus the mounting area 107 when viewed from above (not depicted) . The covering layer (s) 130 may comprise an insulating material and may constitute a solder mask structure of the carrier 105. By means of the covering layer (s) 130, the two contact layers 125 may be partially protected so that an impairment of the contact layers 125 may be suppressed. As shown in Figure 7, the partially covered contact layers 125 comprise regions 126, 127 which are not covered by the covering layer (s) 130. Each of the contact layers 125 com ^¬ prises an uncovered region 126 which serves as a solder ter- minal or, respectively, solder pad 126 and another region 127 which serves as a contact area 127. The solder pads 126 to which wires 160 may be connected by means of soldering (see Figure 10) are used to electrically contact the produced electronic device 100. The two solder pads 126 constitute a cathode terminal and an anode terminal of the electronic de ^¬ vice 100. The contact areas 127 to which bond wires 142 may be connected (see Figure 8) are used to provide electrical connections with the semiconductor chips 140 of the electron ^¬ ic device 100. This is described in more detail further be- low.

With respect to the fabrication of an assemblage of connected electronic devices 100, a respective number of covering lay ^¬ ers 130 may be formed on the carrier assemblage for the jointly produced electronic devices 100 so that each contact layer 125 comprises uncovered region 126, 127 constituting a solder pad 126 and a contact area 127.

After forming the covering layer (s) 130 and therefore provid- ing the solder pads 126 and the contact areas 127, it is for example possible to carry out a plating process in which the solder terminals 126, the contact areas 127 and the mounting pads 116 are provided with an additional metallic plating (not depicted) . The metallic plating may for example comprise different metallic materials or, respectively, a metallic layer stack such as NiPdAu. By means of the metallic plating, effects like an enhanced solderability, an enhanced connec ^¬ tivity to bond wires 142 and an enhanced reflectivity may be provided .

It is pointed out that method steps described with regard to the fabrication of the carrier 105 or, respectively, the car ^¬ rier assemblage shown in Figures 6, 7 may also be carried out in a different order. In this respect, it is possible to firstly cover the contact layers 125 with the covering lay ^¬ er (s) 130, and to subsequently arrange the second dielectric layer 120 on the first dielectric layer 110. Afterwards, the plating process may be carried out. It is furthermore pointed out that the carrier 105 shown in Figure 7 comprising the metal base layer 112 may be also referred to as metal core printed circuit board (MCPCB) .

Afterwards, further processes are carried out in order to fabricate the electronic device 100. This includes arranging unpackaged semiconductor chips 140, also referred to as bare dies, on the carrier 105 in the mounting area 107 as shown in Figure 8. The semiconductor chips 140 are arranged on the mounting pads 116. On each of the mounting pads 116, a re ^¬ spective semiconductor chip 140 is mounted. In order to fix the semiconductor chips 140 on the mounting pads 116, a bond ^¬ ing material such as an adhesive may be applied (not depict ^¬ ed) .

As indicated above, the carrier 105 may be produced with a number of mounting pads 116 which is different from or, respectively, greater than the two mounting pads 116 shown in the sectional view of Figure 8. This also applies to the num ^¬ ber of semiconductor chips 140 mounted on the carrier 105 in the mounting area 107 which may differ or, respectively, ex ^¬ ceed the depicted two semiconductor chips 140.

The semiconductor chips 140 shown in Figure 8 may be optoe- lectronic semiconductor chips 140, for example radiation- emitting semiconductor chips such as LED chips (light emitting diode) . Such semiconductor chips 140 may be configured as sapphire chips. In this respect, the electronic device 100 to be produced in the method may be a an optoelectronic de- vice for generating light radiation.

Each semiconductor chip 140 comprises two front-side contacts to which bond wires 142 may be attached as indicted in Figure 8. It is the front side by means of which a light radiation generated when operating the semiconductor chips 140 may be substantially emitted. The semiconductor chips 140 may be manufactured in a known manner and may comprise, in addition to the front-side contacts, components such as a semiconduc ^¬ tor layer sequence with an active zone for generating light radiation, a subsequently formed or mounted conversion layer for at least partially converting the generated light radia ^¬ tion as the case may be, etc. (not depicted) .

The bond wires 142 depicted in Figure 8 are provided and at ^¬ tached to the front-side contacts of the semiconductor chips 140 and to the contact areas 127 of the carrier 105 in a wire bonding process carried out after arranging the semiconductor chips 140 on the carrier 105. In this process, electrical connections are established between semiconductor chips 140 and the contact areas 127 as well as between semiconductor chips 140 themselves by means of bond wires 142. In this way, semiconductor chips 140 are also electrically connected with the solder pads 126.

Figure 8 depicts a possible electrical interconnection of semiconductor chips 140 in the form of a series connection. As described above, the electronic device 100 may be formed with a greater number of mounting pads 116 and therefore a greater number of semiconductor chips 140. In this regard, various non-depicted electrical interconnections may be real ^¬ ized by means of the applied bond wires 142. It is for example possible to provide one series connection including a plurality of (i.e. more than two) semiconductor chips 140 wherein only the two semiconductor chips 140 locat ^¬ ed at the ends of the series connection are connected to the contact areas 127. Another example are several series connec- tions of semiconductor chips 140, wherein the semiconductor chips 140 arranged at the ends of the series connections are respectively connected to the contact areas 127. Apart from that, it is for example also possible to consider parallel connections or mixed parallel and series connections of semi ^¬ conductor chips 140 arranged in the mounting area 107.

With regard to the fabrication of an assemblage of connected electronic devices 100, semiconductor chips 140 are arranged on the carrier assemblage in all of the mounting areas 107, and respective electrical connections are established by car ^¬ rying out a wire bonding process. Subsequently, further processes are carried out in order to produce the electronic device 100 in which further structures are formed on the carrier 105 as shown in Figure 9. This in ^¬ cludes forming a frame structure 150 on the carrier 105 which encloses the mounting area 107 and thus the semiconductor chips 140 arranged in this area 107. The frame structure 150 may comprise, similar to the opening 121 and thus the mount ^¬ ing area 107, a circular outline when viewed form above (not depicted) . The frame structure 150 may for example be formed from a sil ^¬ icone material. The frame structure 150 may be arranged not only on the covering layer (s) 130 as shown in the sectional view of Figure 9, but also, as the case may be, on the die ^¬ lectric layer 120 and/or on the contact layers 125.

Moreover, the area enclosed by the frame structure 150 is subsequently filled up with an embedding material 151, as al ^¬ so shown in Figure 9. In this way, the semiconductor chips 140 and bond wires 142 may be encapsulated and therefore pro- tected from external influences. The embedding material 151 may for example be a transparent material such as a silicone material. In an alternative configuration, the embedding material 151 may comprise a transparent matrix material such as a silicone material and phosphor particles embedded in the transparent matrix material for at least partially converting light radiation generated by the semiconductor chips 140 (not depicted) . With respect to the fabrication of an assemblage of connected electronic devices 100, frame structures 150 are formed on the carrier assemblage, each frame structure 150 enclosing a respective mounting area 107, and the areas enclosed by the frame structures 150 are filled up with the embedding materi ^¬ al 151.

Afterwards, the assemblage may be singularized into individu ^¬ al separate electronic devices 100, each device 100 having a configuration as shown in Figure 9. In this process, the as ^¬ semblage may be divided for example by means of sawing (not depicted) .

The electronic device 100 shown in Figure 9 and being pro- duced according to the above-described method comprises two dielectric layers 110, 120, wherein the second dielectric layer 120 partially covers the first dielectric layer 110, and wherein the thermal conductivity of the first dielectric layer 110 exceeds the thermal conductivity of the second die- lectric layer 120. This configuration makes it possible to provide an efficient removal of heat during operation of the electronic device 100 as well as to promote a soldering pro ^¬ cess carried out in order to contact the electronic device 100.

The semiconductor chips 140 of the electronic device 100 are arranged on the carrier 105 in the mounting area 107. In this area 107, the first dielectric layer 110 with the higher thermal conductivity is not covered by the second dielectric layer 120, and the semiconductor chips 140 are arranged on the mounting pads 116 located on the first dielectric layer 110. Consequently, heat produced during operation of the sem ^¬ iconductor chips 140 may be efficiently conducted away from the semiconductor chips 140. The heat may be efficiently transferred to the first dielectric layer 110 via the mount ^¬ ing pads 116, and via the first dielectric layer 110 to the metal base layer 112. The metal base layer 112 may act as a heat sink. Moreover, it is possible to arrange the electronic device 100 or, respectively, the metal base layer 112 of the carrier 105 on an additional heat sink (not depicted) . In this way, a heat transfer from the metal base layer 112 to the additional heat sink may occur, thus further promoting the efficient removal of heat during operation of the elec ^¬ tronic device 100 (not depicted) .

In order to contact the electronic device 100 so that elec ^¬ trical energy may be supplied to the electronic device 100 for operating the same, respective wires 160 may be connected to the solder pads 126 by carrying out a soldering process, as shown in Figure 10. As described above, the solder pads 126 constitute a cathode terminal and an anode terminal of the electronic device 100. In the soldering process, a solder 161 is used so that an electrical and also a mechanical con ^¬ nection is established between the wires 160 and the solder pads 126. In this way, the wires 160 are also electrically connected to the contact areas 127 via the contact layers 125, and therefore to the semiconductor chips 140 via the bond wires 142.

The soldering process comprises melting the solder 161 pro ^¬ vided in the area of the solder pads 126 by the application of heat. For this purpose, a soldering device or, respective- ly, a soldering iron may be used (not depicted) . Subsequent ^¬ ly, cooling down results in hardening the solder 161 so that respective solder joints are formed.

The solder pads 126 are located on the second dielectric lay- er 120 with the lower thermal conductivity. Due to this, a removal and transfer of heat to the metal base layer 112 and, as the case may be, to an additional heat sink is suppressed or, respectively, lowered in the area of the solder pads 126, thus making it possible to reliably provide and maintain an appropriate soldering temperature at the solder pads 126. As a consequence, the soldering process may be carried out with a high process quality, and reliable and stable solder joints may be formed. The soldering process may be furthermore car- ried out in an automated and therefore cost-efficient manner. Moreover, the presence of stable solder joints allows for a high efficiency when operating the electronic device 100. With respect to the dielectric layers 110, 120, the following numerical data for thermal conductivities may apply so that an effective removal of heat during operation of the elec ^¬ tronic device 100 as well as soldering with a high quality is possible with a high reliability. The first dielectric layer 110 may for example comprise a thermal conductivity with a minimum value of 10 W/mK, i.e. for example a thermal conduc ^¬ tivity in a range from 10 W/mK to 20 W/mK. The second dielec ^¬ tric layer 120 may comprise a thermal conductivity with a maximum value of 5 W/mK. The thermal conductivity of the sec- ond dielectric layer may for example be smaller than 2 W/mK or smaller than 1 W/mK.

The above-described electronic device and the method for pro ^¬ ducing the same explained with reference to the figures rep- resent possible embodiments or, respectively, embodiments by way of example of the invention. In addition to the embodi ^¬ ments described and illustrated, further embodiments which may comprise modifications and/or combinations of the fea ^¬ tures described are conceivable.

In this respect, it is pointed out that the above-mentioned materials and numerical data are examples which may be re ^¬ placed by other materials and specifications. It is for exam ^¬ ple possible to apply dielectric materials for the first and second dielectric layer 110, 120 comprising thermal conduc ^¬ tivities from the following group: 1,3 W/mK; 2,0 W/mK; 2,2 W/mK; 2,7 W/mK; 3,0 W/mK. In this respect, it may for example be considered that the first dielectric layer 110 comprises a thermal conductivity of 3,0 W/mK, and that the second dielec- trie layer 120 comprises a thermal conductivity of 1,3 W/mK.

Instead of providing a respective mounting pad 116 for each of the semiconductor chips 140, it is also possible to pro- vide one mounting pad 116 (per produced electronic device 100) on which several semiconductor chips 140 may be ar ^¬ ranged . It is further pointed out that instead of semiconductor chips 140 comprising two front-side contacts, other semiconductor chips, for example comprising a front-side contact and a back-side contact or comprising two back-side contacts may be applied. Such semiconductor chips may be arranged on mounting pads 116 located in a mounting area 107 of a carrier 105 and may be mechanically bonded and electrically connected to the mounting pads 116 by means of an electrically conductive bonding material such as an electrically conductive adhesive. In such configurations, the mounting pads 116 may be also used for providing electrical connections between semiconduc ^¬ tor chips and contact areas and/or between semiconductor chips themselves. In this regard, bond wires 142 may be con ^¬ nected to the mounting pads 116 so that for example mounting pads 116 and semiconductor chips and/or mounting pads 116 and contact areas 127 may be electrically connected.

Moreover, an electronic device may not only be realized with radiation-emitting semiconductor chips 140. Instead of radiation-emitting semiconductor chips 140, other types of semi- conductor chips may be used. An example are radiation- receiving semiconductor chips. Moreover, apart from optoelectronic semiconductor chips, other types of semiconductor chips may be considered. Another possible configuration is an electronic device com ^¬ prising only one semiconductor chip arranged on a carrier or, respectively, on a mounting pad 116 of the same.

While the invention has been described in detail with refer- ence to specific embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

REFERENCE NUMERALS

100 device

105 carrier

107 mounting area

110 first dielectric layer

112 metal base layer

114 metallic layer

116 mounting pad

120 second dielectric layer

121 opening

124 metallic layer

125 contact layer

126 solder pad

127 contact area

130 covering layer

140 semiconductor chip

142 bond wire

150 frame structure

151 embedding material

160 wire

161 solder