TECHNICAL FIELD

The invention relates to an electronic driver for a lightsource having a power factor correction circuit and a driver circuit to power the lightsource which is fed by the output of the power factor control circuit. The invention further relates a method of controlling a factor correction circuit of an electronic driver for a lightsource. BACKGROUND TO THE INVENTION

The use of electronic drivers for operating lightsources, e.g. gas discharge lamps or LED, is preferred over the use of conventional ballasts, due to lower losses and improved lamp efficiency, leading to significant energy savings. The input of a typical electronic ballast is formed by means of a factor correction circuit connected to the voltage supply mains, which factor correction circuit is a kind of high frequency filter which is connected with a rectifier circuit.

The power factor of an AC electric power system is the ratio of the real power flowing to the load to the apparent power in the circuit and is a dimensionless number between 0 and 1. It is desirable for the power factor to be as close to 1 as possible.

The power factor correction (PFC) circuits are often used within power supply applications in which AC/DC rectification is performed. Such rectifying arrangements typically comprise a full wave voltage rectifier (usually a diode bridge) and an output capacitor to provide regulation of the output waveform at the output bus. This type of rectifying arrangement only draws current from the AC supply when the full wave rectifier voltage is greater than the voltage across the output capacitor. This is unsatisfactory as it gives an inefficient current profile of the input AC current consisting of separated narrow pulses of current having large peak values. The high harmonic content of this current profile gives a low power factor (typically 0.5) of the rectifying arrangement as a whole.

The power factor is improved by applying a PFC circuit between the diode bridge and the output capacitor. Such a PFC circuit essentially comprises an inductor followed by a diode, with a switch (typically an FET) connected between the inductor and the diode to ground.

By rapidly switching the switch on and off, the inductor is repeatedly first connected directly to ground via the switch and then connected to the output capacitor (via the diode) when the switch is turned off. When the switch is on the current flow through the inductor increases and, during the subsequent time period in which the switch is off, the current decreases, effectively pushing current through the diode to charge the output capacitor. By adjusting the on and off times of the switch by a suitable power factor control circuit the output voltage may be adjusted to a fixed, desired value (target value), although the output voltage is always higher than the input voltage because of the action of the diode in conjunction with the "boosting" action of the inductor.

Figure 1 shows such a known power factor correction circuit 125, based on a boost converter topology. A smoothing capacitor 104 filters a rectified AC input voltage (typically from a bridge rectifier) that is measured by a voltage divider 105, 106. The rectified input voltage is applied to an inductor 101. A secondary winding 102 detects the zero crossings of the current through the inductor 101. A current sensing resistor (shunt) 108 connected to the source of a switch 107 (typically a FET) allows the detection of the inductor peak current to determine a possible over-current condition. In parallel with an output capacitor 1 1 1, a second voltage divider 109, 1 10 is arranged to measure the DC output voltage and a surge condition, for example, due to by load variations. The above four measurements that take place in the power factor correction circuit 125 by means of four measuring inputs 1 17, 1 18, 1 19 and 120 of an electronic control circuit 1 16. The control circuit 1 16 additionally has an output 121, through which the switch 107 is controlled. The electronic control circuit 116 is typically arranged as an ASIC. A total of five pins are used for power factor correction.

In this power factor correction circuit 125 the rectified input voltage is fed to the inductor 101. The inductor 101 is by means of the switch 107 either loaded or unloaded. The on-time of the switch 107 and thus the load time of the inductor 101 is controlled based upon a comparison of the measured DC output voltage V _bus with a fixed reference voltage. The switch 107 is turned off to discharge the inductor 101 until the current through the inductor 101 has fallen to zero (as detected by the secondary winding 102). The switch 107 is cycled with a much higher frequency (at least 10 kHz) than the frequency of the mains voltage (typically 50 Hz) and the frequency of rectified DC input voltage (typically 100 Hz) To reduce costs power factor correction arrangements which include an electronic control circuit with only a single pin for receiving measurement inputs are know - for example from DE 102004025597 and WO 201 1009717.

Known follow boost arrangements help prevent flow of current directly from the mains supply, via the boost inductor and diode, to the output bus. However, where such current flow does occur, the PFC circuit will typically exhibit instability, with the potential to cause visible flicker in a lamp that is powered by the PFC circuit. It is an object of an embodiment of the present invention to increase the range of input supply voltages over which the PFC circuit of an electronic driver for a lightsource remains stable and would not cause visible flicker in a lightsource powered by the PFC circuit. It should, however, be appreciated that the invention is applicable to PFC circuits that power devices other than lightsources.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provided a method of power factor correction for an electronic driver for a lightsource in which an input voltage is applied to an inductor which is cyclically discharged through a diode by the operation of a switch, the switch being controlled by a controller which varies the on period of the switch, during which the inductor is charged, for adjusting an output voltage towards a target value, the method including obtaining an indication of the inductor reaching a discharged state in response to the switch being in an off state, characterised by the controller adjusting the target voltage value in dependence upon an indication of the ratio of the off period of the switch to the on period of the switch.

Conventionally, the target voltage is not varied. On the contrary, typically PFC circuits aim to maintain a constant output (target) voltage. In the embodiment of the present invention to be described, by adjusting the target voltage value in dependence upon an indication of the ratio of the off period of the switch to the on period of the switch the range of input supply voltages over which the PFC circuit remains stable is increased. The target voltage value in the detailed embodiment to be described is increased when the ratio of the off period of the switch to the on period of the switch exceeds a threshold.

In the embodiment, the target value is decreased when the ratio of the off period of the switch to the on period of the switch is below the threshold. In the embodiment, this threshold is the same as the threshold in the preceding paragraph. However, it is possible that there are used different thresholds for increasing and decreasing target voltage value to reach a kind of hysteresis behaviour. The threshold is selected to have a suitable value. The threshold may be 20:1 or less, and is preferably 8: 1 as this is a convenient threshold to implement in a binary system. Other threshold values may be used in dependence upon the circumstances.

In the embodiment the controller controls the switch using information from a single input. This single input may provide an indication of the voltage across the switch. In the embodiment the switch is a field effect transistor (FET), and the single input is an indication of a voltage across the drain to source of the FET.

In the embodiment the controller is an ASIC, and includes the two pins for performing power factor correction, one of which receives the single input mentioned above, and the other of which controls the switch - by controlling at what times a voltage is applied to the gate of the FET. The controller may be formed by a microcontroller or another kind of integrated circuit.

According to a second aspect of the present invention, there is provided a electronic driver for a lightsource comprising a power factor correction circuit including an inductor, a diode, a switch and a controller, operable such that an input voltage applied to the inductor is cyclically discharged through the diode by the operation of the switch, the switch being controlled by the controller which is operable to vary the on period of the switch, during which the inductor is charged, for adjusting the output voltage towards the target value, the controller being responsive to an indication of the inductor reaching a discharged state when the switch is in an off state, characterised in that the controller is operable to adjust the target voltage value in dependence upon an indication of the ratio of the off period of the switch to the on period of the switch.

The electronic driver for the lightsource may include a driver circuit to power the lightsource which is fed by the output of the power factor control circuit. The lightsource may be, for example a gas discharge lamp, LED or OLED. The driver circuit to power the lightsource may be a resonant half bridge, a flyback or a buck converter. BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention an embodiment will now be described by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a prior art power factor correction circuit;

Figure 2 shows a power factor correction circuit in accordance with the embodiment of the present invention, including an electronic control circuit; Figure 3 shows the voltage across the switch of the circuit of Figure 2. This signal combined with the current in Q3 appears at pin PF _mon of the electronic control circuit;

Figures 4A and 4B are a flowchart showing the steps performed in accordance with the power factor correction procedure of the embodiment of the present invention; and

Figure 5 is a timing diagram which shows how the ratio of T _off to T _on varies as the input voltage varies, and the action of the electronic control circuit to increase or decrease the target output voltage in response to the T _0ff : T _on ratio exceeding a threshold. DETAILED DESCRIPTION OF EMBODIMENT OF THE INVENTION

Figure 2 shows a power factor correction circuit of an electronic driver for a lightsource in accordance with an embodiment of the present invention. A sinusoidal input voltage V _in (for example 240v AC mains voltage) is applied to a bridge rectifier 20. The resultant voltage at the input capacitor 22 comprises a succession of half sine waves of the same polarity. (It should, however, be understood that the PFC circuit of the present invention can also be used with an input DC voltage.) The capacitor 22 filters out unwanted high frequency noise. The electronic driver for a lightsource may further comprise one or more driver circuits to power the lightsource. The driver circuit which powers the lightsource is fed by the output voltage V _us of the power factor control circuit. The driver circuit is not shown in this example for simplicity. The driver circuit may be a resonant half bridge, a flyback or a buck converter.

The electronic driver for a lightsource may further comprise an interface through which the intensity or the operation mode of the lightsource can be controlled.

The rectified input voltage is applied to inductor LI . A diode Dl is connected between the inductor L 1 and the output bus at which the output voltage V _us is provided across output capacitor C 1. A switch (in this embodiment a FET) Q3 has its drain connected between the inductor LI and the diode Dl and its source connected to ground. The gate of the switch Q3 is controlled by the single PFC output PF _out of electronic control circuit 24, which in the embodiment is an ASIC. Resistors 26 and 28 are connected in series to form a voltage divider arrangement which is coupled in parallel between the source of the switch Q3 and to a point between the drain of the switch Q3 and the diode Dl . A further resistor 29 is connected in series between the source of the switch Q3 and ground and has a much smaller resistance than that the resistance of resistors 26 and 28. The voltage at measuring point 30 between the resistors 26 and 28 is monitored by the single power factor control input pin PF _mon of the electronic control circuit 24.

Briefly, the normal operation of this circuit is as follows. The electronic control circuit 24 output PF _0Ut selects an appropriate on time duration T _on for the switch Q3 and applies a voltage to the gate of the switch Q3 to close the switch during period T _on . The current in the inductor LI increases during the period T _on . When the period T _on ends, the output PF _0Ut of the electronic control circuit 24 controls the gate of the switch Q3 to open the switch, starting the period T _off . During the time period T _off the energy stored in the inductor LI during the period T _on is gradually discharged and is pushed through the diode Dl to charge the output capacitor CI . By adjusting the T _on and T _off periods the output voltage V _bus can be adjusted, but is always higher than the input voltage because of the action of the diode in conjunction with the boosting action of the inductor LI . The switch is cycled at a frequency (e.g. 10kHz) much higher than the frequency of the input mains voltage (e.g. 50 or 60 Hz). Conventionally, the power factor control circuit would be operated to maintain the output voltage V _bus at the bus at a constant target value, V _bus target- In normal operation the power factor control circuit of an electronic driver for a lightsource operates in a critical continuous mode (CCM). In the CCM the period T _off should end as soon as the current flowing through the inductor falls to substantially zero. As mentioned above, conventionally, the zero crossing of the current from the inductor is measured using a secondary winding provided in relation to the inductor LI . However, providing such a secondary winding increases the cost of the power factor correction circuit. Further, for the secondary winding to be monitored by the electronic control circuit 24, an additional input pin to receive the measurement signal from the secondary winding would be required, which would add to the size, complexity and cost of the electronic control circuit.

According to the present embodiment the electronic control circuit 24 estimates whether the current from the inductor LI is zero using the signal applied to the PF _mon input of the electronic control circuit 24.

When the switch Q3 is open during time period T _off the input PF _mon to the electronic control circuit 24 from measurement point 30 provides an indication of the voltage across the switch Q3. This voltage corresponds substantially to the output bus voltage V _bus from the beginning of the time period T _0ff until the inductor discharge current reaches zero. When the inductor current reaches zero, the measured voltage by PF _mon reduces, and then indicates Q3 current during time period T _on . Figure 3 shows a waveform typical of the voltage across the switch Q3, which is monitored by PF _mon .

Time period A corresponds to T _on , when switch Q3 is closed and the inductor LI is charged. During this period A the voltage at PF _raon indicates the current in Q3. When the switch is then opened, time period T _off begins, as represented by time periods Bl and B2 in Figure 3. During time period Bl the inductor LI is steadily discharged and the current flowing through the diode Dl gradually deceases from an initial relatively high current. During time period Bl the voltage PF _mon corresponds substantially to the output voltage V _bus (400 volts in this example). However, as the current from the inductor LI reaches zero, at the beginning of time period B2, the voltage PF _mon reduces.

A threshold of the PF _mon voltage is set at which the electronic control circuit 24 determines that the inductor current has reached zero. For example, when the voltage PF _mon falls to a zero current indicator value it is determined by the electronic control circuit 24 that the zero inductor current point has been reached. The zero current indicator value may be 90% of the voltage measured at PF _mon during the time period Bl immediately preceding the current time period B2. The voltage may be measured at the beginning of period Bl, after a predetermined delay from the start of time period Bl, or by detecting the voltage a plurality of times during time period Bl and averaging (e.g. calculating the arithmetical mean of) the voltages, or using the highest or lowest value of the plurality of voltages. In response to this determination, the electronic control circuit 24 closes the switch Q3, thereby ending the time period T _0ff and beginning the next time period T _on .

The electronic control circuit 24 calculates the output voltage V _bus indicated by PFmon during time period Bl and compares this to a target output voltage bus _j arget- I the indicated output voltage is less than the target value, then the time period T _on is increased. Conversely, if the indicated output voltage is greater than the target output voltage, then the time period T _on is decreased.

As the input voltage V _in increases relative to the output voltage V _bus , the electronic control circuit 24 increases the ratio of T _off : T _on - the decrease in the period T _on reducing the voltage boost in order to maintain the output voltage Vbus constant. The ratio T _off : T _on should therefore give an indication of the input mains voltage V _in .

In accordance with the present embodiment, it is desirable to prevent current flow directly from the input mains supply via the boost inductor LI and diode Dl to the output bus in order to avoid PFC circuit instability, which can occur at relatively high mains voltages V; _n . In accordance with an important feature of the embodiment of the present invention, it is desired to increase the output voltage Vb _us ^at the bus before the input mains voltage V _in increases above a predetermined proportion of the output voltage Vb _us

By increasing the output voltage V _bus at the bus, the PFC circuit is able to operate at higher input mains voltages V _in (relative to the output voltage) than would otherwise be the case without instability occurring.

However, in the embodiment, advantageously, the output voltage is not increased to an unlimited value. If the normal target output voltage is 400 volts, then in the embodiment increasing the output voltage V _bus up to 420 volts is contemplated. Once the output voltage is determined to have reached 420 volts, no further increases in the output voltage are performed, as this would require a larger output capacitor CI, which would increase costs. When the input voltage Vi _n is of such a high value that an output voltage above 420 volts would be required, this is considered to be outside the normal operating voltage range of the PFC circuit, and instability outside the normal operating voltage range is considered to be acceptable (although preferably no damage is caused). Outside of the normal operating voltage range, the PFC circuit may not operate, or at least will not operate in the CCM.

As discussed above, the ratio of T ₀ ff: T _on can provide an indication of the input mains voltage V _in . However, for this ratio to vary in a predictable manner with different values of mains voltage Vj _n , the point at which the zero inductor current flow occurs must be detectable by the electronic control circuit 24, so that the transition between time period T ₀ ff and T _on can be performed by the electronic control circuit 24. If the zero inductor current cannot be detected, then electronic control circuit 24 cannot determine when the time period T _off should end and the next time period T _on should begin.

From the discussion above, it will be understood that the point at which the inductor current reaches zero is detected by measuring at PF _mon the voltage across the drain and source of the switch Q3. The electronic control circuit 24 determines when the voltage at PF _mon falls to below 90% of the bus voltage value V _Bus (measured at PF _mon during period Bl in Figure 3) as an indication that there is zero inductor current. When zero inductor current flows, the voltage of PF _mon reduces and oscillates as shown in Fig.3. However, if the input mains voltage V _in is a high proportion of the bus voltage V _Bus , then the 90% threshold of the electronic control circuit 24 will never be crossed and it will never be detected that zero inductor current is flowing. The electronic control circuit 24 will therefore not be able to determine when to transition from the T _off to T _on state. The T _off : T _on ratio will no longer provide an indication of the input mains voltage, and so cannot be used to determine when to increase the output voltage at the bus in order to put off the onset of instability.

The electronic control circuit 24 may include a timer that times the duration of the T _off period. When the T _off period exceeds a maximum value (for example, 800ms), the electronic control circuit 24 may then automatically close the switch Q3, thereby ending the time period T _off and beginning the next time period T _on , even though no zero inductor current crossing has been detected. Whilst such an arrangement allows the PFC circuit to continue operating, the ratio of T _off :T _on is no longer proportional to the input mains voltage V; _n . This presents a problem: it is desired to increase the voltage V _bus target when the input mains voltage V _in is a high proportion of the bus voltage V _Bus , but when this state exists, there is no reliable way of determining the input mains voltage V _in ; it is not monitored directly by the electronic control circuit 24, and is no longer indicated by the ratio of T ₀ ff.T _on .

In the embodiment, a method of controlling the target voltage V _busJarget is used, which allows the onset of instability to be put off when the input mains voltage V _in is relatively high but which does not rely on the ratio of T ₀ ff:T _on to indicate when the input voltage is so high that instability might occur.

In accordance with an advantageous aspect of the present embodiment, if the ratio T ₀ f : T _on exceeds a predetermined threshold, such as KF:1 (i.e. if T _off exceeds KF x T _on ), then the target output voltage V _{bus Jarget} is increased. The T ₀ ff: T _on ratio may be calculated by the electronic control circuit 24, and the increased target voltage V _us _target ^mav be implemented in the control logic of the electronic control circuit 24 and applied to future calculations of the Τ _ο1Γ : T _on ratio. As will be understood from the preceding discussion, increasing the target voltage Vbusjarget will tend to increase the value of T _on relative to T _off . The predetermined threshold may be programmable or adaptive (i.e. adjusted during operation out of measurement results).

By selecting the ratio of KF: 1, this will result in the target voltage V _bus j _arget being increased before the input mains voltage V _in approaches such a high value that the zero inductor current cannot be detected at PF _mnn .

In normal operation of the circuit, the relationship of the duty cycle, D, of the switch Q3 to V _in and V _bus is:

D = 1 - (V _in / V _bus ), where

D = T _on / (T _on + T _off ) A ratio of T _off : T _on of KF:1 gives a duty cycle of : D = 1 / (1 + KF)

Assuming a bus voltage V _bus of about 400V at the capacitor C 1 in Fig.2, a ratio of T _off : T _on of KF:1 gives:

D = 1 / (1 + KF) = 1 - (Vi„ / 400 V) so V _in « 356 V (which is approximately 90% of V _bus ) for KF = 8.

The arrangement will preferably start increasing V _bus _ _target when V _in is approximately 90% of V _bus .

Other ratios of a ratio of T _off : T _on may be used. Theoretically a difference of about 5% between V _bus and V _in is enough for the concept to work. Up to this point the ratio of T _off : T _on can give an indication of the mains voltage V _in . For a bus voltage V _bus of about 400V at the capacitor CI in Fig.2, this gives a maximum mains voltage V _in of 380V before increasing V _{bus target} . ). This gives a duty cycle of:

D = l - (380V / 400V) - 1/20, equivalent of a ratio of T _off : T _on of 19: 1, or about 20: 1.

If, in response to the increase in the target output voltage V _{bus target} , the T _off : T _on ratio decreases (i.e. T ₀ ff is less than KF x T _on in the preferred embodiment), then the target output voltage V _busJarget is decreased by the control logic. Advantageously, the rate of increase of the target voltage V _{bus target} will be higher than the rate of decrease of the target voltage V _busJarget . As indicated above, an upper limit may be applied to the target voltage V _{bus target} , to prevent the follow boost from increasing the bus voltage excessively - for example, above 420 volts. It is also possible that either T _on or T ₀ f as input values for the calculation of the threshold (for determination of the ratio of T ₀ ff: T _on as an indication of the input mains voltage V _in ) are adjusted by an offset value. This can be done for instance if parasitic effects have to be compensated. The embodiment will now be described in relation to the flowchart of Figures 4 A and 4B. The target bus voltage V _busJarget is initially set at an optimum value (also refered as Vbus min), for example 400V. At step A the output pin PF _0Ut of the electronic control circuit 24 receives from the control logic an instruction to switch the switch 23 on.

At step B the pin PF _0Ut switches the gate on in order to close the switch Q3. Time period A Figure 3 ensues. The duration of T _on is calculated by the control logic in the electronic control circuit 24.

At step C, when the control logic determines that the time period T _on ends, the pin PF _0Ut then opens the switch Q3. This causes the period T _off to begin, at step D. Time period Bl of Figure 3 then ensues. During time period Bl, the voltage at pin PF _mon is monitored, at step E.

When the voltage at pin PF _mon falls below a threshold (90% of the detected output bus voltage V _bus in the example), it is determined that the zero inductor current stage has been reached, at step F.

At step G the control logic calculates a new period T _on based on the measurements made at pin PF _mon . For example, the control logic may determine the difference between the indicated bus voltage at PF _mon during time period Bl and the target bus voltage V _bu sjarget- If the indicated bus voltage is less than the target bus voltage V _{bus target} , then the new time period T _on will be increased over the previous period T _on . Conversely, if the indicated bus voltage is greater than the target bus voltage V _{bus target} , then the new time period T _on may be decreased compared to the previous time period T _on . At step H it is determined whether the ratio of T _off : T _on is greater than KF: 1. If, at step H, it is determined that the ratio of T _off : T _on is greater than KF: 1 then the control logic determines that it would be desirable to increase the target bus voltage V _{bus target} in order to put off the onset of instability. However, before the target voltage V _us _ _target is increased, at step I it is determined whether Vbus _j a _rget is i ^{ess man} a maximum value (set at 420 volts in this example).

If at step I it is determined that V _bus _ _target is less than the maximum value, then at step J the bus target is incremented by an amount VBUS UP. The new value of V _{bus Jarget} is then used in future calculations of T _on by the control logic until the target bus voltage V _bus is changed again. The process then returns to step A.

If at step I it is determined that V _{bus Jar&et} is greater than or equal to the maximum value, then the process returns to step A without incrementing the target voltage V _{bus Jarget} . This prevents the target bus voltage being increased excessively, which would require the use of a larger rated voltage CI and would anyway be outside the normal operating voltage of the PFC circuit.

If at step H it is determined that the ratio of T _{o f} : T _on is less than or equal to F.T, then at step K it is determined whether the target bus voltage V _{bus target} is greater than the optimum value of the voltage bus (400V in this example).

If at step K it is determined that the target bus voltage V _busJarget is equal to (or less than) than the optimum value, then the process returns to step A. On the other hand, if at step K it is determined that the target voltage V _bus ^ _g e _t is greater than the optimum value, then, at step L the target voltage V _bus ^ _g e _t is decremented by an amount VBUS DN. However, before the target voltage Vt _m s _jarg e _t is decreased, at step K it is determined whether V _{bus target} is less than a minimum value (set at 400 volts in this example).

Advantageously, the rate of increase of V _{bus t} a _rget will be greater than the rate of decrease of V _busJarget . This may be achieved by only allowing step J to be repeated when a minimum time period P _up has elapsed. For example, the minimum time period P _up may be the rectified input voltage cycle period. Further, step L is only allowed to be repeated when a minimum time period Pdown has elapsed. For example, the minimum period Pdown may be 10 times the period P _up .

The effect of the flowchart of Figure 4 can be seen by consulting the waveform timing diagrams of Figure 5. Waveform (a) shows the voltage of the rectified input voltage V _in over a period of time, T = 1... T = N.

Waveform (b) shows the ratio T _off : T _on over the same time period. This is the ratio that will be calculated by the logic of the electronic control circuit 24 in performing the power factor control function. As discussed above, as the input voltage V _in increases relative to the output voltage V _bus , the radio T _off : T _on will be increased in order to tend to keep the output voltage at a desired target value. This can be seen in the waveform (b), where the ratio T _off : T _on increases when the voltage V _in increases. The dashed line 51 represents the point at which the ratio T _off : T _on exceeds KF:1.

The ratio exceeding F: 1 will be detected by the control logic in the electronic control circuit 24, and a signal (c) generated when this condition is true, in order to increment the V _{bus target} by the value VBUS UP (corresponding to step J in the flowchart of Figure 4).

When the ratio T _of f: T _on is less than F:1, then the Vbus target value is decremented by the amount VBUS DN, corresponding to step L of Figure 4.

The changing of the Vb _Usj arget value is shown in waveform (d).