This invention relates generally to an electronic lock comprising at least one key member with a code identifying said member, and a lock member having means for storage of opening codes authorizing opening of the lock, and for comparison of- a code receiv¬ ed from a key member with each of the stored opening codes.

To open an electronic lock comprising a key mem¬ ber and a lock member it is necessary to transmit from the key member to the lock member information that identifies the key member. This information is hereinafter designated the key code. If the code trans¬ mitted from a key member is found, when checked, to be correct the lock is opened. When a key is lost it shall preferably be possible to use a key having another key code than the lost one and at the same time the code of the lost key must not be accepted any more by the lock members.-

It has already been suggested to use in electronic locks keys having two codes which are elements of a consecutive series such that the second code of a key is the first code of the next key, etc. If at least one code of a lost key is known a new key can be made, it being possible to satisfy the above-mentioned desire (see for example U.S. Patent Re.29,259) .

The object of the present invention is to provide an electronic lock which in addition to the above-men¬ tioned desire also satisfies high requirements placed on the possibilities of selecting the codes by means of which the lock shall permit being opened.

This and further objects of. the invention are rea¬ lized in that the electronic lock of the kind indicated in the introduction is embodied with the characteristic

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features according to any of the appended claims.

The invention will be described in greater detail hereinbelow with reference to the accompanying drawing which illustrates a block diagram of an embodiment of the lock member of the electronic lock according to the present invention.

A first comparator 1 has a programmable read only memory 2, inputs connected to a shift register 3 and two outputs coupled directly and via a delay element 4, respectively, to a clock input and a reset-input of a counter 5 having four outputs. The output of the shift register 3 is also connected to a first input of a se¬ cond comparator 6 the second input of which is coupled to the read output of a random access memory 7 the read in put of which is also connected to the output of the shift re gister 3. The output of the comparator 6 and the first output (0) of the counter 5 are each connected to one input of an AND gate 8 the output of which is coupled to a input of. an OR gate 9 the second input of which is coupled to the fourth output (3) of the counter 5. The read out¬ put of the random access memory 7 is also coupled to an input of a third comparator 10 the second input of which is supplied with a code containing all zeros and the output of which is coupled to an input of a se- cond AND gate 11. The second input of the AND gate 11 is coupled to the second output (1) of the counter 5 and the output of the AND gate is connected to the write in¬ put of the random access memory 7. The output of the comparator 6 and the third output (2) of the counter 5 are connected each to one input of a third AND gate 12 the output of which is connected to an input of a second OR gate 13 the second input of which is connected to the fourth output (3) of the counter 5 and the output of which is connected to the erase input of the random access memory 7.

The above-described lock member has the following

modes of function, it being presupposed that a control code is stored in the read only memory 2, several open¬ ing codes different from the control code are stored in the random access memory 7 and the counter 5 in the output state delivers a signal on its first output.

A code identifying the key- member is transmitted to the shift register 3.

If said key code is not equal to the control code of the read only memory 2 but equal to an opening code of the random access memory 7, the comparator 1 will supply a signal to the delay element 4 and the comparator 6 will deliver a signal to the AND gate 8 which thus re¬ ceives signals on both of its inputs and thus delivers a signal to the OR gate 9. Said signal occurs at the output of the OR gate 9 as a signal releasing or allow¬ ing opening of the lock. After the delay of the delay element a signal is supplied to the reset input of the counter 5, which is however already reset.

If the supplied key code is neither equal to the control code in the read only memory 2 or any of the opening codes in the random access memory 7 the delay element 4 only will receive an input signal and will deliver with delay a reset signal to the counter 5.

If the key component is of the type containing a code corresponding to the control code in the read only memory 2 said code when supplied once to the shift re¬ gister 3 will cause the comparator 1 to deliver a clock signal to the counter 5 and advance said counter by one step such that the _. signal occurs at the second output (1) of the counter 5. If the code corresponding to the control code is supplied a second time to the shift re¬ gister 3 the counter 5 will be correspondingly advanced by another step and as a result a signal occurs at the third output (2) of the counter 5. If the same code is supplied a third time the counter 5 will be advanced by

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a further step such that there occurs at its fourth out¬ put (3) a signal which passes the OR gate 9 and provides a signal permitting or releasing opening of the lock. The signal at the fourth output of the counter 5 is also supplied via the OR gate 13 to the erase input of the - random access memory 7 whereby all opening codes stored in the random access memory are erased.

If an optional code is supplied to the shift re¬ gister from a key member after the ^" counter 5 has been advanced by one step said code will be written into the random access memory 7 in an empty position therein, as determined by the comparator 10. Immediately afterwards the counter 5 is reset via the delay element 4, and an opening signal occurs at the output of the OR gate 9. If a code corresponding to an opening code of the random access memory 7 is supplied to the shift register 3 after the counter 5 has been advanced by two steps the opening code only will be erased in the random access memory because of the occurrence of simultaneous signals at the inputs of the AND gate 12.

An electronic lock designed in conformity with the present invention will thus permit completely controlling which key or keys shall be able to open the lock (be¬ cause the codes of the key or keys are registered in the read only memory 2) . The particular key having the control code is not normally utilized but is kept in a safe place. Essential advantages inherent in the lock according to the invention are tha*t no- knowledge of the codes of the keys in question is required, i.e. for use with the lock there are not required keys having codes especially developed for the the lock, and that an op¬ tional number of different keys can be registered in the random access memory and therefore be utilized for open¬ ing of the lock.