GRAPHENE, METHOD FOR ITS MANUFACTURE AND CHIP COMPRISING THE

SAME DESCRIPTION FIELD OF THE INVENTION

The present invention relates to electronic and optoelectronic devices showing very low electrical resistance, more in particular, to superconductive devices comprising graphene and AB0 ₃ crystals.

STATE OF THE ART Recently graphene, a honeycomb bi-dimensional Carbon monolayer (Fig.1 ), has become a prominent material of research given its unique properties, including mass-less Dirac behavior for the electrons, quantum hall effect, a minimum conductivity even when the carrier density tends to zero, a high electronic mobility independent of the level of doping for a quite large range and a uniform (2.3%) absorption over the full optical spectral range, impermeability against oxygen, water and helium, high elastic strength. Last but not least, it presents the possibility to tune the electronic and optical properties by changing the level of doping through electric fields. Since the preparation of high quality flakes in 2004 using mechanical exfoliation, several electronic and photonic devices have been realized, including high frequency transistors, liquid crystal displays, high efficiency photodetectors, resonating membranes and organic solar cells. The future industrialization of the graphene containing devices significantly depends on the availability of large graphene sheets with high quality on the appropriate substrate. Another crucial aspect for most of the applications is being able to induce doping in graphene and change its electrical and optical properties. For example an undoped graphene layer has a typical sheet resistance of >1000 ohm/square, making the doping necessary for most of the electric and electronic applications. The electrical properties of graphene also depend significantly on the substrate. For example suspended graphene as well as graphene on hexagonal boron nitride typically show a conductivity one order of magnitude larger than graphene on glass. The improved electrical performance of graphene on crystalline boron nitride is mainly due to a lower surface roughness and the interactions at the interface with the substrate, thanks to the matching of the graphene lattice with the hexagonal boron nitride. It has also been theoretically shown that graphene can become superconductive if properly intercalated by lithium atoms, though with very low (about 10K) critical temperatures [G. Profeta et al., Nature Physics vol.8, p.131 (2012)]. In another theoretical work [G. Savini et al., Phys. Rev. Lett. Vol.105, p.037002 (2010)] it has been shown that hydrogenated graphene (graphane) when properly doped with holes at levels higher than 10 ¹⁴ cm ^"2 can become superconductive at 90K.

Supercurrent in graphene (superconducting proximity effect) was observed experimentally at lower level of carrier density when superconducting contacts were used in a Josephson junction configuration [H.B. Heershe et al., Nature 446, p. 56 (2007)].

SUMMARY OF THE INVENTION

The present invention aims to achieve an electronic or optoelectronic platform with sheet resistance lower than 1 Ω/square, at higher temperatures as in the prior art, that is, higher than 77K.

For this purpose, the invention comprises an electronic platform comprising a substrate made of a AB0 ₃ crystal and at least one layer of a two-dimensional conducting sheet of carbon atoms of a thickness between one and four atoms, wherein the conducting layer are placed on top of a face of the crystal whose orthogonal axis is at an angle up to 35 ⁵ of the crystal's spontaneous polarization axis (usually called c-axis or c-cut). The crystal can be LiNb0 ₃ , LiTa0 ₃ , Lil0 ₃ , Ba _x Sn- _x TiOjj _, Pb(Zr _x Ti ₁ . _x )0 ₃ , with x varying between 0 and 1 . Optionally, the graphene layer is shaped as Hall bars and the platform comprises gold contacts of a thickness of 10 to 1000 nm. The invention also comprises a chip platform with a layer of chromium of a thickness of 1 to 50 nm between the graphene layer and the gold contacts.

BRIEF DESCRIPTION OF THE DRAWINGS To complete the description and in order to provide for a better understanding of the invention, a set of drawings is provided. Said drawings illustrate a preferred embodiment of the invention, which should not be interpreted as restricting the scope of the invention, but just as an example of how the invention can be embodied. The drawings comprise the following figures:

Fig. 1 shows the hexagonal structure of graphene with Carbon atoms distance of about 0.142 nm.

Fig. 2 shows the octahedra linking conditions of constituent atoms of LiNb0 ₃ crystals in the ab crystallographic plane.

Fig. 3 is a side view of LiNb0 ₃ crystals with opposite spontaneous polarization (P _s ). Fig. 4 shows a graphene layer on a c-cut LiNb0 ₃ crystal according to the invention. Fig. 5 depicts an embodiment of the inventions of the graphene on LiNb0 ₃ chip layout, electrical measurements set up in the cryogenic environment.

Fig. 6 shows an embodiment of the invention provided with contacts made of gold and the graphene in the shape of Hall bars.

Fig. 7 is a graph of the temperature cycle inducing anomalously low electrical resistance in the graphene on LiNb0 ₃

Fig. 8 is a graph of the resistance as a function of current at different temperatures after the thermal cycle of Fig. 7.

DESCRIPTION OF THE INVENTION

The invention is based on the following effect: The crystal structure of LiNb0 ₃ consists of distorted oxygen octahedra by sharing their corners, faces and edges along different crystallographic directions, forming a trigonal (c-axial) lattice. Along the c-axis (the ideal cation stacking sequence along the trigonal axis is□— Li— Nb—□— Li— Nb—□—□ where□ indicates a vacancy) each octahedron shares its oxygen planes with the neighboring upper and lower ones. In the ab plane, perpendicular to the c- axis, each octahedron shares its oxygen edges with the neighboring ones (Fig.2). In Fig.2 we can see that each octahedron is surrounded by other six octahedra, e.g. each Li0 ₆ octahedron is surrounded by three D0 ₆ octahedra and three Nb0 ₆ octahedra [D. Xue et al., Journal of Physics and Chemistry of Solids vol.66, p.589 (2005)]. LiNb0 ₃ in its ferroelectric phase has a spontaneous electrical polarization (P _s ) of about 0.72 C/m ² along the c-axis. The ferroelectric state is characterised by a hysteresis effect of the electrical polarization as a function of the applied electric field, making the crystal possess P _s in the absence of an external electrical field. A region of the crystal with uniform P _s is called domain. The crystal is called single domain or single crystal when it has the same P _s through the whole volume. Note that LiNb0 ₃ can also have either a paraelectric phase whereby there are no regions with P _s or a multidomain crystal structure consisting of domain regions oriented in a random or predefined manner. In a simplified picture the side view of the structure of ferroelectric LiNb0 ₃ is represented in Fig. 2. Note that the Li ⁺ ions are positioned on opposite sides of the oxygen planes while the Nb ⁵⁺ ions are in between oxygen planes. It is also known that one can switch the spontaneous polarization, e.g. create opposite domain regions or orient all the domains in the same direction (form a single domain structure) by applying high electric fields, of the order of 20kV/mm at room temperature. During this process, named electric-field domain inversion or poling, the Li ⁺ ions move across the oxygen planes while the Nb ⁵⁺ ions are displaced between two consecutive oxygen planes, and the distances between the atoms change [X. Zhang et al., Materials Science and Engineering B vol.120, p. 21 (2005)]. Fig. 3 shows the ferroelectric LiNb0 ₃ structure of oppositely oriented domains (up and down spontaneous polarization). LiNb0 ₃ also possesses pyroelectric, piezoelectric, photorefractive and nonlinear optical properties. The pyroelectric effect consists in a change of the spontaneous polarization upon temperature and it is characterised by the pyroelectric coefficient (p,) which, for LiNb0 ₃ , is about -4x10 ^"5 C/(m ² K). In reality p, depends on temperature as it is shown by Y.V. Shaldinfor for the range below 300K [Y.V. Shaldin, Crystallography Reports vol.53, p.847 (2008)]. When the temperature changes the Li ⁺ and Nb ⁵⁺ ions move with respect to the oxygen planes. In particular when the temperature decreases the Li ⁺ and Nb ⁵⁺ ions move further toward the c+ face, i.e. P _s increases and the c+ face becomes more positive while the c- face becomes more negative. The opposite happens when the temperature is increased. The created polarization bound charge induces internal electric fields of about 0.15 kV/(mm K), if the change in temperature is fast enough not to allow free charges to arrive on the surface and thus compensate for the induced polarization charges. Note that the pyroelectric effect produces the largest charge density on the face of the crystal when it is cut such that the face is orthogonal to the c-axis, i.e. the angle between the orthogonal axis to the face and the c-axis is zero. The pyroelectric effect at low temperature (<300K) has been investigated showing that the electric fields induced might generate internal electrical breakdown, thus providing extra free charge and different screening situations for the spontaneous polarization [S.L. Bravina et al., Ferroelectrics vol.298, p.31 (2004)]. When the temperature variation is sufficiently fast and large (e.g. 100K) the internal electric fields due to the pyroelectric effect might reach values close to the coercive field of the crystal, i.e. the field needed to switch the domains (spontaneous polarization). In that case, as it happens for domain inversion by applying external electrical fields, the polarization charge change can reach values of 1 .44 C/m ² .

The piezoelectric effect consists in a change of spontaneous polarization due to application of pressure (stress) for example through a mechanical deformation. As it is the case of the pyroelectric effect polarization charges are induced.

Note that when the spontaneous polarization changes, be it for example through the pyroelectric, piezoelectric or domain inversion, bound charges are generated which create electric fields. This is always accompanied by the attraction or generation of free charges which compensate (neutralize) the bound charges. The speed of the charge compensation (neutralization) depends on the effect and external conditions. For example the process is slow in vacuum in the case of the pyroelectric effect and it is practically instantaneous in the case of domain inversion by applying external electric fields using voltage generators, which also provide the free charges.

Superconductivity requires strong interactions between charge carriers and lattice vibrations (phonons). LiNb0 ₃ as well as other ferro-electric materials carry optical phonon modes which are strongly coupled to the electronic degree of freedom. In addition, the lithium ions under temperature changes become very reactive and mobile, thus increasing the chance of intercalation in the graphene. In the presence of strong electrical fields, the AB03 crystals could show a superconductive behaviour (K. Ueno et al., Nature Materials vol. 7 page 855 (2008)).

Other ferroelectric AB0 ₃ crystals possess properties similar to LiNb0 ₃ and could be used for the purpose of the invention. These include LiTa0 ₃ , Lil0 ₃ , Β3 _χ 8η_ _χ Τί0 _3, Pb(Zr _x Ti ₁ . _x )0 ₃ , with x varying between 0 and 1 .

An embodiment of the electronic or optoelectronic platform according to the invention can be seen in Figs. 4 to 6. A two-dimensional conductor consisting of a sheet of carbon atoms with a thickness of one to 4 atoms is deposited on a face of a lithium niobate crystal prepared by known means with a face whose orthogonal axis is up to 35 ⁵ oriented with respect to the c-axis of the crystal The fabrication process of the devices starts with the cleaning of the lithium niobate substrates employing well known procedure in semiconductor fabrication both wet (e.g acetone and isopropanol sonication, cleaning in an alkaline soap, ΝΗ4θΗ :Η2θ2:Η ₂ 0 solution) and dry (e.g. plasma cleaning with oxygen). After substrate preparation, graphene can be deposited by known techniques directly on top of the substrate surface either before the electrical contact fabrication or after their deposition. One or a plurality of atom thick layers (each between 0.3 and 0.4 nm thick) are deposited. The fabrication of the contacts is typically made by physical vapor deposition techniques (e.g evaporation, sputtering etc.) by depositing for instance a layer of chromium, titanium or nickel with a thickness ranging from 1 to 50 nm and on top of it a layer of gold having a thickness ranging from 10 to 1000 nm. The patterning of graphene to obtain the desired shape, e.g. hall bars with typical dimensions as in fig.6, is carried out by first depositing a very thin layer of a protecting material, typically an aluminum layer ranging from 1 to 20 nm, most commonly 3 nm. After the protective layer deposition, the pattern of the device is defined by resist photolithography. After the development the photoresist remains on top of the graphene to protect it during the following step. The unprotected graphene is etched away in a reactive ion etching oxygen plasma system with techniques well known in the literature and the final shapes of the graphene layer obtained. After this step the resist can be left as a protection in the case of graphene on top of the contacts or removed to further proceed with the fabrication. After the fabrication process the chip is inserted into a cryogenic chamber in vacuum where it is electrically connected according to the scheme in Fig. 5. Note that the external resistance R in the figure is much larger than the resistance of the graphene layer between the two points where the voltage V is measured. The typical value of that resistance is R= 1 Mohm in order to obtain a current of the order of 1=1 μΑ when the generator is set to 1 V. To obtain the resistance value of the graphene a four point probe measurement technique can be used as indicated in Fig 5 and it is calculated by dividing the voltage V measured by the voltage probes by the current I. An important step in order to obtain a very low resistance device includes a process, e.g. pyroelectric effect, piezoelectric effect, domain inversion, that can induce changes in the spontaneous polarization, thus bound charges in proximity to the crystal's surface and the graphene layer. As a consequence free charges are drawn into the graphene layer which increases their electrical conductivity. For example the process can rely on the pyroelectric effect by a thermal cycling applied in the cryostat. In Fig. 7 it is shown that a proper thermal cycling (bottom) induces jumps in the measured resistance until this reaches stably a value close to zero. The cycle consists at least of a decrease of at least 1 K/min from room temperature to a temperature below the critical temperature, i.e. the temperature at which the transition from normal to low electrical resistance state occurs, e.g. about 170-180K in our case. The cycle can also consists of a number of cycles to induce the low resistance state, with a temperature ranging from a minimum of 1 K to a maximum of 600K, being typically between 10K to 300K. The number of cycles needed to induce the low resistance state can range from 1 to 100 with a typical value of 5 while the temperature ramp rate can range from 1 K/min to 15K/min being typically 5K/min. Note that after being reached the low resistance state is maintained during subsequent cycles. Fig. 8 shows that the designed platform reached practically zero electrical resistance and the range over which it is maintained close to zero reduces for increasing temperature. At a temperature around 170-180K this range becomes negligible and correspondingly the resistance starts increasing (deviating from zero). The initial resistance before the thermal cycling was about 2kQ, after the thermal cycle in the low resistance state (below 170-180K) the resistance becomes lower than 50mQ and in the normal resistance state (above 170-180K) is always less than 20Ω. The latter value corresponds to a level of doping (carrier concentration) in graphene of the order of 10 ¹⁴ cm ^"2 . The actual resistance in the low resistance state can be even smaller than 50mQ which is the current resolution of the system. This low resistance is likely to be mediated by the lattice vibrations (phonons) of the ferroelectric material or the enhanced carrier-phonon interactions in the graphene itself, which are enhanced by the increased carrier concentration.

In this text, the term "comprises" and its derivations (such as "comprising", etc.) should not be understood in an excluding sense, that is, these terms should not be interpreted as excluding the possibility that what is described and defined may include further elements, steps, etc.

On the other hand, the invention is obviously not limited to the specific embodiment(s) described herein, but also encompasses any variations that may be considered by any person skilled in the art (for example, as regards the choice of materials, dimensions, components, configuration, etc.), within the general scope of the invention as defined in the claims.