NOTCH ADAPTED CONTACT RING SEAL AND THIEF ELECTRODE

BACKGROUND OF THE INVENTION

[0001] Manufacture of semiconductor integrated circuits and other micro-scale devices typically requires formation of multiple metal layers on a wafer or other substrate. By electroplating metals layers in combination with other steps, such as planarizing, etching and photolithography, patterned metal layers forming the micro- scale devices are created.

[0002] Electroplating is performed with the substrate, or one side of the substrate, in a bath of liquid electrolyte, and with electrical contacts touching a conductive layer on the substrate surface. Electrical current is passed through the electrolyte and the conductive layer. Metal ions in the electrolyte deposit or plate out onto the substrate, creating a metal film on the substrate. The metal ions also tend to plate out onto the electrical contacts as well. This affect, referred to as "plate-up", changes the electric field around the contacts, causing non-uniform plating. The metal plated onto the electrical contacts consequently must be removed, adding to the time requirements and complexity of the manufacturing process.

[0003] So called dry or closed contact rings have been developed to avoid plate- up of the contacts. In these designs, a seal seals the electrolyte away from the electrical contacts. The seal contacts the substrate surface radially inwardly of the electrical contacts, so that the contacts remain isolated from the electrolyte. Industry specifications for plating with a sealed contact ring increasingly require that the annular band at the edge of the wafer covered by the seal must be as small as possible, currently towards about 1 mm. To plate wafers having a notch in the edge of the wafer (to indicate a specific crystal orientation of the wafer material), the seal correspondingly must have an inward protrusion at the notch to maintain a continuous seal against the wafer. During electroplating, electric current is crowded at the notch due to the irregular geometry. This causes the plated film to be thicker around the notch than at the rest of the wafer. The yield of the wafer may therefore be reduced since the thicker plated film around the notch may negatively affect subsequent processing steps.

[0004] Accordingly, engineering challenges remain in electroplating wafers and similar work pieces having edge irregularities, such as a notch.

SUMMARY OF THE INVENTION

[0005] Current crowding resulting in thicker plating in the region of the notch is reduced or eliminated by increasing the influence of a current thief electrode at the region of the notch. A recess may be provided in the contact ring, or in the seal of the contact ring, or both. The recess provides a larger flow path through the electrolyte from the region of the notch on the wafer to the current thief electrode, causing the current electrode thief to draw more current from the region of the notch, relative to the rest of the wafer.

[0006] In a first design, an electro-processing apparatus has a thief current electrode operating with a contact ring having a seal, to compensate for electric field distortions created by a notch (or other irregularity) on the wafer or work piece. The shape of the seal is changed to provide a localized area around the notch having a greater exposure to the thief electrode. The thief electrode consequently draws more current preferentially away from the region of the notch, improving plating uniformity. In a first aspect, a contact ring has a seal with a thin section at the notch. The shape of the seal at the notch is changed, relative to the rest of the seal, to reduce current crowding at the notch. The change in the shape of the seal at the notch reduces the resistance of current path between the thief electrode and the wafer edge to increase thief electrode current drawn from the region of the notch. As a result, the wafer is plated with a film having more uniform thickness.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Fig. 1 is a schematic drawing of an electroplating apparatus.

[0008] Fig. 2 is a schematic drawing of the contact ring of the electroplating apparatus shown in Fig. 1 .

[0009] Fig. 3 is an enlarged detail view of a section of the seal on the contact ring shown in Fig. 2.

[0010] Fig. 4 is a further enlarged detail view of tip of the seal of Fig. 3.

[0011] Fig. 5 is a perspective schematic view of the wafer shown in Fig. 4.

[0012] Fig. 6 is a perspective schematic view of the seal as shown in Fig. 2.

[0013] Fig. 7 is a schematic view of all sections of the seal in a processing position, except at the notch shown in Fig. 5.

[0014] Fig. 8 is a schematic section view of the seal of Figs. 6 and 7, at the notch.

[0015] Fig. 9 is a schematic section view of an alternative embodiment.

[0016] Fig. 10 is a perspective view of a contact ring. [0017] Fig. 1 1 is an enlarged detail section view of the electrical connection between the contact fingers on the ring contact to the chuck assembly and the rotor.

[0018] Fig. 12 is section view showing unclamping the chuck assembly of Fig. 1 1 from a rotor. DETAILED DESCRIPTION

[0019] To achieve a high yield of devices from each wafer, the edge zone which is contacted by the seal must be as small as possible. In the past, an edge zone of 2 or 3 mm (i.e., the annular ring at the wafer edge not useable for manufacturing devices) was often acceptable. With current industry requirements, the edge zone is now approaching or already at 1 mm. Referring momentarily to Fig. 5, some wafers 50 have a notch 52 (enlarged for illustration). On a 300 mm diameter wafer 50, the notch 52 extends in 1 .5 mm. Therefore, the seal used for processing these types of wafers has an inward projection at the notch to avoid plating fluid leaking through the notch. The resulting seal covers more of the wafer around the notch. This changes the electric field in the region around the notch, causing the plated film around the notch to be thicker than the plated film on the rest of the wafer, due to current crowding at the notch.

[0020] One method to improve uniformity near the notch is to remove ring contact fingers at the notch. This is effective when the plated film is thin (<0.5 microns). For films greater than 0.5 microns thick, the notch region still plates preferentially when the fingers near the notch are removed. Because the wafer is rotating during plating, special shielding or geometry modifications to components of plating apparatus that do not rotate with the wafer are not practical. [0021] The engineering challenges presented by the notch (or other edge irregularity) may be met with a seal having a flatted section at the notch. The shape of the seal at the notch is changed, relative to the rest of the seal, to reduce current crowding at the notch. The change in the seal shape changes the resistance or restriction of a thief electrode current between a thief electrode and the wafer edge. Thief electrode current is preferentially focused at the current crowding area near the notch and the film thickness uniformity is improved.

[0022] As an alternative or supplemental design feature for improving uniformity at the notch, a separate contact channel for the contact fingers in the flat region may be used. This channel can be driven to a slightly higher potential so that the plated film at the notch is more uniform with the rest of the wafer. In addition, a small external thief electrode may be imbedded in the external body of the seal near the flat. This external thief electrode may be controlled to the same potential as the rest of the ring and not require a separate power supply channel. The thieving region reduces the current crowding at the flat. The external thief electrode may be deplated during each ring maintenance step.

[0023] The techniques described above may be used for copper damascene plating with a sealed contact ring having a flat at the notch. They may also be used for wafer level packaging plating (WLP) if the electroplating apparatus has an edge thief electrode. In these applications, the seal shape at portions of the wafer circumference may be changed to allow more or less thieving in these regions. For example, while WLP wafers may not need a seal with a flat side because they have no notch, they may have regions of less open area (i.e. more photoresist coverage) around the edge of the wafer that results in current crowding and reduced plating uniformity.

[0024] Many WLP wafers have a scribe region near the notch characterized by less open area. In processing these types of wafers, a seal with a smaller cross section at the notch allows the thief electrode to act preferentially at the scribe region, improving current flux uniformity. Where partial die are not patterned on the wafer (i.e. no dummy bumps), there may be varying regions of continuous photoresist around the wafer which can also be matched with an appropriate varying ring cross section to cause the thief electrode to act more or less strongly.

[0025] Turning now in detail to the drawing, as shown in FIG. 1 , an electroplating apparatus 20 has a rotor 24 in a head 22. The rotor 24 includes a backing plate 26 and a contact ring 30 having a seal 80. Contact ring actuators 34 move the contact ring 30 vertically (in the direction T in FIG. 1), to engage the contact ring 30 and the seal 80 onto the down facing surface of a wafer or substrate 50. A bellows 32 may be used to seal internal components of the head.

[0026] The contact ring typically has metal fingers 35 that contact a conductive layer on the wafer 50. The head 22 is positioned to place the substrate 50 into a bath of liquid electrolyte held in a vessel 38 in a base 36. One or more electrodes are in contact with the liquid electrolyte. FIG. 1 shows a design having a center electrode 40 surrounded by a single outer electrode 42, although multiple concentric outer electrodes may be used. An electric field shaping unit 44 made of a di-electric material may be positioned in the vessel between the electrodes and the wafer. [0027] A membrane 60 may optionally be included, with anolyte in a lower chamber below the membrane and with catholyte in an upper chamber above the membrane 60. Electric current passes from the electrodes through the electrolyte to a conductive surface on the wafer. A motor 28 in the head may be used to rotate the wafer during electroplating.

[0028] Turning to Figs. 2-4, the seal 80 typically has an elastomer tip 84 which contacts and forms a seal against the wafer, with the tip 84 supported on, or part of, a rim 86 having a beam-like or cantilever structure. The contact fingers 35, which are typically flexible metal elements, touch the wafer to the outside of the seal, so that they are not exposed to the electrolyte. Conventional seals 80 generally have a uniform cross section around the entire circumference.

[0029] Referring now to Fig. 6, to compensate for current crowding at the notch 52, the present apparatus 20 may have a seal 80 having a thin section 90. In use, the wafer 50 is loaded into the apparatus 20 with the notch 52 aligned with the flat section 90. As the seal 80 rotates with the wafer 50 during processing, the flat section 90 remains aligned with the notch 52. For a 300 mm diameter wafer having an industry standard notch, the flat section may have a width AA of 25-33 mm, or 27-31 mm.

[0030] In Figs. 7-9, the gray areas represent liquid electrolyte 46 in the vessel 38. The white areas 44 represent the solid material of the field shaping unit 44. Fig. 7 shows a cross section of seal 80 around the entire circumference, except at the flat section 90. An electric current flow path through the electrolyte 46 with characteristic dimension P1 is formed between the bottom or down-facing surface 82 of the seal 80 and the top surface 48 of the field shaping unit 44. [0031] Fig. 8 shows a cross section of the seal 80 at the flat section 90. At the flat section 90, the seal 80 does not project down as far as it does over the rest of the circumference of the seal 80. As a result, the electric current flow path through the electrolyte 46 at the flat section 90 has a characteristic dimension P2, which is 20-400% or 50-200% greater than P1 . As the resistance of the P2 path is less than the P1 , the thief electrode 92 exerts a stronger influence on the electric field at the notch 52, helping to compensate for the current crowding at the notch 52.

[0032] Fig. 9 shows an alternative design having an outer current flow path 96 leading to a second or outer electrode 94. Both electrodes 92 and 94 may be connected to thief channels drawing thieving current, or the electrode 94 may act as a current thief while electrode 92 acts an anode (with the contact fingers acting as a cathode). With electrode 92 acting as an additional anode and electrode 94 acting as a current thief, current flow through section 96 is increased, allowing for better compensation for wafer offset and notch correction. The cross section area and length of the section or space 96 (which is a volume of electrolyte) influences the amount of current drawn from the wafer edge to the thief electrode 94. The cross section area of the space 96 may be increased around the notch by providing a local recess in the contact ring (which rotates with the wafer so that the recess remains aligned with the notch during plating).

[0033] Turning now to Figs. 10, 1 1 and 12, in certain newer wafer processing systems, the wafer is placed into a chuck 100 which includes a ring contact 30 with the seal 80. The chuck (with the wafer enclosed) travels through a processing system having an array of various apparatus or chambers to perform different processing steps. In this type of system, seals modified as discussed above may be matched to specific types of wafers. For example, the seal on one set of chucks for wafers may have reduced thickness regions near the scribe, and other chucks may have seals specially modified for use with wafers having dummy bumps. With this approach, no changes to the electroplating apparatus itself are needed to handle various wafers and their unique plating uniformity issues around the wafer circumference.

[0034] As used here, wafer means a substrate, for example a silicon wafer, on which microelectronic, micro-mechanical and/or micro-optical devices are formed. The techniques described above may similarly be used to reduce plating deviations caused by scribe regions.