Title:
ELECTROSTATIC DISCHARGE (ESD) PROTECTIVE CIRCUIT FOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/157117
Kind Code:
A1
Abstract:
An electrostatic discharge (ESD) protective circuit for an integrated circuit comprises a master ESD protective circuit (401), a resistor (402), and a slave ESD protective circuit (403). The master ESD protective circuit (401) at least comprises one high-voltage N-trench MOS transistor (T1). A gate, a source and a body of the high-voltage N-trench MOS transistor (T1) are grounded, and a drain of the high-voltage N-trench MOS transistor (T1) is connected to a pin pad of an integrated circuit. The slave ESD protective circuit (403) at least comprises one low-voltage N-trench MOS transistor (T2). A gate, a source and a body of the low-voltage N-trench MOS transistor (T2) are grounded, and a drain of the low-voltage N-trench MOS transistor (T2) is connected to the drain of the high-voltage N-trench MOS transistor (T1) by means of the resistor (402), and is connected to a protected circuit (404) in the integrated circuit. By means of the electrostatic discharge (ESD) protective circuit, an ESD protective circuit having a small leaked current can be implemented, thereby reducing power consumption of a system.
Inventors:
AN JIANHONG (CN)
Application Number:
PCT/CN2017/073392
Publication Date:
September 21, 2017
Filing Date:
February 13, 2017
Export Citation:
Assignee:
CHINA ACADEMY TELECOMMUNICATIONS TECHNOLOGY (CN)
International Classes:
H02H9/00
Foreign References:
| CN103515939A | 2014-01-15 | |||
| CN101102040A | 2008-01-09 | |||
| US6351362B1 | 2002-02-26 |
Attorney, Agent or Firm:
TDIP & PARTNERS (CN)
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