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Patent Searching and Data


Title:
ELEMENT MOUNTING SUBSTRATE, SEMICONDUCTOR MODULE, CAMERA MODULE, AND METHOD FOR PRODUCING ELEMENT MOUNTING SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2011/080952
Kind Code:
A1
Abstract:
An element mounting substrate (210) on which chip parts (220) are mounted is provided with an opening (300) corresponding to an area for installing a semiconductor element (120). A transparent member (310) is fitted in the opening (300), and a side surface at the outer periphery of the transparent member (310) is fixed, by an adhesive (320), to an inner wall of the element mounting substrate (210) exposing to the opening (300). Further, a second element mounting substrate (210) mounted with a lens (290) and chip parts (220) is laminated on a first element mounting substrate (110) mounted with a semiconductor element (120), through a solder ball (270). The second element mounting substrate (210) is provided with an opening (300) corresponding to an area for installing the semiconductor element (120). A transparent member (310) is fitted in the opening (300), and the outer periphery of the transparent member (310) is fixed, by an adhesive (320), to an inner wall of the second element mounting substrate (210) exposing to the opening (300).

Inventors:
USUI RYOSUKE (JP)
NAKASATO MAYUMI (JP)
TABATA OSAMU (JP)
Application Number:
PCT/JP2010/067120
Publication Date:
July 07, 2011
Filing Date:
September 30, 2010
Export Citation:
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Assignee:
SANYO ELECTRIC CO (JP)
USUI RYOSUKE (JP)
NAKASATO MAYUMI (JP)
TABATA OSAMU (JP)
International Classes:
H04N5/335; G02B7/02; H01L27/14; H01L31/02; H04N5/225
Foreign References:
JP2009239636A2009-10-15
JP4374078B22009-12-02
JP2007142058A2007-06-07
JP2009147664A2009-07-02
JP2008148222A2008-06-26
Attorney, Agent or Firm:
Hiroshi Sumiya (JP)
KADOYA HIROSHI (JP)
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