TECHNICAL FIELD

The disclosure relates to the field of power semiconductor devices, in particular trench-gate semiconductor devices and elementary cells of such devices and methods for their production. In particular, the disclosure relates to a semiconductor trench device and method for manufacturing thereof.

BACKGROUND

Power semiconductor switching devices, for example a Metal-Oxide-Semiconductor-Field- Effect-Transistor (MOSFET) or an Insulated-Gate-Bipolar-Transistor (IGBT), are integrated devices, which incorporate a large number of elementary cells. Their gate electrode can be realized either on a semiconductor surface as a planar structure (e.g., planar-gate MOSFET) or in a semiconductortrench (e.g., trench-gate MOSFET). A benefit of the trenchgate technology over the planar-gate technology is a larger cell integration density resulting in a lower device resistance. On the other hand, the trench-gate can be easier exposed to high electric fields, especially in wide-bandgap materials, e.g., in silicon carbide (SiC), which may result in poor device reliability and finally in device breakdown. Hence, it is essential to shield the trench-gate from the high electric fields and to achieve a trade-off between the effectiveness of shielding and the device resistance.

SUMMARY

This disclosure provides a solution for improved trench-gate shielding against high electric fields in a semiconductor device in order to improve device reliability.

In particular, this disclosure presents a solution for an improved trench-gate semiconductor device.

The presented solution results in improved power density and reliability, in particular when used in wide bandgap power semiconductor devices. The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

The solution presented in this disclosure presents a technique how to shield a trench-gate of a device from high electric fields and how to achieve a low device resistance. The disclosure presents a new mechanism how to electrically connect a shield below the trenchgate to a current input region. While connecting the shield below the trench-gate to the current input region on a one trench sidewall for all or just for some elementary cells decreases channel integration and finally increases the device resistance, the technique presented in this disclosure is based on a connection of the shield with the current input region without using the trench sidewall. This novel solution provides improved channel integration leading to reduced device resistance and improved device reliability.

The disclosure presents a trench-gate device with a shield which is buried in a drift region of a first doping type below the trench-gate and a method of manufacturing thereof. The shield can be implemented as a semiconductor material of a second doping type. The shield can be electrically connected with a current input region. The connection between the shield and the current input region may be implemented inside an elementary cell as stripe pillars vertically stretching from a semiconductor surface to a shield depth and orthogonal to the shield, by which a shielding grid pattern is created. The same kind of pillars produced using the same technological process and positioned around an active area of the device can be used as an edge termination. For every elementary cell both sidewalls of the trench conduct the electrical current. A consequence of the applied manufacturing method is a presence of a plug region, which extends above the shield and below a body region. Due to presence of the shield below the trench-gate and both conducting trench sidewall channels, the device exhibits excellent gate shielding properties and low resistance, respectively. The new technology has been developed for the SiC trench-gate MOSFET, but it may also be applicable to other materials, e.g., silicon (Si), gallium nitride (GaN), gallium oxide (Ga2O3), and to other devices, e.g., IGBT.

The disclosure focuses on the following key concepts that are described hereinafter in more detail. A first key concept is a trench-gate device with a shield below a trench, where the shield is electrically connected with a current input region and both trench sidewalls conduct the electrical current. The latter means that the trench sidewalls in an elementary cell are not used for the connection between the shield and the current input region. The connection between the shield and the current input region is implemented inside the elementary cell by orthogonal stripe pillars.

A second key concept are the orthogonal stripe pillars, which connect the shield below the trench-gate and the current input region. The pillars are placed inside the elementary cell. The pillars are produced in the same technological step as the shield. The pillars stretch vertically from a semiconductor surface to a trench depth. Both the pillars and the shield below the trench create a shielding grid pattern. A distance between the stripe pillars is a matter of design and has to be chosen in order to balance different device parameters.

A third key concept is the plug region, which is a consequence of an applied manufacturing method. It extends above the shield and below a body region. The plug region has an additional function, which is modulation of a channel length and of a junction-field-effect- transistor (JFET) region length.

A fourth key concept is the manufacturing method of the device. Particularly, the method for fabrication of the buried shield below the trench with the connection to the current input region inside the elementary cell is the relevant part. The method uses four key technological processes, which are trench etching, epitaxial regrowth in trenches, semiconductor surface planarization and ion implantation.

A fifth key concept is an edge termination, e.g., floated field rings (FFR), which is produced using the same technological step as the shield. Similarly to the stripe pillars, the edge termination stretches from the semiconductor surface to the shield depth. It is positioned around an active area of the device. This edge termination can be considered as a standalone sub-solution.

In order to describe the disclosure in detail, the following terms, abbreviations and notations will be used:

SiC Silicon Carbide

MOS Metal Oxide Semiconductor FET Field Effect Transistor

S source

D drain

G gate

CMP chemical-mechanical-polishing

CVD chemical-vapor-deposition

FFR floating-field rings

IGBT insulated gate bipolar transistor

JFET junction FET

SEM scanning electron microscopy

FIB focused ion beam

According to a first aspect, the disclosure relates to an elementary cell for a trench-gate semiconductor device, the elementary cell comprising: a first active area; a second active area; an inactive area separating the first active area from the second active area, the first active area and the second active area being configured for conducting an electrical current from a current input region to a current output region; a substrate of a first semiconductor doping type, the substrate being arranged at a bottom surface of the elementary cell; a drift region of the first semiconductor doping type arranged above the substrate; a control region arranged in a trench in a top surface of the elementary cell opposing the bottom surface, the trench comprising a trench-gate bottom and trench-gate side-walls adjacent to the trench-gate bottom; and a shield region of a second semiconductor doping type being arranged in the drift region, the shield region comprising a first part placed in the first active area and the second active area below the trench-gate bottom and a second part placed in the inactive area, the second part being configured to form an electrical connection with the current input region via the inactive area; wherein the shield region of the elementary cell forms a shielding structure for shielding the control region of the elementary cell from an electric field.

The purpose of the inactive area in this cell is to shield the trench and to contact the shield with the potential of the current input region.

Such an elementary cell provides the technical advantage of high gate oxide reliability, i.e., low dielectric field, and low on-state resistance achieved for the device. The bottom and corners of the trench-gate are properly shielded and both trench sidewalls conduct the electrical current. Such elementary cell thus results in improved power density and reliability. The elementary cell can be advantageously applied in wide bandgap power semiconductor devices.

In an exemplary implementation of the elementary cell, the elementary cell comprises a buffer layer placed between the substrate and the drift layer.

The buffer layer provides the advantage of design flexibility. The buffer layer may be a first deposited layer and the drift layer a second deposited layer. The elementary cell is not limited to these two layers, it understands that even more layers can be deposited. For example, the drift layer can be decomposed into a plurality of layers which have different functions. In other words, there are basically two layers, the buffer layer and the drift layer, but the number of layers is not limited to 2. There may be other layers having another function than the drift layer and the buffer layer, e.g., a recombination-enhancement layer, a current spreading layer, etc. This provides a high degree of design flexibility when designing the elementary cells and the trench-gate semiconductor device.

In an exemplary implementation of the elementary cell, the second part of the shield region forms a stripe-shaped pillar separating the trench from the inactive area.

The second part of the shield region thus terminates the trench in the active area.

An advantage of the stripe-shaped pillars is that they connect the shield below the trenchgate and the current input region. The pillars are placed inside the elementary cell. These pillars can be produced in the same technological step as the shield, thereby reducing complexity of the manufacturing process. The pillars can stretch vertically from the semiconductor surface, i.e., the top surface of the elementary cell, to a trench depth. Both the pillars and the shield below the trench create a shielding grid pattern to provide improved shielding characteristics. A distance between the stripe pillars can be flexibly designed and chosen in order to advantageously balance different device parameters.

In an exemplary implementation of the elementary cell, the trench extends along a direction of the elementary cell; and the second part of the shield region extends orthogonally to the direction of the elementary cell.

Note that the direction of the elementary cell is referred to with reference sign 104 in Figure 1 described below. It corresponds to the direction of z-axis in Figure 1. This provides the advantage that the elementary cell can be optimally shielded against electric fields from different directions.

In an exemplary implementation of the elementary cell, the first part of the shield region is placed below the trench-gate bottom and alongside both trench-gate side walls.

The shield below the gate trench protects the gate oxide at the bottom and in the corners of the gate trench from high electric fields. The protection of the gate oxide from the high electric fields prevents from early oxide dielectric breakdown and results in high device reliability.

In an exemplary implementation of the elementary cell, the elementary cell comprises: a plug region of the first semiconductor doping type, embedded in the drift region, the plug region extending above the first part of the shield region alongside the trench-gate sidewalls; a body region of the second semiconductor doping type, embedded in the drift region, the body region extending above the plug region alongside the trench-gate side-walls; and a source region of the first semiconductor doping type, the source region being embedded in the body region and extending alongside the trench-gate side-walls.

The plug region, which is a consequence of the applied manufacturing method, provides the following advantages. The plug region can modulate the channel length and the JFET length. The doping and depth and width of the plug region, combined with the parameters of the shield and of the gate trench, give plenty of possibilities for device optimization in terms of the resistance and reliability.

In an exemplary implementation of the elementary cell, the body region is configured to form a channel on the trench-gate side-walls between the source region and the plug region, the plug region being configured to modulate a channel length.

This provides the advantage that the characteristics of the channel can be influenced by the design of the body region together with the plug region design.

In an exemplary implementation of the elementary cell, the elementary cell comprises: a body contact region embedded in the body region, the body contact region being arranged in parallel to the source region. Such a body contact region provides the technical advantage of suppressing a turn-on of a parasitic bipolar junction transistor built by the current input region (emitter), body region (base) and drift region (collector), by setting the electrical potential of the base close to the electrical potential of the emitter.

In an exemplary implementation of the elementary cell, the trench-gate bottom is formed to indent into the first part of the shield region.

This provides the advantage of design flexibility. In one design the trench-gate bottom is formed to indent into the first part of the shield region, while in another design, the trenchgate bottom is formed not to indent into the first part of the shield region.

In an exemplary implementation of the elementary cell, the body region extends laterally from the trench-gate side walls to an edge of the elementary cell; and the plug region is spaced apart from the edge of the elementary cell.

The depth and width of the plug region together with its doping, combined with the parameters of the shield and of the gate trench, give plenty of possibilities for device optimization in terms of resistance and reliability.

The above-described elementary cell is also referred herein to as elementary cell and respective trench-gate semiconductor device according to a first embodiment.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment 2, the first semiconductor doping type comprises an n-type semiconductor doping and the second semiconductor doping type comprises a p-type semiconductor doping; or the first semiconductor doping type comprises a p-type semiconductor doping and the second semiconductor doping type comprises an n-type semiconductor doping.

A trench-gate semiconductor device comprising such elementary cells according to the first alternative and a trench-gate semiconductor device comprising such elementary cells according to the second alternative can advantageously form a complementary pair of devices, which may serve as a base for the CMOS technology. In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

3, the substrate is of the first semiconductor doping type to form an elementary cell of a trench-gate MOSFET device or of the second semiconductor doping type to form an elementary cell of a trench-gate IGBT device.

This provides the advantage that from its principle of operation, IGBT offers lower static (conduction) power losses than MOSFET. IGBT enables higher current densities than MOSFET or alternatively higher blocking voltages at the same current densities as MOSFET.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

4, any of the substrate, the buffer layer and the drift layer is made of one of the following semiconductor materials: silicon carbide, silicon, gallium nitride, gallium oxide or diamond.

The advantage of this Embodiment 4 is that a material or materials with optimum electrical or thermal parameters can be used for certain device applications.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

5, the shield region is made of another material than the drift region.

The advantage of this Embodiment 5 is that a device may become cheaper in fabrication or may gain better electrical properties, if alternative materials are used for the shield region.

The shield region may be produced using one or more semiconductor or non-semiconductor materials different than the drift layer, e.g., the shield region may be produced using polysilicon.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

6, the trench-gate bottom is spaced apart from the first part of the shield region.

This means that the trench-gate bottom does not indent into the shield region, i.e., there is a distance between trench-gate bottom and shield region.

The advantage of this Embodiment 6 is a structure, where the shield has no direct contact with the trench but it is still connected to the current input region using the orthogonal pillars, which can easily be distinguished and recognized in the product. Besides, this structure provides improved electrical performance.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

7, the plug region extends laterally from the trench-gate side walls up to an edge of the elementary cell.

The advantage of this seventh embodiment is a lower device resistance since the plug region counter-dopes the body region in its whole length. The counter-doping can reduce the ion implantation tail of the body region and hence it can reduce the JFET resistance between the shield region and the body region.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

8, the body contact region is embedded in the entire second part of the shield region.

The advantage of this eighth embodiment is a structure which is easier to fabricate, particularly wider orthogonal body contact region may ease device processing or improve its reliability. In addition, this eighth embodiment enables to design the orthogonal stripe pillar of a smaller width than for the first embodiment and to use the device active area more optimally.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

9, the source region of the first semiconductor doping type counter-dopes the second part of the shield region.

The advantage of this ninth embodiment is a device structure which is easier to fabricate, particularly, the replacement of the rectangular structures with the stripe structures for the source region 7 and the elimination of the narrow orthogonal body contact region 468 may ease or improve the photolithography process.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

10, the body contact region is embedded in the entire second part of the shield region and the source region of the first semiconductor doping type counter-dopes the second part of the shield region. The tenth embodiment of the device is thus a combination of the eighth embodiment and the ninth embodiment.

The advantage of this tenth embodiment is a device structure which is easier to fabricate, particularly the replacement of the rectangular structures with the stripe structures for the source region and the wider orthogonal body contact region ease or improve the photolithography process.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

11 , the body contact region forms a plurality of rectangular contacts which are surrounded by the source region.

The advantage of this eleventh embodiment is a smaller cell pitch of the elementary cell. As a result, the cell integration can increase and the device resistance decreases.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

12, the trench extends from the first active area through the inactive area to the second active area of the elementary cell.

The advantage of this twelfth embodiment is a smaller cell pitch of the elementary cell due to the source region and the body contact region arrangement.

In addition, removal of the semiconductor material everywhere along the stripe cell during the trench-gate etching process (the shield region broken into a plurality of contacts) increases the channel density. As a result, the device resistance decreases. Moreover, patterning of long stripes instead of short stripes during the photolithography and trench etching eases the fabrication process and makes it more reliable.

In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment

13, the shield region is formed using deep ion implantation into the drift region.

The advantage of this thirteenth embodiment is that the manufacturing method for producing such elementary cell and respective trench-gate semiconductor device using deep ion implantation is less complex and cheaper. In an exemplary implementation of the elementary cell, referred hereinafter as Embodiment 14, the trench-gate bottom and the first part of the shield region partially overlap.

This provides the advantage that it enables preferential current conduction on one trench sidewall, which is beneficial for the materials with anisotropic electrical properties, for example for those where the carrier mobility is different on different crystallographic planes.

According to a second aspect, the disclosure relates to a trench-gate semiconductor device comprising: an array of elementary cells according to the first aspect described above; wherein the shield regions of the array of elementary cells are interconnected to form a shielding grid for shielding the control regions of the array of elementary cells from an electric field.

The technical advantages of such a trench-gate semiconductor device are high gate oxide reliability, low dielectric field and low on-state resistance achieved for the device. The bottom and corners of the trench-gate are properly shielded and both trench sidewalls conduct the electrical current.

In an exemplary implementation of the trench-gate semiconductor device, the trench-gate semiconductor device comprises: an edge termination of the second semiconductor doping type surrounding the array of elementary cells, wherein the edge termination forms part of the second part of the shield region.

Note that the edge termination is arranged outside of the elementary cell.

The edge termination may comprise a plurality of edge termination regions.

The edge termination surrounds the array of elementary cells. In a very special case, the edge termination may even surround a single elementary cell.

The edge termination may extend from the top surface of the elementary cell until a depth of the shield region.

An advantage of the edge termination is that it reduces the electric field at the edge of the trench-gate semiconductor device, i.e., outside of the array of elementary cells. According to a third aspect, the disclosure relates to a method for producing an elementary cell for a trench-gate semiconductor device, the method comprising: providing a substrate comprising a bottom surface and a top surface opposing the bottom surface, the substrate comprising a drift layer of a first semiconductor doping type arranged at the top surface; forming a shield region in the drift layer by: removing material of the drift layer from the top surface of the substrate to form a first intermediate device having a first trench; applying a first material layer of a second semiconductor doping type onto the top surface of the first intermediate device and planarizing the top surface to provide a second intermediate device, the second intermediate device having a top surface and a bottom surface opposing the top surface, the bottom surface corresponding to the bottom surface of the substrate; removing material from the top surface of the second intermediate device to form a third intermediate device having a second trench; applying a second material layer of the first semiconductor doping type onto the top surface of the third intermediate device and planarizing the top surface to provide a fourth intermediate device, the fourth intermediate device having a top surface and a bottom surface opposing the top surface, the bottom surface corresponding to the bottom surface of the substrate; ion implantation in the top surface of the fourth intermediate device to form a fifth intermediate device; and removing material from the ion-implanted top surface of the fifth intermediate device to form a final device having a third trench, the final device providing the elementary cell for the trenchgate semiconductor device.

When applying the first material layer onto the top surface of the substrate, the first material is applied not only onto the first trench but on the whole top surface. The first material thus fills the first trench and produces a non-uniform surface hence planarization is needed to make the surface planar.

The same applies for applying the second material layer onto the top surface of the third intermediate device.

Such method provides the advantage of fabrication of a buried shield below the trench with the connection to the current input region inside the elementary cell. The method can be implemented by using four key technological processes, which are trench etching, epitaxial regrowth in trenches, semiconductor surface planarization and ion implantation.

The method provides the advantage of producing an elementary cell for a trench-gate semiconductor device in which the trench-gate is shielded from high electric fields and which achieves a low device resistance. The method provides advantage of electrically connecting the shield below the trench-gate to the current input region (e.g., source region and to the respective source electrode). This method increases channel integration and decreases the device resistance by connecting the shield with the current input region without using the trench sidewall.

According to a fourth aspect, the disclosure relates to a method for producing an elementary cell for a trench-gate semiconductor device, the method comprising: providing a substrate comprising a bottom surface and a top surface opposing the bottom surface, the substrate comprising a drift layer of a first semiconductor doping type arranged at the top surface; forming a shield region in the drift layer by ion implantation in the drift layer to provide a second intermediate device, the second intermediate device having a top surface and a bottom surface opposing the top surface, the bottom surface corresponding to the bottom surface of the substrate; removing material from the top surface of the second intermediate device to form a third intermediate device having a second trench; applying a second material layer of the first semiconductor doping type onto the top surface of the third intermediate device and planarizing the top surface to provide a fourth intermediate device, the fourth intermediate device having a top surface and a bottom surface opposing the top surface, the bottom surface corresponding to the bottom surface of the substrate; ion implantation in the top surface of the fourth intermediate device to form a fifth intermediate device; and removing material from the ion-implanted top surface of the fifth intermediate device to form a final device having a third trench, the final device to providing the elementary cell for the trench-gate semiconductor device.

This method according to the fourth aspect is different from the method according to the third aspect in that the first trench and first material deposition (and first planarization) do not exist, because they are replaced with the ion implantation. Thus, for better understanding, this method starts after ion implantation directly with forming the second trench and applying the second material layer, in order to have the equivalent process steps as in the method according to the third aspect.

Such method provides the same advantages as the method according to the third aspect described above. This method according to the fourth aspect provides additional design flexibility, since the first three steps of the method according to the third aspect can be replaced by the step of ion implantation. In an exemplary implementation of the method according to any of the third or fourth aspect described above, removing material of the drift layer, removing material from the top surface of the second intermediate device, and removing material from the ion-implanted top surface of the fifth intermediate device comprises trench etching; applying the first material layer comprises epitaxial regrowth in the first trench; and applying the second material layer comprises epitaxial regrowth in the second trench.

This provides the advantage that the method can be implemented by using four key technological processes, which are trench etching, epitaxial regrowth in trenches, semiconductor surface planarization and ion implantation.

In an exemplary implementation of the method according to any of the third or fourth aspect described above, the method comprises: forming a body region of a second semiconductor doping type embedded in the drift region, the body region extending alongside trench-gate side-walls of the third trench; forming a source region of the first semiconductor doping type embedded in the body region, the source region extending alongside the trench-gate sidewalls of the third trench; and forming a body contact region in parallel to the source region above the body region.

This method provides the same advantages as the corresponding features of the elementary cell manufactured by such method as described above.

According to a fifth aspect, the disclosure relates to a trench-gate semiconductor device, comprising: an array of elementary cells; a substrate of a first semiconductor doping type, the substrate being arranged at a bottom surface of the array of elementary cells; a drift region of the first semiconductor doping type arranged above the substrate; an edge termination of a second semiconductor doping type surrounding the array of elementary cells, wherein the edge termination is embedded in the drift region.

The purpose and technical advantage of the edge termination is to reduce the electric field at the edge of the trench-gate semiconductor device.

The edge termination may comprise a plurality of edge termination regions.

In an exemplary implementation of the trench-gate semiconductor device, the trench-gate semiconductor device comprises: a first active area; a second active area; an inactive area separating the first active area from the second active area, the first active area and the second active area being configured for conducting an electrical current from a current input region to a current output region; a control region arranged in a trench in a top surface of the elementary cell opposing the bottom surface, the trench comprising a trench-gate bottom and trench-gate side-walls adjacent to the trench-gate bottom; and a shield region of a second semiconductor doping type being arranged in the drift region, the shield region comprising a first part placed in the first active area and the second active area below the trench-gate bottom and a second part placed in the inactive area, the second part being configured to form an electrical connection with the current input region via the inactive area; wherein the shield region of the elementary cell forms a shielding structure for shielding the control region of the elementary cell from an electric field.

This trench-gate semiconductor device provides the same advantages as the corresponding elementary cell described above.

In an exemplary implementation of the trench-gate semiconductor device, the edge termination forms part of the second part of the shield region.

An advantage of this edge termination is that the edge termination can be manufactured in the same production step as the forming of the second part of the shield region. This facilitates production of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the disclosure will be described with respect to the following figures, in which:

Fig. 1 shows a 3D structure of an elementary cell 100 for a trench-gate semiconductor device according to the disclosure;

Fig. 2a shows a cross section of the elementary cell 100 of Figure 1 ;

Fig. 2b shows another cross section of the elementary cell 100 of Figure 1 in a direction which is orthogonal to a direction of the elementary cell; Fig. 2c shows a top view of the elementary cell 100 of Figure 1 ;

Fig. 3 shows a cross section of a trench-gate semiconductor device 200 according to a first embodiment;

Fig. 4a shows a schematic diagram of a method 400a according to a first embodiment for producing an elementary cell for a trench-gate semiconductor device;

Fig. 4b shows a schematic diagram of a method 400b according to a second embodiment for producing an elementary cell for a trench-gate semiconductor device;

Fig. 5a shows a 3D structure of a first intermediate device 500a having a first trench 501 at its top surface 102 corresponding to the structure after the etching step 401 of the method 400a;

Fig. 5b shows a 3D structure of a second intermediate device 500b produced by any of the methods 400a and 400b according to Figures 4a and 4b, corresponding to the structure after the regrowth 402 step and planarization step 403 of the method 400a or corresponding to the structure after the ion implantation 404 step of the method 400b;

Fig. 5c shows a 3D structure of a third intermediate device 500c with a second trench 503a, 503b at its top surface, corresponding to the structure after the etching step 405 of the method 400a or 400b;

Fig. 5d shows a 3D structure of a fourth intermediate device 500d produced by any of the methods 400a and 400b according to Figures 4a and 4b, corresponding to the structure after the regrowth 406 step and planarization step 407 of the method 400a or 400b;

Fig. 5e shows a 3D structure of a fifth intermediate device 500e with ion implantation in its top surface, corresponding to the structure after the ion implantation step 408 of the method 400a or 400b;

Fig. 5f shows a 3D structure of a final device 500f that may correspond to the trench-gate semiconductor device 100 produced by any of the methods 400a and 400b according to Figures 4a and 4b, corresponding to the structure after the etching 409 step of the method 400a or 400b; Fig. 6 shows a cross section of a trench-gate semiconductor device 600 with edge termination 602 according to the disclosure;

Fig. 7a shows a cross section of an elementary cell 700 according to a sixth embodiment;

Fig. 7b shows another cross section of the elementary cell 700 according to the sixth embodiment in a direction which is orthogonal to a direction of the elementary cell;

Fig. 7c shows a top view of the elementary cell 700 according to the sixth embodiment;

Fig. 8a shows a cross section of an elementary cell 800 according to a seventh embodiment;

Fig. 8b shows another cross section of the elementary cell 800 according to the seventh embodiment in a direction which is orthogonal to a direction of the elementary cell;

Fig. 8c shows a top view of the elementary cell 800 according to the seventh embodiment;

Fig. 9a shows a cross section of an elementary cell 900 according to an eighth embodiment;

Fig. 9b shows another cross section of the elementary cell 900 according to the eighth embodiment in a direction which is orthogonal to a direction of the elementary cell;

Fig. 9c shows a top view of the elementary cell 900 according to the eighth embodiment;

Fig. 10a shows a cross section of an elementary cell 1000 according to a ninth embodiment;

Fig. 10b shows another cross section of the elementary cell 1000 according to the ninth embodiment in a direction which is orthogonal to a direction of the elementary cell;

Fig. 10c shows a top view of the elementary cell 1000 according to the ninth embodiment;

Fig. 11a shows a cross section of an elementary cell 1100 according to a tenth embodiment;

Fig. 11 b shows another cross section of the elementary cell 1100 according to the tenth embodiment in a direction which is orthogonal to a direction of the elementary cell; Fig. 11c shows a top view of the elementary cell 1100 according to the tenth embodiment;

Fig. 12a shows a cross section of an elementary cell 1200 according to an eleventh embodiment;

Fig. 12b shows another cross section of the elementary cell 1200 according to the eleventh embodiment in a direction which is orthogonal to a direction of the elementary cell;

Fig. 12c shows a top view of the elementary cell 1200 according to the eleventh embodiment;

Fig. 13a shows a cross section of an elementary cell 1300 according to a twelfth embodiment;

Fig. 13b shows another cross section of the elementary cell 1300 according to the twelfth embodiment in a direction which is orthogonal to a direction of the elementary cell;

Fig. 13c shows a top view of the elementary cell 1300 according to the twelfth embodiment;

Fig. 14 shows a 3D structure of the elementary cell 1300 according to the twelfth embodiment;

Fig. 15a shows a cross section of an elementary cell 1500 according to a fourteenth embodiment;

Fig. 15b shows another cross section of the elementary cell 1500 according to the fourteenth embodiment in a direction which is orthogonal to a direction of the elementary cell; and

Fig. 15c shows a top view of the elementary cell 1500 according to the fourteenth embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

The semiconductor devices described herein may be implemented in various applications, e.g., in power conversion devices for automotive and industrial applications. The described semiconductor devices may be applied in integrated circuits and/or modules and power applications and may be manufactured according to various technologies. For example, the semiconductor devices may be utilized in logic integrated circuits, power modules, analog integrated circuits, mixed signal integrated circuits, optical circuits, memory circuits and/or integrated passives.

Fig. 1 shows a 3D structure of an elementary cell 100 for a trench-gate semiconductor device according to the disclosure. The elementary cell 100 comprises a first active area 110a and a second active area 120a which are separated by an inactive area 115.

Figures 2a, 2b and 2c show the same structure as presented in Fig. 1 as an elementary cell cross-section, as a cross-section in a direction which is orthogonal to a direction of the elementary cell and as a top view, respectively. All the figures show just the semiconductor material with the doped regions and the trench region.

The elementary cell 100 shown in Figure 1 and Figures 2a to 2c comprise a first active area 110a; a second active area 120a; and an inactive area 115 separating the first active area 110a from the second active area 120a. The first active area 110a and the second active area 120a are configured for conducting an electrical current from a current input region to a current output region.

The elementary cell 100 comprises a substrate 1 of a first semiconductor doping type. The substrate 1 is arranged at a bottom surface 101 of the elementary cell 100. The elementary cell 100 comprises a drift region 3 of the first semiconductor doping type arranged above the substrate 1 .

The elementary cell 100 comprises a control region arranged in a trench 111 , 121 in a top surface 102 of the elementary cell 100 opposing the bottom surface 101. The trench 111 , 121 comprises a trench-gate bottom 9a and trench-gate side walls 9b adjacent to the trenchgate bottom 9a.

The elementary cell 100 comprises a shield region 4a, 4b of a second semiconductor doping type which is arranged in the drift region 3. The shield region 4a, 4b comprises a first part 4b placed in the first active area 110a and the second active area 120a below the trenchgate bottom 9a and a second part 4a placed in the inactive area 115. The second part 4a is configured to form an electrical connection with the current input region via the inactive area 115.

The shield region 4a, 4b of the elementary cell forms a shielding structure for shielding the control region of the elementary cell 100 from an electric field.

The purpose of the inactive area 115 in this cell 100 is to shield the trench and to contact the shield with the source potential, i.e., the potential of the current input region.

The elementary cell 100 may comprise a buffer layer 2 placed between the substrate 1 and the drift layer 3.

The second part 4a of the shield region 4a, 4b may form a stripe-shaped pillar separating the trench 111 , 121 from the inactive area 115.

The second part 4a of the shield region 4a, 4b may thus terminate the trench 111 , 121 in the active area 110a, 120a.

The trench 111 , 121 may extend along a direction 104 of the elementary cell 100. The second part 4a of the shield region 4a, 4b may extend orthogonally to the direction 104 of the elementary cell 100. Note that the direction of the elementary cell is referred to with reference sign 104. It corresponds to the direction of z-axis in Figure 1.

The first part 4b of the shield region 4a, 4b may be placed below the trench-gate bottom 9a and alongside both trench-gate side walls 9b.

The elementary cell 100 may comprise a plug region 5 of the first semiconductor doping type, embedded in the drift region 3. The plug region 5 may extend above the first part 4b of the shield region 4a, 4b alongside the trench-gate side walls 9b.

The elementary cell 100 may comprise a body region 6 of the second semiconductor doping type, embedded in the drift region 3. The body region 6 may extend above the plug region 5 alongside the trench-gate side walls 9b.

The elementary cell 100 may comprise a source region 7 of the first semiconductor doping type. The source region 7 may be embedded in the body region 6 and may extend alongside the trench-gate side walls 9b.

The body region 6 may be configured to form a channel on the trench-gate side walls 9b between the source region 7 and the plug region 5. The plug region 5 may be configured to modulate a channel length.

The elementary cell 100 may comprise a body contact region 8 embedded in the body region 6. The body contact region 8 may be arranged in parallel to the source region 7.

The trench-gate bottom 9a may be formed to indent into the first part 4b of the shield region.

The body region 6 may extend laterally from the trench-gate side walls 9b to an edge of the elementary cell 100. The plug region 5 may be spaced apart from the edge of the elementary cell 100.

According to a second embodiment of the elementary cell 100, the first semiconductor doping type may comprise an n-type semiconductor doping and the second semiconductor doping type may comprise a p-type semiconductor doping. Alternatively, the first semiconductor doping type may comprise a p-type semiconductor doping and the second semiconductor doping type may comprise an n-type semiconductor doping. A trench-gate semiconductor device 100 comprising such elementary cells according to the first alternative and a trench-gate semiconductor device 100 comprising such elementary cells according to the second alternative can form a complementary pair of devices, which may serve as a base for the CMOS technology.

According to a third embodiment of the elementary cell 100, the substrate 1 can be of the first semiconductor doping type to form an elementary cell 100 of a trench-gate MOSFET device. Alternatively, the substrate 1 can be of the second semiconductor doping type to form an elementary cell 100 of a trench-gate IGBT device.

According to a fourth embodiment of the elementary cell 100, any of the substrate 1 , the buffer layer 2 and the drift layer 3 can be made of one of the following semiconductor materials: silicon carbide, silicon, gallium nitride, gallium oxide or diamond.

According to a fifth embodiment of the elementary cell 100, the shield region 4a, 4b can be made of another material than the drift region 3.

The shield region may be produced using one or more semiconductor or non-semiconductor materials different than the drift layer, e.g., the shield region may be produced using polysilicon.

According to a sixth embodiment of the elementary cell 100 as exemplarily shown in Figures 7a, 7b and 7c, the trench-gate bottom 9a may be spaced apart from the first part 4b of the shield region.

This means that the trench-gate bottom 9a does not indent into the shield region 4b, i.e., there is a distance between trench-gate bottom 9a and shield region 4b

According to a seventh embodiment of the elementary cell 100 as exemplarily shown in Figures 8a to 8c, the plug region 5 may extend laterally from the trench-gate side walls 9b up to an edge of the elementary cell 100.

According to an eighth embodiment of the elementary cell 100 as exemplarily shown in Figures 9a to 9c, the body contact region 8 may be embedded in the entire second part 4a of the shield region. According to a ninth embodiment of the elementary cell 100 as exemplarily shown in Figures 10a to 10c, the source region 7 of the first semiconductor doping type may counter-dope the second part 4a of the shield region 4a, 4b.

According to a tenth embodiment of the elementary cell 100 as exemplarily shown in Figures 11a to 11c, the body contact region 8 may be embedded in the entire second part 4a of the shield region and the source region 7 of the first semiconductor doping type may counterdope the second part 4a of the shield region 4a, 4b.

According to an eleventh embodiment of the elementary cell 100 as exemplarily shown in Figures 12a to 12c, the body contact region 8 may form a plurality of rectangular contacts which are surrounded by the source region 7.

According to a twelfth embodiment of the elementary cell 100 as exemplarily shown in Figures 13a to 13c and Figure 14, the trench 111 , 121 may extend from the first active area 110a through the inactive area 115 to the second active area 120b of the elementary cell 100.

According to a thirteenth embodiment of the elementary cell 100, the shield region 4a, 4b may be formed using deep ion implantation into the drift region 3, as exemplarily shown in Figure 4b.

According to a fourteenth embodiment of the elementary cell 100 as exemplarily shown in Figures 15a to 15c, the trench-gate bottom 9a and the first part 4b of the shield region 4a, 4b may partially overlap.

The elementary cell 100 described above may be used for forming a trench-gate semiconductor device as described in the following.

Such a trench-gate semiconductor device may comprise an array of elementary cells 100 as described above. The shield regions 4a, 4b of the array of elementary cells 100 may be interconnected to form a shielding grid for shielding the control regions of the array of elementary cells 100 from an electric field. The trench-gate semiconductor device may be a trench-gate semiconductor device 600 as shown in Figure 6, comprising: an edge termination 602 of the second semiconductor doping type surrounding the array of elementary cells 100.

The edge termination 602 may form part of the second part 4a of the shield region 4a, 4b as shown in Figure 6.

Note that the edge termination 602 is arranged outside of the elementary cell 100.

The edge termination 602 may comprise a plurality of edge termination regions.

The edge termination surrounds the array of elementary cells 100. In a very special case, the edge termination may even surround a single elementary cell 100.

The edge termination 602 may extend from the top surface 102 of the elementary cell 100 until a depth of the shield region 4a, 4b.

An advantage of the edge termination is that it reduces the electric field at the edge of the trench-gate semiconductor device, i.e., outside of the array of elementary cells.

In the following a design implementation of the elementary cell 100 for a trench-gate semiconductor device as shown in Figure 1 is described in more detail.

In the elementary cell 100, the shield region 4b of the second doping type is placed in parallel to the direction 104 of the elementary cell and below the trench-gate bottom 9a. In the presented solution, the trench-gate bottom 9a indents into the shield region 4b.

The shield region 4a of the second doping type is orthogonal to the direction of the elementary cell and stretches up to the semiconductor top surface creating stripe pillars. The shield regions 4a and 4b build a shielding grid at a depth below the trench-gate bottom 9a. A distance between the stripe pillars of the shield region 4a is a matter of design and it can be chosen in order to balance different device parameters.

The plug region 5 of the first doping type is parallel to the direction of the elementary cell and stretches vertically between the shield region 4b and the body region 6. The plug region 5 is split by the shield region 4a. In the presented solution shown in Figure 1 , the plug region 5 stretches laterally only in some part of the drift layer 3.

The body region 6 of the second doping type is present in both the active area 110a, 120a and the inactive area 115, where in the inactive area 115 it co-dopes the shield region 4a and creates a new region 46.

The source region 7 of the first doping type is parallel to the direction 104 of the elementary cell 100 and it is placed in the upper part of the body region 6. The source region 7 is split by the shield region 4a.

The body contact region 8 of the second doping type is present in both the active area 110a, 120a and the inactive area 115 and it is placed in the upper parts of the body region 6 and the region 46. The body contact region 8 in the inactive area 115 creates a new contact region 468.

Fig. 3 shows a cross section of a trench-gate semiconductor device 200 according to a first embodiment.

The trench-gate semiconductor device 200 forms a new device structure, which is n-type SiC trench-gate MOSFET. The device structure consists of an elementary cell, e.g., an elementary cell 100 as described above with respect to Figure 1 and Figures 2a to 2c, which has a first active area 110a and a second active area 120a, and of an inactive area 115 separating the first active area 110a from the second active area 120a, e.g., as described above with respect to Figures 1 and 2a to 2c.

The active area 110a, 120a is a device part which belongs to an electrical current conduction path from top to bottom of the device. The device structure is symmetrical, where a symmetry axis is vertical.

The device 200 is fabricated on a substrate 1 of a first doping type (here n-type), on top of which a buffer layer 2 of the first doping type is deposited, on top of which a drift layer 3 of the first doping type is deposited. Both buffer layer 2 and drift layer 3 can be implemented as stacks of layers of various thickness and doping parameters. The device 200 incorporates a shield region of a second doping type, whose first part 4b is located in the elementary cell below the trench-gate bottom 9a and whose second part 4a is located in the inactive area. In the presented solution, the trench-gate bottom 9a indents into the shield region 4b.

A plug region 5 of the first doping type stretches vertically between the shield region 4b and a body region 6 of the second doping type. In the presented solution, the plug region 5 stretches laterally only is some part the drift layer 3.

A source region 7 of the first doping type is placed in an upper part of the body region 6.

A body contact region 8 of the second doping type is placed in the upper part of the body region 6 in the neighborhood of the source region 7.

The plug region 5 and the body region 6 and the source region 7 are adjacent to the trenchgate sidewalls 9b.

The trench-gate bottom 9a and the trench-gate sidewalls are covered with a gate dielectric layer 10, typically with silicon dioxide.

A metal-like gate layer 11 , typically using doped polysilicon, is deposited onto the gate dielectric layer 10 in a trench region defined by the trench-gate bottom 9a and the trenchgate sidewalls 9b, forming a gate electrode (G).

Optimally, the corners between the trench-gate bottom 9a and the trench-gate sidewalls 9b are rounded.

A low-ohmic active contact 13 is placed onto the source region 7 and the body contact region 8 and is separated from the gate layer 11 by an interlayer dielectric (ILD) 12, typically using silicon dioxide.

A metal layer 14 is deposited onto a device top surface, contacting the active contact 13 and forming a source electrode (S).

A metal layer 15 is deposited onto a device bottom surface, forming a drain electrode (D). Both metal layer 14 and metal layer 15 can be implemented as stacks of layers of various thickness and chemical composition.

The connection between the shield region 4b and the source electrode (S) is formed by the shield region 4a.

A channel may be formed in the body region 6 on the trench-gate sidewalls 9b between the source region 7 and the plug region 5. The device conducts the electrical current from the source electrode (S) to the drain electrode (D) only when the channel is open and the electrons are injected from the source region 7 to the channel. This happens when an electrical potential difference between the gate electrode (G) and the source electrode (S) is above a certain threshold voltage level and when the electrical potential of the drain (D) is higher than the electrical potential of the source (S).

The n-type SiC trench-gate MOSFET, referred to as embodiment 1 in this disclosure, contains a shield below a gate trench. The shield protects the gate oxide at the bottom and in the corners of the gate trench from high electric fields. The protection of the gate oxide from the high electric fields prevents from early oxide dielectric breakdown and results in high device reliability.

The shield is connected to the source electrode, which allows for setting the shield at an electric potential close to a source electric potential. The connection between the shield and the source electrode is made inside the elementary cell 100 using the pillars which are orthogonal to the direction of the elementary cell.

Both the shield below the trench-gate and the pillars are produced in the same technological step. The epitaxy, which is used forthe shield and pillars processing, assures high activation of the dopants and doping homogeneity in depth of the structure. The connection between the shield and the source electrode results in fast turn-off of the device and in high device reliability.

The shield is placed below the gate trench hence a pitch of the elementary cell does not increase because of the presence of the shield. The resistance of the device, which is inverse correlated with the cell pitch, may be low. The connection between the shield and the source electrode is made not on trench sidewalls, but inside the elementary cell using the pillars which are orthogonal to the direction of the elementary cell. For every elementary cell, both trench sidewalls conduct the electrical current through the channels. The resistance of the device, which is inverse correlated with the density of the current conducting channels, may be low.

The plug region, which is a consequence of the applied manufacturing method, has an additional function. It can modulate the channel length and the JFET length. The doping and depth and width of the plug region, combined with the parameters of the shield and of the gate trench, give plenty of possibilities for device optimization in terms of the resistance and reliability.

The manufacturing method enables to process the edge termination, e.g. an edge termination 602 as shown in Figure 6, without any additional effort. The edge termination, e.g., floating field rings (FFR), can be processed using the same steps as for the shield (pillars).

The complexity of the manufacturing method may be acceptable considering the achievable gain in the device current density and the improved device reliability, especially when the effective edge termination does not require any additional process.

Fig. 4a shows a schematic diagram of a method 400a according to a first embodiment for producing an elementary cell for a trench-gate semiconductor device.

The method 400a may be used for producing an elementary cell 100 for a trench-gate semiconductor device, e.g., an elementary cell 100 as described above with respect to Figures 1 and 2a to 2c.

The method 400a comprises providing a substrate 1 , 2, 3 comprising a bottom surface 101 and a top surface 102 opposing the bottom surface 101 , the substrate 1 , 2, 3 comprising a drift layer 3 of a first semiconductor doping type arranged at the top surface 102 (not shown in Figure 4a).

The method 400a comprises forming a shield region 4a, 4b in the drift layer 3 by applying the following steps: Removing material 401 of the drift layer 3 from the top surface 102 of the substrate 1 , 2, 3 to form a first intermediate device 500a having a first trench 501 , e.g., as shown in Figure 5a;

Applying 402 a first material layer 502 of a second semiconductor doping type onto the top surface 102 of the first intermediate device 500a and planarizing 403 the top surface to provide a second intermediate device 500b, e.g., as shown in Figure 5b, the second intermediate device 500b having a top surface and a bottom surface opposing the top surface, the bottom surface corresponding to the bottom surface of the substrate 1 , 2, 3;

Removing material 405 from the top surface of the second intermediate device 500b to form a third intermediate device 500c having a second trench 503a, 503b, e.g., as shown in Figure 5c;

Applying 406 a second material layer 504a, 504b of the first semiconductor doping type onto the top surface of the third intermediate device 500c and planarizing 407 the top surface to provide a fourth intermediate device 500d, e.g., as shown in Figure 5d, the fourth intermediate device 500d having a top surface and a bottom surface opposing the top surface, the bottom surface corresponding to the bottom surface of the substrate 1 , 2, 3;

Ion implantation 408, 505 in the top surface of the fourth intermediate device 500dto provide a fifth intermediate device 500e, e.g., as shown in Figure 5e; and

Removing material 409 from the ion-implanted top surface of the fifth intermediate device 500e to form a final device 500f having a third trench 111 , 121 , e.g., as shown in Figure 5f, the final device 500f may correspond to the elementary cell 100 for the trench-gate semiconductor device.

When applying the first material layer onto the top surface of the substrate, the first material is applied not only onto the first trench but on the whole top surface. The first material thus fills the first trench and produces a non-uniform surface, hence planarization is needed to make the surface planar.

The same applies for applying the second material layer onto the top surface of the third intermediate device. The above-described steps of removing material of the drift layer 3, removing material from the top surface of the second intermediate device, and removing material from the ion- implanted top surface of the fifth intermediate device may comprise trench etching as shown in Figure 4a.

The above-described step of applying the first material layer may comprise epitaxial regrowth in the first trench as shown in Figure 4a.

The above-described step of applying the second material layer may comprise epitaxial regrowth in the second trench as shown in Figure 4a.

The method 400a may further comprise forming a body region 6 of a second semiconductor doping type embedded in the drift region 3, the body region 6 extending alongside trenchgate side-walls 9b of the third trench, e.g., as described above with respect to Figure 1.

The method 400a may further comprise forming a source region 7 of the first semiconductor doping type embedded in the body region 6, the source region 7 extending alongside the trench-gate side-walls 9b of the third trench, e.g., as described above with respect to Figure 1.

The method 400a may further comprise forming a body contact region 8 in parallel to the source region 7 above the body region 6, e.g., as described above with respect to Figure 1 .

In the following, the manufacturing method 400a is described in more detail.

The manufacturing method 400a of the device may use four key technological processes, which are trench etching, epitaxial regrowth in trenches (refill), semiconductor surface planarization and ion implantation. The simplified manufacturing method is presented in Fig. 4a as a flow chart. The most important steps of the method are:

1) Etching of a first trench in a top semiconductor layer (first doping type). The layer, in which the first trench is etched, belongs to the drift layer 3, which may be implemented as a stack of layers of various thickness and doping parameters. The drift layer 3 is deposited on the buffer layer 2, which may be implemented as a stack of layers of various thickness and doping parameters. The buffer layer 2 is deposited on the substrate 1. ) Epitaxial regrowth in the first trench (second doping type). The layer might be deposited using a chemical-vapor-deposition (CVD) process. The deposited layer forms a shield region, which in the next steps will be separated into the shield region 4a and the shield region 4b. ) Surface planarization. The top of the semiconductor needs to be planarized, in order to remove completely the deposited layer from the surface and to leave it only in the trench. The planarization might be done using grinding and chemical-mechanical- polishing (CMP). ) Etching of a second trench in the active area of the device. The second trench is wider and shallower than the first trench. The shield region is separated into two parts 4a (inactive area) and 4b (active area). ) Epitaxial regrowth in the second trench (first doping type). The layer might be deposited using the chemical-vapor-deposition (CVD) process. The doping of the layer must be equal or higher than the first type doping of the drift layer 3 and must be lower than the second type doping of the body region 6. The deposited layer forms the plug region 5. ) Surface planarization. The top of the semiconductor needs to be planarized, in order to remove completely the deposited layer from the surface and to leave it only in the trench. The planarization might be done using grinding and chemical-mechanical- polishing (CMP). ) Ion implantation. The body region 6 of the second doping type is implanted in the whole area of the device, creating the region 46 in the inactive area. The source region 7 of the first doping type is implanted in a defined part of the active area, including the area above the shield region 4b. The body contact region 8 of the second doping type is implanted in defined parts of both the active area and the inactive area, creating the region 468 in the inactive area. ) Etching of a third trench in the active area of the device. The third trench is thinner and deeper than the second trench. The third trench defines the trench-gate bottom 9a and the trench-gate sidewalls 9b. Note that for the embodiment 6 the third trench is not deeper than the second trench, but is shallower. This is how the shield becomes separated from the trench-gate bottom.

9) Remaining standard steps of device fabrication. The steps include thermal annealing, gate oxidation or gate oxide deposition, gate layer deposition, processing of the ILD, processing of the active contacts, processing of the gate pad region, metallization, passivation, backside processing and others.

The intermediate steps of the manufacturing method 400a are presented in Figures 5a to 5f, where Fig. 5a shows the structure after step 1 , Fig. 5b shows the structure after steps 2 and 3, Fig. 5c shows the structure after step 4, Fig. 5d shows the structure after steps 5 and 6, Fig. 5e shows the structure after step 7, Fig. 5f shows the structure after step 8 as described below with respect to Figures 5a to 5f.

Fig. 4b shows a schematic diagram of a method 400b according to a second embodiment for producing an elementary cell for a trench-gate semiconductor device.

The method 400b corresponds to the method 400a described above with respect to Figure 4a, where the first three steps 401 , 402, 403 are replaced by an ion implantation 404.

This method 400b is different from the method 400a in that the first trench 501 and first material layer 502 and first planarization 403 do not exist, because they are replaced with an ion implantation 404 as described in the following. Thus, for better understanding, this method 400b starts after ion implantation 404 directly with forming the second trench 503a, 503b and applying the second material layer, in order to have the equivalent process steps as in the method 400a.

Hence, the method 400b for producing an elementary cell 100 for a trench-gate semiconductor device 100 comprises the following steps:

Providing a substrate 1 , 2, 3 comprising a bottom surface 101 and a top surface 102 opposing the bottom surface 101 , the substrate 1 , 2, 3 comprising a drift layer 3 of a first semiconductor doping type arranged at the top surface 102.

Forming a shield region 4a, 4b in the drift layer 3 by ion implantation 404 in the drift layer 3 to provide the second intermediate device 500b, as shown in Figure 5b, the second intermediate device 500b having a top surface and a bottom surface opposing the top surface, the bottom surface corresponding to the bottom surface of the substrate 1 , 2, 3. By this ion implantation 404 in the drift layer 3, the forming of a first intermediate device 500a can be avoided and the second intermediate device 500b can be formed immediately.

Removing material 405 from the top surface of the second intermediate device 500b to form a third intermediate device 500c as shown in Figure 5c, the third intermediate device 500c having a second trench 503a, 503b.

Applying 406 a second material layer of the first semiconductor doping type onto the top surface of the third intermediate device 500c and planarizing 407 the top surface to provide a fourth intermediate device 500d, as shown in Figure 5d, the fourth intermediate device 500d having a top surface and a bottom surface opposing the top surface, the bottom surface corresponding to the bottom surface of the substrate 1 , 2, 3.

Ion implantation 408 in the top surface of the fourth intermediate device 500d to form a fifth intermediate device 500e, as shown in Figure 5e.

Removing material 409 from the ion-implanted top surface of the fifth intermediate device 500e to form a final device 500f having a third trench 111 , 121 , as shown in Figure 5f. The final device 500f may correspond to the elementary cell 100 for the trench-gate semiconductor device 100.

The above-described steps of removing material from the top surface of the second intermediate device and removing material from the ion-implanted top surface of the fifth intermediate device may comprise trench etching as shown in Figure 4b.

The above-described step of applying the second material layer may comprise epitaxial regrowth in the second trench as shown in Figure 4b.

The method 400b may further comprise forming a body region 6 of a second semiconductor doping type embedded in the drift region 3, the body region 6 extending alongside trenchgate side walls 9b of the third trench, e.g., as described above with respect to Figure 1.

The method 400b may further comprise forming a source region 7 of the first semiconductor doping type embedded in the body region 6, the source region 7 extending alongside the trench-gate side walls 9b of the third trench, e.g., as described above with respect to Figure 1.

The method 400b may further comprise forming a body contact region 8 in parallel to the source region 7 above the body region 6, e.g., as described above with respect to Figure 1 .

Fig. 5a shows a 3D structure of a first intermediate device 500a having a first trench 501 at its top surface 102 corresponding to the structure after the etching step 401 of the method 400a.

Fig. 5b shows a 3D structure of a second intermediate device 500b produced by any of the methods 400a and 400b according to Figures 4a and 4b, corresponding to the structure after the regrowth 402 step and planarization step 403 of the method 400a or corresponding to the structure after the ion implantation 404 step of the method 400b.

Fig. 5c shows a 3D structure of a third intermediate device 500c with a second trench 503a, 503b at its top surface, corresponding to the structure after the etching step 405 of the method 400a or 400b.

Fig. 5d shows a 3D structure of a fourth intermediate device 500d produced by any of the methods 400a and 400b according to Figures 4a and 4b, corresponding to the structure after the regrowth 406 step and planarization step 407 of the method 400a or 400b.

Fig. 5e shows a 3D structure of a fifth intermediate device 500e with ion implantation in its top surface, corresponding to the structure after the ion implantation step 408 of the method 400a or 400b.

Fig. 5f shows a 3D structure of a final device 500f that may correspond to the trench-gate semiconductor device 100 produced by any of the methods 400a and 400b according to Figures 4a and 4b, corresponding to the structure after the etching 409 step of the method 400a or 400b.

Fig. 6 shows a cross section of a trench-gate semiconductor device 600 with edge termination 602 according to the disclosure. The manufacturing methods 400a, 400b described above with respect to Figures 4a and 4b can be used to process an edge termination 602 of a whole device (chip), e.g., the trenchgate semiconductor device 600 shown in Figure 6, without any additional effort. The edge termination 602, e.g., floating field rings (FFR) can be processed as the shield region 4a around the device 600. This kind of edge termination 602 shown in Figure 6 stretches vertically from the semiconductor surface to the shield depth, and it can be deeper than the trench-gate bottom 9a.

In this case, the direction of the shield region 4a is not limited to the orthogonal direction against the direction of the elementary cell. In addition, the edge termination 602 implemented as the shield region 4a may not require in its upper part the body region 6 and the body contact region 8, which create the regions 46 and 468. It may, however, contain them or just the body contact region 8 in the shield region 4a, depending on the design.

Figure 6 presents an example of such edge termination. Only the semiconductor material with the doped regions and the trench region are displayed, similarly as in Fig. 2a. The described edge termination 602 is an optional feature of the device 600. The device 600 can use any other type of the edge termination 602. This edge termination 602 can be considered as a stand-alone sub-solution. In addition, this edge termination 602 can have other variations, e.g., after etching 401 of the first trench according to the manufacturing method presented in Fig. 4a, the bottom of the trenches only in the edge termination region 602 can be implanted prior to the epitaxial regrowth, which increases the depth of the edge termination 602.

The trench-gate semiconductor device 600 of Figure 6 comprises an array of elementary cells 100 and a substrate 1 of a first semiconductor doping type. The substrate 1 is arranged at a bottom surface 101 of the array of elementary cells 100.

The trench-gate semiconductor device 600 comprises a drift region 3 of the first semiconductor doping type arranged above the substrate 1 .

The trench-gate semiconductor device 600 comprises an edge termination 602 of a second semiconductor doping type surrounding the array of elementary cells 100. The edge termination 602 is embedded in the drift region 3. The purpose and technical advantage of the edge termination 602 is to reduce the electric field at the edge of the trench-gate semiconductor device.

The edge termination 602 may comprise a plurality of edge termination regions as shown in Figure 6.

Each elementary cell 100 of the trench-gate semiconductor device 600 may comprise: a first active area 110a; a second active area 120a; an inactive area 115 separating the first active area 110a from the second active area 120a as described above with respect to Figure 1. The first active area 110a and the second active area 120a are configured for conducting an electrical current from a current input region to a current output region.

Each elementary cell 100 of the trench-gate semiconductor device 600 may comprise: a control region arranged in a trench 111 , 121 in a top surface of the elementary cell 100 opposing the bottom surface 101 , e.g., as described above with respect to Figure 1. The trench 111 , 121 comprises a trench-gate bottom 9a and trench-gate side walls 9b adjacent to the trench-gate bottom 9a.

Each elementary cell 100 of the trench-gate semiconductor device 600 may comprise a shield region 4a, 4b of a second semiconductor doping type being arranged in the drift region 3, the shield region 4a, 4b comprising a first part 4b placed in the first active area 110a and the second active area 120a below the trench-gate bottom 9a and a second part 4a placed in the inactive area 115, e.g., as described above with respect to Figure 1.

The second part 4a is configured to form an electrical connection with the current input region via the inactive area 115.

The shield region 4a, 4b of the elementary cell may form a shielding structure for shielding the control region of the elementary cell from an electric field.

The edge termination 602 may form part of the second part 4a of the shield region 4a, 4b as shown in Figure 6.

An advantage of this edge termination 602 is that the edge termination can be manufactured in the same production step as the forming of the second part 4a of the shield region. This facilitates production of the device. As can be seen from Figure 6, a transition region 601 may be arranged between the elementary cell 100 and the edge termination 602.

In the following, different embodiments of the elementary cell 100 shown in Figure 1 and Figures 2a, 2b, 2c are presented.

The second embodiment of the elementary cell and the corresponding trench-gate semiconductor device is a device for which all the defined semiconductor regions have the opposite doping type as presented in the first embodiment.

The device according to the second embodiment is complementary to the device according to the first embodiment. A complementary pair of devices is essential for some application and is a base for the Complementary-Metal-Oxide-Semiconductor (CMOS) technology.

The third embodiment of the elementary cell and the corresponding trench-gate semiconductor device is a device for which the doping of the drift layer 3 is opposite to the doping of the substrate 1 , which converts trench-gate MOSFET to trench-gate IGBT. For IGBT, the source electrode is called the emitter, the drain electrode is called the collector and the gate electrode is called the gate.

The technical advantage of this third embodiment is as follows. From its principle of operation, IGBT offers lower static (conduction) power losses than MOSFET. IGBT enables higher current densities than MOSFET or alternatively higher blocking voltages at the same current densities as MOSFET.

The fourth embodiment of the elementary cell and the corresponding trench-gate semiconductor device is a device which instead of silicon carbide uses another semiconductor material for the substrate 1 and/or for the buffer layer 2 and/or for the drift Iayer 3. The materials can be for example silicon, gallium nitride, gallium oxide or diamond.

The advantage of this fourth embodiment is that a material or materials with optimum electrical or thermal parameters can be used for certain device applications.

The fifth embodiment of the elementary cell and the corresponding trench-gate semiconductor device is a device for which the shield region (both below the trench-gate and the pillars) uses one or more semiconductor or non-semiconductor materials different than the drift layer, e.g., a semiconductor device for which the shield region is produced using polysilicon.

The advantage of this fifth embodiment is that a device may become cheaper in fabrication or may gain better electrical properties, if alternative materials are used for the shield region.

The sixth embodiment of the elementary cell 700 and the corresponding trench-gate semiconductor device is a device in which the trench-gate bottom does not indent into the shield region 4b. In other words, there is a distance between the trench-gate bottom 9a and the shield region 4b.

For this sixth embodiment, an elementary cell cross-section, a cross-section in a direction which is orthogonal to a direction of the elementary cell (no change comparing to the first embodiment) and a top view (no change comparing to the first embodiment) are shown in Figures 7a, 7b and 7c, respectively. All the figures show just the semiconductor material with the doped regions and the trench region.

The advantage of the embodiment is a structure, where the shield has no direct contact with the trench, but it is still connected to the current input region using the orthogonal pillars, which could be easily distinguished and recognized in the competitors’ products. The electrical performance of this structure is, however, still a subject of research and development.

The seventh embodiment of the elementary cell 800 and the corresponding trench-gate semiconductor device is a device in which the plug region 5 extends laterally in a whole region below the body region 6. For this seventh embodiment, an elementary cell crosssection, a cross-section in a direction which is orthogonal to a direction of the elementary cell and a top view (no change comparing to the first embodiment) are shown in Figures 8a, 8b and 8c, respectively. All the figures show just the semiconductor material with the doped regions and the trench region.

The advantage of this seventh embodiment might be a lower device resistance since the plug region 5 counter-dopes the body region 6 in its whole length. The counter-doping can reduce the ion implantation tail of the body region 6 and hence it can reduce the JFET resistance between the shield region 4b and the body region 6. The eight embodiment of the elementary cell 900 and the corresponding trench-gate semiconductor device is a device in which the body contact is placed in the whole width of the orthogonal stripe pillar, where the region 468 is created. For this eighth embodiment, an elementary cell cross-section, a cross-section in a direction which is orthogonal to a direction of the elementary cell (no change comparing to the first embodiment) and a topview are shown in Figures 9a, 9b and 9c, respectively. All the figures show just the semiconductor material with the doped regions and the trench region.

The advantage of this eighth embodiment is a structure which is easier to fabricate, particularly wider orthogonal body contact region 468 may ease device processing or improve its reliability. In addition, the embodiment enables to design the orthogonal stripe pillar of a smaller width than for the embodiment 1 and to use the device active area more optimally.

The ninth embodiment of the elementary cell 1000 and the corresponding trench-gate semiconductor device is a device in which the source contact region 7 counter-dopes the shield region 4a (new region 467 is created) and in which there is no orthogonal region 468.

For this ninth embodiment, an elementary cell cross-section (no change comparing to the first embodiment), a cross-section in a direction which is orthogonal to a direction of the elementary cell (no change comparing to the first embodiment) and a top-view are shown in Figures 10a, 10b and 10c, respectively. All the figures show just the semiconductor material with the doped regions and the trench region.

The advantage of this ninth embodiment is a device structure which is easier to fabricate, particularly the replacement of the rectangular structures with the stripe structures for the source region 7 and the elimination of the narrow orthogonal body contact region 468 may ease or improve the photolithography process.

The tenth embodiment of the elementary cell 1100 and the corresponding trench-gate semiconductor device is a device in which the source contact region 7 counter-dopes the shield region 4a (new region 467 is created) and in which the body contact is placed in the whole width of the orthogonal stripe pillar, where the region 468 is created.

For this tenth embodiment, an elementary cell cross-section, a cross-section in a direction which is orthogonal to a direction of the elementary cell (no change comparing to the first embodiment) and a top view are shown in Figures 11a, 11 b and 11c, respectively. All the figures show just the semiconductor material with the doped regions and the trench region.

The advantage of this tenth embodiment is a device structure which is easier to fabricate, particularly the replacement of the rectangular structures with the stripe structures for the source region 7 and the wider orthogonal region 468 ease or improve the photolithography process.

The eleventh embodiment of the elementary cell 1200 and the corresponding trench-gate semiconductor device is a device in which the body contact region 8 is implemented as a plurality of rectangular contacts and the source region 7 surrounds the body contact region 8. The orthogonal region 468 is not present in this embodiment. If the contacts overlap the shield region 4a, they create the regions 467 and 468 for the source contact 7 and the body contact 8, respectively.

For this eleventh embodiment, an elementary cell cross-section, a cross-section in a direction which is orthogonal to a direction of the elementary cell and a top-view are shown in Figures 12a, 12b and 12c, respectively. All the figures show just the semiconductor material with the doped regions and the trench region.

The advantage of this eleventh embodiment is a smaller cell pitch of the elementary cell. As a result, the cell integration can increase and the device resistance decreases.

The twelfth embodiment of the elementary cell 1300 and the corresponding trench-gate semiconductor device is a device in which the trench-gate etching process removes the semiconductor material everywhere along the stripe cell, which means that the shield region 4a, which is implemented in other embodiments as orthogonal stripes, is broken into a plurality of regions.

In this structure, a) the source region 7 and the body contact region 8 are implemented as stripes in the same way as for embodiment 10 or b) the body contact region 8 is implement as a plurality of contacts in the same way as for embodiment 11 . If the contacts overlap the shield region 4a, they create the regions 467 and 468 for the source contact 7 and the body contact 8, respectively. Forthis embodiment case b), an elementary cell cross-section, a cross-section in a direction which is orthogonal to a direction of the elementary cell and a top view are shown in Figures 13a, 13b and 13c, respectively. All the figures show just the semiconductor material with the doped regions and the trench region. In addition, for the same case a 3D structure is shown in Figure 14.

In the presented twelfth embodiment, the shield below the trench-gate and the shield pillars are produced using a single production step, which is preferably the epitaxy step.

In addition, in this embodiment, the plug region is present on both sides of the gate trench and not placed just at one trench-gate sidewall.

The advantage of this twelfth embodiment is a smaller cell pitch of the elementary cell due to the source region 71467 and the body contact region 81468 arrangement.

In addition, removal of the semiconductor material everywhere along the stripe cell during the trench-gate etching process (the shield region 4a broken into plurality of contact) increases the channel density. As a result, the device resistance decreases. Moreover, patterning of long stripes instead of short stripes during the photolithography and trench etching eases the fabrication process and makes it more reliable.

A thirteenth embodiment of the elementary cell and the corresponding trench-gate semiconductor device is a device for whom the shield region 4a and the shield region 4b are processed using deep ion implantation into the drift layer 3 instead of the first trench etching 401 , epitaxy 402 and planarization 403, which are the first three steps in the manufacturing method 400a presented in Fig. 4a.

Such a device can be produced by the method 400b described above with respect to Figure 4b.

The advantage of this thirteenth embodiment is that the manufacturing method 400b is less complex and cheaper.

The fourteenth embodiment of the elementary cell 1500 and the corresponding trench-gate semiconductor device is a device for which the shield region 4b and the trench are misaligned, particularly where one of the trench sidewalls 9b has no overlay with the shield region 4b.

The fourteenth embodiment of the device is a device for which the shield region 4b and the trench are misaligned, particularly where one of the trench sidewalls 9b has no overlay with the shield region 4b. For this fourteenth embodiment, an elementary cell 1500 crosssection, a cross-section in a direction which is orthogonal to a direction of the elementary cell 1500 (no change comparing to the first embodiment) and a top view (no change comparing to the first embodiment) are shown in Figures 15a, 15b and 15c, respectively. All the figures show just the semiconductor material with the doped regions and the trench region.

The advantage of this fourteenth embodiment is that it enables preferential current conduction on one trench sidewall, which may be beneficial for the materials with anisotropic electrical properties, for example for those where the carrier mobility is different on different crystallographic planes.

The techniques described in this disclosure are applicable to metal-oxide-semiconductor (MOS) devices which contain trenches in their gate structure and for which there is a need to protect the gate from high electric fields. An example of such devices are power semiconductor devices, whose majority is implemented as vertical structures, where the blocking voltage drops mostly on a lightly doped drift layer and the electrical current flows through the drift layer between the bottom electrode and the top electrode. The examples of the vertical power semiconductor devices are MOSFET, IGBT and Superjunction MOSFET, all with the trench-gate. The techniques described in this disclosure are applicable to various semiconductor materials, most of all to those used for fabrication of the power devices, which are silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3) and diamond, for example. The techniques described in this disclosure are also applicable to devices, for which the shield region (both below the trench-gate and pillars) uses one or more semiconductor or non-semiconductor materials different than the drift layer, e.g., a semiconductor device for which the shield region is produced using polysilicon. The power devices using the disclosed structure can be integrated in power modules and various power electronics applications which require low power loss and high reliability. While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.