EMBEDDED ARCHITECTURE WITH SERIAL INTERFACE FOR TESTING FLASH MEMORIES

CLAIM OF PRIORITY

Benefit of Priority is hereby claimed to U.S. Patent Application No. 11/676,049, filed February 16, 2007 and entitled "EMBEDDED ARCHITECTURE WITH SERIAL INTERFACE FOR TESTING FLASH MEMORIES", which is incorporated herein by reference in it entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention pertains to testing circuitry for flash memories, and to improvements in the time needed to screen flash memory arrays. More particularly, the present invention pertains to flash memory integrated circuits with on-board testing circuitry.

2. The Prior Art It is well known that screening a flash array accounts for the majority of the time spent during flash memory testing. Flash array screening usually consists of a sequence of erasing the array, programming the array with a pattern, and reading and verifying the pattern written into the array. If the programmed pattern can be verified, then the array is assumed to be defect free, otherwise, if errors occur, some defects have been detected. Repeating the sequence with different patterns allows for the highlighting of different types of faults.

Thus, a key point in testing the array is determining whether or not the defects can be repaired by substituting a redundant row or column of the array, and calculating the redundancy information, which, once permanently stored in the device, will be used during the entire life cycle of the chip to substitute the faulty part of the array.

As technology features scale down and flash memory densities grow larger, the total number of interactions increase between the external tester and

the flash memory during the array screening, becoming a real bottleneck. This is mainly due to the low frequency used to interface the flash memory with the external tester. Such low frequencies are needed to avoid bouncing and noise, because of the long cables connecting the probe card with the testing apparatus. To deal with this issue, one of the testing strategies has been to embed on the chip all the logic and circuitry necessary for testing the array, thus reducing the number of interactions between the tester and the array. This strategy is also known as B.I.S.T. (Built-in Self Test).

Another common strategy to reduce test time has usually been to increase the number of dice tested in parallel. In this way, cost is shifted to expensive probe cards with larger buses for address and data, and complexity is transferred to longer software codes.

BRIEF DESCRIPTION OF THE INVENTION An architecture for embedded testing of flash memory is presented. The present invention improves total testing time, thus reducing the overall die cost. It combines a serial interface, to increase the number of dice tested in parallel, with on-chip logic able to screen the memory array and reduce the number of interactions with an external tester. In one aspect of the present invention, a flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface. The testing logic is configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the nonvolatile redundancy registers.

In another aspect of the invention, a method for testing a flash memory array on a flash memory device is disclosed. The flash memory device includes a set of non- volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface. The method comprises the steps of the testing logic: accepting a set of serial commands from an external tester; erasing the array; programming the array with a test pattern; reading the array and

comparing the results with expected results to identify errors; determining whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generating redundancy information; and programming the redundancy information into the non-volatile redundancy registers. The present invention aims at reducing the testing time of flash memories by combining a serial interface to increase the number of dice tested in parallel, without over increasing the total number of wires on the probe card (which will be referred to herein as S ² I_LOGIC), and embedded logic to speed up the execution of test routines on the array, minimizing the total number of data exchanges between the external tester and the flash device (which will be referred to herein as BIST LOGIC).

To fulfill this task, the architecture of the present invention is able to accept a set of serial commands from an external tester and start its operations; to erase the array; to program the array using a standard pattern; to read the array and compare the results with an expected pattern; to calculate whether or not the errors can be repaired by substituting a redundant row or column and to calculate the related redundancy information; to store the redundancy information inside its volatile registers; to program into non volatile registers the redundancy information stored in its volatile registers; and to read the information stored in the non volatile registers into its volatile registers.

BRIEF DESCRIPTION OF THE DRAWING FIGURES FIG. 1 is a block diagram showing flash memory devices configured according to the principles of the present invention coupled to a tester. FIG. 2 is a block diagram of an integrated circuit in accordance with the present invention.

FIG. 3 is a block diagram showing the BIST architecture according to the present invention.

FIG. 4 is a diagram showing a S ² I_LOGIC block in accordance with the present invention.

FIG. 5 is a block diagram showing in more detail a S ² I-LOGIC block in accordance with the present invention.

FIG. 6 is a state diagram in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

The architecture of the present invention can be extended to chips with N redundancy resources made of K bits, where N is the number of redundancy resources available on the device and K is the number of bits needed to completely describe a single resource. Referring now to FIG. 1, a block diagram shows two flash memory devices 10 and 12 configured according to the principles of the present invention and including a S ² I_logic block 14 and a BIST logic block 16. Flash memory devices 10 and 12 are coupled to a tester 18 via a 5-wire bus 20. The 5-wire bus 20 includes Vpp, a potential that may be used to program the flash memory devices 10 and 12, V _DD to supply the standard power for the flash memory devices 10 and 12, GND, to supply the standard ground reference to the flash memory devices 10 and 12, I/O, a bi-directional serial data line used to exchange data between the tester and the flash memory devices 10 and 12, and CLK, a clock signal used to synchronize the data exchange between the tester and the flash memory devices 10 and 12.

Referring now to FIG. 2, a block diagram shows an illustrative integrated circuit 30 having features in accordance with the present invention. As shown in FIG. 2, the integrated circuit 30 includes several circuits. MICRO 32 is a processor that executes instructions. ROM 34 is a read only memory that stores instructions executable by the MICRO 32. S ² IJLOGIC 36 is a circuit that decodes the serial commands coming from the external tester and sends back information about the status of the current internal operation (on going or finished). PADS 38 are the five device I/O pads defined by the S ² I specification. ADDRESS COUNTER 26 is connected to S ² I_LOGIC 36, and DECODER 28 is connected to ADDRESS COUNTER 26 and ARRAY 42.

BIST_LOGIC 40 is a logic circuit that reads the data coming from the ARRAY 42 through the READ/VERIFY SENSE AMPS 44, defines redundancy information to be stored into its volatile registers, loads the PROGRAM LOGIC 46 to program the ARRAY 42 with a standard test pattern, loads the PROGRAM

LOGIC 46 to program the FUSE ARRAY 48, and loads the redundancy information from the FUSE ARRAY 48 into its volatile registers.

Referring now to FIG. 3, a block diagram shows architecture for a BIST logic circuit 50 according to the principles of the present invention. The following discussion assumes a flash memory chip with N redundancy resources of K bits each. Persons of ordinary skill in the art will readily be able to configure such an architecture with other configurations of redundancy resources.

The BIST LOGIC circuit 50 includes several circuit blocks. PATTERN GENERATOR 52 is a circuit driven by commands from the S ² I that generates a reference data pattern given the current row and column addresses (for instance ALLO, ALLl, checkerboard, diagonal, etc.). SCRAMBLER 54 is a circuit that scrambles the data read from the flash array in a standard format (i.e., if the device reads four words of 16 bits each in parallel, the scrambler may, for example, order the words from left to right and from most significant bit (MSB) to least significant bit (LSB) in a sequence of fourth word, third word, second word, first word.)

XOR 56 is a circuit that compares the scrambled data from the array with the reference pattern from the PATTERN GENERATOR 52 and outputs a current error vector. DECODER 58 is a circuit that, given the current redundancy configuration, decodes the already-detected errors (previous error vector). SUB 60 is a subtractor circuit that determines the new error vector, subtracting the previous error vector, which is from the DECODER, from the current error vector, which is from the XOR. ADDER 62 is an adder circuit that counts the number of new errors in the new error vector. CHECK

REDUNDANCY RULES 64 is a circuit that determines if the new errors are repairable or not (many different rules may be implemented as defined by a user). If one or more new errors are not repairable, CHECK REDUNDANCY RULES 64 issues a FATAL_ERROR INT signal. As an example, a simple rule that may be implemented where two redundancy resources are available is to assert the signal FATAL ERROR INT if there are more than two new errors in the current page.

CHOOSE REDUNDANCY RESOURCE 66 is a circuit that determines which redundancy resources are to be used. In the architecture shown in FIG. 3,

assume an example with two redundancy resources. If resourcefl] is to be used, then the signal EN_REG[1] is driven high from CHOOSE REDUNDANCY RESOURCE 66. If resource[2] is to be used, then signal EN_REG[2] is driven high from CHOOSE REDUNDANCY RESOURCE 66. If both resources are to be used, both signals EN_REG[1] and EN_REG[2] are driven high from

CHOOSE REDUNDANCY RESOURCE 66. If no resources are needed then both signals EN_REG[1] and EN_REG[2] are driven low from CHOOSE REDUNDANCY RESOURCE 66. Different filling sequences may be implemented depending on the chip redundancy architecture. REDUNDANCY ENCODER 68 is a circuit that encodes the positions of the new errors, using information used by the SCRAMBLER 54. It can then encode data identifying the word and the particular output within that word in which the errors occurred.

BIST_REG[N:1] 70 are a set of N volatile registers, each having K bits, that can be either loaded with the current status of the redundancy stored in the fuse array or updated with the new redundancy calculated by the embedded redundancy logic depending on the state of the multiplexers 72.

FF[N: 1] 74 are N flip-flops used to synchronize N signals EN_REG[N:1] on the rising edge of SAVE_BIST signal. FF[O] 76 is a flip-flop used to synchronize the signal FATAL ERROR INT on the rising edge of the

SAVE_BIST signal. UPDATE_BIST[N:1] on lines 78 are N signals used to selectively trigger registers BIST_REG[N:1] 70.

The BIST LOGIC has several inputs. DATA_BUS 80 is driven with a page of data read out of the flash array from the READ/VERIFY SENSE AMPS 44 of FIG. 2. CONF 82 is any number of signals coming from the S ² I_LOGIC 36 of FIG. 2 used to select the current desired reference pattern. SAVE_BIST 84 is a pulse issued by the MICRO 32 of FIG. 2 during the execution of a scan routine each time a new page has been read from the array. READ_RED_BIST 86 is a signal issued by the MICRO 32 of FIG. 2 to switch the multiplexers 72 so that the current status of redundancy may be loaded into the BIST-REG 70. FUSE_RESOURCE[N:1] 88 is NxK bits of redundancy information coming from the N non volatile registers of the flash memory.

The BIST_LOGIC has several outputs. BIST_REG[N:1] 70 are N volatile registers made of K bits, each one associated with one of the N

redundancy resources of the chip. FATAL ERROR 92 is a signal showing if the new errors in the last page read from the array can be repaired by substituting a redundant row or column.

An example of a simple scan routine useful to verify a pattern and to calculate and store the needed redundancy includes the following procedures:

1. load current redundancy status from fuses;

2. read a page;

3. trigger a SAVE_BIST pulse;

4. check FATAL_ ERROR signal; 5. if FATAL_ERROR=1 then exit and throw away the die;

6. if FATAL_ERROR=0 then increase the current page address;

7. jump to step 2 until the scan is completed.

Referring now to FIG. 4, a diagram shows an S ² I-LOGIC block that controls the S ² I interface in accordance with the present invention. S ² I-LOGIC is a logic circuit controlling the interface and has several input and output lines. The FUSE input 100 controls a fuse that if programmed permanently disables the S ² I interface. The CLOCK Input 102 carries a clock signal used to synchronize data exchange between the flash memory device and the tester. The BUSY input 104 carries a signal from the MICRO 32 showing if the current routine is being performed or is completed. The FATAL_ERROR input 106 is a signal from the BIST LOGIC 40 showing whether or not the current portion of the array can be repaired by substituting a redundant row or column. The RESET input 108 is a signal to reset the S ² I-LOGIC.

The BUFFER DIS AB output 110 is a signal to shut off the buffer leakage once the pads are left floating. The I/O 112 is a bi-directional line. It accepts input commands from the tester and it outputs either FATAL ERROR, used to notify the tester if an unrepairable error has occurred, or BUSY, used to notify the external tester when the internal operation has finished. An internal state machine will change the information on the I/O line 112, depending on the current status of the ongoing operation. The I/O_DIRECTION line 114 outputs a signal to show if I/O 112 is in input or output mode. Both the tester and the flash memory device to which it is coupled must share the same protocol to understand when the I/O line is in input or output mode. The

MICRO_CONTROL output 116 is a set of signals used to trigger the MICRO 32 and make it execute the correct test routine.

The present invention advantageously utilizes a set of commands that are used to trigger all the operations that will be executed by the embedded testing logic. An exemplary command set is shown in the following table. Persons of ordinary skill in the art will appreciate that the present invention is not limited to the command set shown herein and that other useful commands may be specified for operating the apparatus disclosed herein. Persons of ordinary skill in the art will appreciate that software or firmware for providing this command set will vary depending on the exact circuitry used to implement the circuit blocks disclosed in the drawing figures herein. The provision of such software or hardware is a routine exercise for a person of ordinary skill in the art.

Command Table

Referring now to FIG. 5, a block diagram shows the S ² I_LOGIC block 36 in more detail. The clock input 102 and I/O input 112 are used to operate shift register 120. In one embodiment of the present invention, shift register 120 is formed using 25 flip-flops. Shift register 120 is used to acquire from the serial I/O input 112 the instruction code (20 bits), the address (25 bits), and the data (16 bits) to be programmed.

Counter 122 is a 6-bit counter in one embodiment of the present invention, and is also driven from clock input 102. The output of counter 122 is presented to counter mask 124. Three outputs Cnt_25 (reference numeral 126), Cnt_20 (reference numeral 128), and Cnt_16 (reference numeral 130) developed in counter mask 124, indicate the complete acquisition of the instruction code, address, and data, respectively. Input decoder 132 decodes the 20-bit instruction code provided from shift register 120 and defines which of the operations defined by the commands shown in the command table above is to be performed. A state machine formed from combinatorial logic 144 and status flip-flop 134 determines the future states based on the current state and the status of the inputs of the combinatorial logic 144, which include the decoded command from input decoder 132 on lines 136, the BUSY input 104 of the S ² I_LOG1C block, the Cnt_25, Cnt_20, and Cnt_16 outputs of counter mask 124, and the FUSE input 100 of the S ² I-LOGIC block. The output of flip-flop 134 includes one bit that drives the enable inputs of shift register 120 and counter 122 on line 138. Other output bits from status flip-flop 134 on lines 140 drive combinatorial logic 142. Based on the current state and the shift register data, combinatorial logic 142 controls the direction of the data on I/O line 112 of the S ² I_LOGIC block by asserting a signal on line 114 of the S ² I-LOGIC block, and provides the embedded microcontroller 32 (FIG. 2) with the several inputs discussed with reference to FIG. 4.

Referring now to FIG. 6, a state diagram 150 is shown corresponding to the state machine formed from combinatorial logic 144 and status flip-flop 134. At state 152, the LOAD_COMMAND is issued. If there is a TLATCH SETTING COMMAND, a TLATCH command is issued at state 154, before returning back to state 152.

If a BIST_CMD is issued at state 152, then a SET BIST REG command is issued at step 156, before proceeding with the BIST at step 158. At state 158, as long as the BUSY signal equals 1 (i.e., the current routine is still being performed), the state machine loops back to state 158. If the BUSY signal equals 0 (i.e., the current routine is completed) and there has been a program or erase command, the state machine returns to state 152. If the BUSY signal equals 0 and there has been a verify command, the state machine proceeds to state 160, where the FATAL_ERROR signal is output before returning to state 152. If a LATCH_ADD_CMD is issued at state 152, then the ENABLE LATCH ADD command is issued at state 162. The state machine then proceeds to state 164, where the INPUT_ADD command is issued until the Cnt_25 value equals 1. If the Cnt_25 value equals 1, the state machine proceeds to state 166, where a LATCH_ADD pulse is implemented before returning to state 152. If a RESET_FLASH_CMD is issued at step 152, then a RESET pulse is implemented at state 168 before returning to state 152.

While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.