Priority Claim

[0001] The instant patent application is related to and claims priority from the co-pending provisional India patent application entitled, “Current Sensing High-Side Emulation Tracking”, Serial No.: 202241042518, Filed: 25-July-2022, Attorney docket no.: AURA-333-INPR, which is incorporated in its entirety herewith to the extent not inconsistent with the description herein.

[0002] The instant patent application is related to and claims priority from the co-pending NonProvisional US patent application entitled, “EMULATING CURRENT FLOWING THROUGH AN INDUCTOR DRIVEN BY A COMBINATION OF HIGH-SIDE SWITCH AND A LOW- SIDE SWITCH IN A SWITCHING CONVERTER”, Serial No.: 18/055,839, Filed: 16- November-2022, Attorney docket no.: AURA-036-US, which is incorporated in its entirety herewith to the extent not inconsistent with the description herein.

Background

[0003] Technical Field

[0004] Embodiments of the present disclosure relate generally to power supply circuits, and more specifically emulating current flowing through an inductor driven by a combination of high-side switch and a low-side switch in a switching converter.

[0005] Related Art

[0006] Switching converter refers to a component which generates a regulated DC (direct current) voltage from an input supply voltage by employing one or more switches, as is well known in the relevant arts. Typically, a switching converter transforms the input supply voltage into a pulsed voltage by operating switch(es), the pulsed voltage then being smoothed using capacitors, inductors, and other elements to generate the regulated DC voltage.

[0007] Power is supplied from the input to the output by turning ON switches (e.g., MOSFETs) until the desired voltage is reached. Switching converters are used in components such as regulated power supplies, which in turn are used in devices such as computers and mobile phones, as is also well known in the relevant arts.

[0008] A switching converter often contains a pair of switches driving an inductor. Each switch is typically implemented as a transistor (e.g., MOSFET) and the switches are connected in series between input supply voltage and a reference terminal (e.g., ground). The switch coupled closer to the input voltage (source of input power to the converter) is termed as the high-side switch, while the other one is termed as a low-side switch. The switches are operated by a control circuit which switches on the transistors in successive non-overlapping time durations to cause the switch that is currently ON to drive the inductor in the corresponding duration.

[0009] There is often a need to emulate the current flowing through such an inductor. Emulation implies construction of the inductor current, and the output of emulation can be either an emulated signal which is akin to the inductor current, or a representation of the inductor current in some other suitable form such as voltage or digital values. The emulated information can then be used for various purposes as suited in the corresponding environments.

[0010] Several aspects of the present disclosure are directed to emulating current flowing through an inductor driven by a combination of high-side switch and a low-side switch in a switching converter.

Brief Description of the views of Drawings

[0011] Example embodiments of the present disclosure will be described with reference to the accompanying drawings briefly described below.

[0012] Figure 1 is a block diagram of an example system in which several aspects of the present disclosure can be implemented.

[0013] Figure 2A is a block diagram illustrating the details of a voltage regulator module (VRM) in an embodiment of the present disclosure.

[0014] Figure 2B is a diagram illustrating example waveforms of a pulse-width modulated (PWM) signal to a smart power stage (SPS) and the inductor-current.

[0015] Figure 3 is a diagram illustrating the implementation of an SPS in an embodiment of the present disclosure.

[0016] Figure 4 is a diagram illustrating the details of a current emulator block in an embodiment of the present disclosure.

[0017] Figure 5 is a diagram illustrating example waveforms of emulated inductor current in an embodiment of the present disclosure.

[0018] In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Detailed Description

[0019] 1. Overview

[0020] According to an aspect of the present disclosure, inductor current in a switching converter is emulated. A high-side switch and a low-side switch in the switching converter respectively drive the inductor in a first phase and a second phase periodically. A current emulator block in the switching converter measures (or senses) a first portion of the inductor current corresponding to a longer phase of the first phase and the second phase, the other one of the first phase and the second phase being a shorter phase. The current emulator block estimates a peak of the inductor current at a transition from the shorter phase to the longer phase. The estimating includes (a) comparing an estimated magnitude with a first magnitude of the inductor current at the transition in a first period, (b) changing the estimated magnitude, and performing (a) and (b) until the estimated magnitude equals the first magnitude to identify the peak. The current emulator block generates a second portion of the inductor current during the shorter phase of the inductor current based on the estimated magnitude, and provides the first portion and the second portion as an emulated current of the inductor current.

[0021] Several aspects of the present disclosure are described below with reference to examples for illustration. However, one skilled in the relevant art will recognize that the disclosure can be practiced without one or more of the specific details or with other methods, components, materials and so forth. In other instances, well-known structures, materials, or operations are not shown in detail to avoid obscuring the features of the disclosure. Furthermore, the features/aspects described can be practiced in various combinations, though only some of the combinations are described herein for conciseness.

[0022] 2. Example System

[0023] Figure 1 is a block diagram of an example system in which several aspects of the present disclosure can be implemented. System 100 is shown containing power supply 110, central processing unit (CPU) 120, storage 130, network interface 140 and peripherals 150. In an embodiment, system 100 corresponds to a computer (desktop, laptop, etc.), although system 100 can represent other types of systems in other embodiments. It is understood that system 100 can contain more or fewer blocks than those shown in Figure 1 A

[0024] CPU 120, in general, represents a processor or a system-on-chip (SoC), and is shown as receiving a pair of supply voltages (Va and Vb) on respective paths 112A and 112B from power supply 110. As an example, Va may be a smaller voltage than Vb, and may be used to power a core portion of CPU which may include arithmetic logic unit (ALU), microprogram sequencer, registers, etc. Vb may be used to power the rest of CPU 120, such as for example, input/output (I/O) units, I/O buffers, on-chip peripherals etc. CPU 120 provides various signals (all deemed to be contained in path 121) specifying, among others, its power supply requirements to power supply 110. Examples of such signals can be those that specify the specific mode of operation (in terms of power consumption) such as PSI, PS2, PS3, etc., which refer to “Power Save States for Improved Efficiency”.

[0025] Storage 130 represents a memory that may include both volatile and non-volatile memories. For example, in a personal computer, storage can include magnetic memory (hard disk) as well as solid state memory (RAM, Flash, etc.). Storage 130 is shown receiving a supply voltage on path 113 for powering various circuits and blocks within.

[0026] Network interface 140 operates to provided two-way communication between system 100 and a computer network, or in general internet. Network controller 140 implements the electronic circuitry required to communicate using a specific physical layer and data link layer standard such as Ethernet or Wi-Fi™. Network interface 140 may also contain a network protocol stack to allow communication with other computers on a same local area network (LAN) and large-scale network communications through routable protocols, such as Internet Protocol (IP). Network interface 140 receives a power supply on path 114 for powering internal circuits and blocks. Network interface 140 receives from/transmit to external systems and CPU 120 respectively on path 141 and path 124.

[0027] Peripherals 150 represents one or more peripheral circuits, such as for example, speakers, microphones, user interface devices, etc. Peripherals 150 receives a power supply on path 115, and communicates with external devices on path 151.

[0028] Power supply 110 receives one or more sources of power (e.g., battery) on path 101, and operates to provide the desired power supply voltages on paths 112A, 112B, 113, 114 and 115. In an embodiment, power supply 110 is designed to contain one or more DC-DC converters within to generate the power supply voltages. Power supply 110 responds to signals from CPU 120 received on path 121 to control the multi-phase converters to reduce/increase current output based on the specific signal (e.g., PSI, PS2 and PS3).

[0029] In the embodiment, power supply 110 is a voltage regulator module (VRM), sometimes also called processor power module (PPM), and contains one or more step-down switching (buck) converters to generate several smaller voltages from a higher-voltage supply source. In other embodiments however, other types of DC-DC converters such as boost, buck-boost, hysteretic converters etc., can be implemented instead of a buck converter. With a VRM, multiple devices/ICs requiring different supply voltages can be mounted on the same platform, for example, a computer motherboard of a personal computer (PC). Accordingly, the description is continued with respect to a VRM as shown in Figure 2A.

[0030] 3. Voltage Regulator Module

[0031] Figure 2A is a block diagram illustrating the details of a VRM in an embodiment of the present disclosure. Power Supply 110 is implemented as a Voltage Regulator Module and is shown containing phase controller 210, smart power stage (SPS) SPSA-1 (220-1) through SPSA- 6 (220-6), SPSB-1 (230-1) through SPSB-3 (230-3), inductors 225A-1 through 225A-6, and 227B-1 through 227B-3 and capacitors 226A-1 through 226A-6, and 228B-1 through 228B-3. Power supply Va (240) is generated by a 6-phase buck converter (there are six SPSes - 220-1 through 220-6), while power supply Vb (250) is generated by a 3-phase buck converter (there are three SPSes - 230-1 through 230-3). Nodes/Paths 240 and 250 can correspond to paths 112A and 112B of Figure 1. In the interest of conciseness, other power supply circuits that generate supplies on paths 113, 114 and 115 are not shown in Figure 2.

[0032] Phase controller 210 performs regulating functions to enable the generation of regulated voltages Va and Vb. Accordingly, Va and Vb are shown as being provided as inputs to phase controller 210, to enable operation of one or more feedback loops within phase controller 210 to regulate Va and Vb. Phase controller 210 also receives inductor-current information (current flowing through each of the inductors) from each of the SPSes to enable various operations such as current-mode control of voltage regulation, current limiting, short circuit protection, and balancing the currents generated by each SPS of a same converter so as to make the currents from each SPS of a converter to be substantially equal in magnitude.

[0033] The combination of (corresponding circuitry within) phase controller 210, an SPS, an inductor and a capacitor forms one “phase” of each multi-phase buck converter. Thus, for example, SPSA-1, inductor 225A-1, capacitor 226A-1, and the corresponding portion within phase controller 210 form a single buck converter, and one phase of the 6-phase buck converter. It is noted here that, while each phase is shown as having its own separate capacitor (e.g., 226A- 1), in another embodiment, only a single larger capacitor (larger capacitance) may be employed at node 240 (as well as 250). In other embodiments, multiple capacitors are placed close to the load powered by the corresponding supply voltage.

[0034] Each SPS may be implemented to contain a high-side switch, a low-side switch, gatedrive circuitry for the two switches, a temperature monitor circuit and an inductor-current sense (or emulation) circuit to provide information indicating the magnitude of inductor current to phase controller 210. The current supplied by an SPS, and therefore the corresponding inductor current waveform generally depends on the load current drawn from the supply voltage, although the high-side switch and low-side switch of an SPS may be viewed as ‘driving’ the inductor. Each SPS receives a source of power as an input which is connected to the high-side switch (shown in detail in sections below). In Figure 2 A, the supply source is numbered 201, and has a voltage Vin. Typical value of Vin in a VRM is about 21 volts (V).

[0035] Each SPS communicates with phase controller 210 via corresponding signals PWM, SYNC, CS and TMP. Thus, SPSA-1 is shown connected to phase controller 210 through signal/paths PWMA-1 (211), SYNC-A (212), CSA-1 (213) and TMPA (214). SPSA-6 communicates with phase controller 210 via signals PWMA-6, SYNC-A, CSA-6 and TMP (214). Similarly, SPSB-1 is shown connected to phase controller 210 through signal/paths PWMB-1 (216), SYNC-B (217), CSB-1 (218) and TMPB (219). SPSB-3 communicates with phase controller 210 via signals PWMB-3, SYNC-B, CSB-3 and TMP (219). The other SPSes would have similar connections with phase controller 210.

[0036] Signal PWM is an input to an SPS and provides a pulse-width modulated (PWM) signal, which may, for example, be a binary signal of fixed frequency. The PWM signal controls the opening and closing of high-side switch and low-side switch of the phase. The duty cycle of the PWM signal is set by phase controller 210 and is designed to generate the desired power supply voltage and/or control/change the current supplied by that phase. For example, PWMA-1 would have a duty cycle as required for the magnitude of Va and the current to be provided by SPSA-1. As is well known in the relevant arts, the PWM signals to each SPS of a same converter are staggered, i.e., delayed with respect to each other in phase such that typically no two high-side switches or low-side switches in the converter (i.e., respective SPSes) will be overlapping. Such a technique is employed for reasons such as, for example, to ensure that the peak instantaneous current drawing from Vin is relatively low (or zero) at all times.

[0037] Signal TMP is an output from an SPS to phase controller 210, an provides information regarding the temperature in the SPS. Phase controller 210 may process the TMP signal (or the information contained in it) to adjust the current supplied by that phase, or for shut-down of the VRM. The TMP outputs of each phase of a converter are wired together, and a single input is connected to phase controller 210. The maximum of the TMP outputs of a phase is driven on the wired connection.

[0038] Signal SYNC is an input to an SPS and may be used by phase controller 210 for the purposes of waking-up the SPS upon power-up of the power supply 110, and also to indicate the power-mode (e.g., PS2, PS3), i.e., output current requirement, of the multi-phase converter. Typically, all SPSes of the same converter share a single SYNC signal.

[0039] Signal CS (current sense) is an input to phase controller 210 from an SPS, and contains information regarding the magnitude of the inductor current of that phase. The information can be in the form of a current, voltage, digital values, etc.

[0040] Figure 2B illustrates a PWM signal to an SPS and the inductor-current information CS in an example. For ease of understanding, the SPS is assumed to be SPSA-1. Signal 211 represents the PWM signal PWMA-1, and signal 213 represents CS signal CSA-1 generated by SPSA-1. PWMA-1 is shown as being at logic high level in time intervals t20-t21 , t22-t23 and t24-t25, and logic low level in intervals t21-t22 and t23-t24. A logic high level of PWMA-1 causes the high- side switch and the low-side switch in SPSA-1 to be respectively closed and open. A logic low level of PWMA-1 causes the high-side switch and the low-side switch in SPSA-1 to be respectively open and closed. Intervals in which PWMA-1 is a logic high may be viewed as a ‘first phase’, and intervals in which PWMA-1 is a logic low may be viewed as a ‘second phase’. The first and second phases repeat, as may be observed from Figure 2B, and are thus periodic. The high-side switch and the low-side switch may be viewed as respectively ‘driving’ the inductor in each of the first phases and second phases periodically. It is noted that the terms ‘first phase’ and ‘second phase’ are not to be confused with the phases of a multi-phase converter (as noted above).

[0041] CSA-1 213 represents the current flowing through inductor 225A-1. CSA-1 can be a replica current, voltage and digital values (assuming SPSA-1 has the circuitry to generate such digital values), as examples. In the example of Figure 2 A, CSA-1 is a current and may be a scaled replica of the current through inductor 225A-1. In the first phases (such as t20-t21), CSA- 1 rises linearly, and in the second phases (such as t21-t22) CSA-1 falls linearly, just as the inductor-current would.

[0042] The other SPSes may also have similar waveforms at the corresponding connections to phase controller 210.

[0043] As noted above, each SPS provides its CS signal to phase controller 210 to enable phase controller 210 to perform various operations such as current-mode control of voltage regulation, current limiting, short circuit protection, and balancing the currents generated by each SPS of a buck converter so as to make the currents from each SPS of a converter to be substantially equal in magnitude. Accordingly, the implementation details of an SPS in an embodiment of the present disclosure is described next.

[0044] 4. Smart Power Stage (SPS)

[0045] Figure 3 is a diagram illustrating the implementation of an SPS in an embodiment of the present disclosure. SPSA-1 (220-1) is shown in detail in Figure 3. The other SPSes can also be implemented to be similar to SPSA-1. However, in other embodiments, an SPS can have more or fewer blocks. SPSA-1 is shown containing gate driver 310, high-side (HS) switch 320, low-side (LS) switch 330, temperature sensor 340 and current emulator block 350. Also shown in Figure 3 are inductor 225 A-l and capacitor 226A-1. Node 240 provides the supply voltage Va.

[0046] Temperature sensor 340 measures the ambient temperature at SPS 220-1 periodically, and provides the temperature values on path 214.

[0047] Gate driver 310 receives binary signal PWMA-1, and in response to the logic level of PWMA-1 generates the appropriate voltage to turn ON and turn OFF HS switch 320 and LS switch 330 in corresponding intervals indicated by PWMA-1. HS switch 320 and LS switch 330 are each shown implemented as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with gate driver 310 driving the gate terminals of the MOSFETs, although other implementations for the switches are possible. In the example of Figure 3, when PWMA-1 is a logic high (corresponding to the first phase), gate driver 310 generates respective appropriate voltages on paths 312 (en-HS) and 313 (en-LS) to switch ON MOSFET 320 and switch OFF MOSFET 330. When PWMA-1 is a logic low (corresponding to the second phase), gate driver 310 generates respective appropriate voltages on paths 312 and 313 to switch OFF MOSFET 320 and switch ON MOSFET 330.

[0048] As shown in Figure 2B, when PWMA-1 is logic high, current flows from Vin to the load (connected to Va node, but not shown) via HS MOSFET 320 and inductor 225 A- 1 with rising slope. When PWMA-1 is logic low, the inductor current flows in the loop formed by ES MOSFET 330, inductor 225A-1 and load with falling slope.

[0049] Current emulator block 350 operates to construct the inductor current, and provides the constructed inductor current on path CSA-1. One problem with measuring (or sensing) the inductor current is when the duration for which a switch (HS or LS) is ON only for a very short duration. Generally, the duration for which the HS switch and LS switch are ON in the respective phases (the first and second phases noted above) depends on the difference between Vin and Va (or regulated output voltage in general). If Vin is much greater than Va (e.g., Vin equals 21V and Va is IV), then the first phase (also termed charging phase) is of a very short duration, while the second phase (also termed discharging phase) is of a comparatively long duration.

[0050] In general, it may be difficult to measure the inductor current reasonably accurately during a very short phase, such as the first phase noted herein. On the other hand, it may be easier to measure the inductor current fairly accurately during a long phase, such as the second phase noted herein.

[0051] Current emulator block 350 operates to generate replicas of the inductor current in the first phases as well as the second phases. In the second phases, current emulator block 350 measures (and creates a replica of) inductor current. In the example of Figure 3, current emulator block 350 receives the voltage across LS MOSFET 330 via paths 335 and 399 (ground) in the second phases. Current emulator block 350 in effect divides the measured voltage with the ON- resistance of LS MOSFET 330 to obtain the inductor current magnitude in the second phases. In other embodiments, other techniques for measuring inductor current in the second phases can be used, that are well-known in the relevant arts.

[0052] However, since the first phases are very short, current emulator block 350 does not measure the inductor current in the first phases, but operates to estimate and create a replica (scaled or otherwise) of the inductor current in the first phases.

[0053] The manner in which current emulator block 350 measures and creates a replica (scaled or otherwise) of inductor current in the second phases, and estimates and creates a replica (scaled or otherwise) of the inductor current in the first phases is described next along with the implementation details of current emulator block 350 in an embodiment. [0054] 5. Current Emulator Block and Emulating Inductor- Current

[0055] Figure 4 is a diagram illustrating the details of a current emulator block in an embodiment of the present disclosure. Current emulator block 350 (of Figure 3) is shown containing circuits 40 and 41. It is noted herein that the details of circuit 40 as relevant for the operation of circuit 41 (and current emulator block 350) have been provided and described. However, it is to be understood that in alternative implementations of current emulator block 350, circuit 40 may be implemented differently, and use more components and circuitry.

[0056] Circuit 40 measures (or senses, rather than estimating) the inductor current IL (inductor 225A-1 of Figure 2 is also shown for clarity) in the second phases (i.e., when LS switch 330 (Figure 3) is closed and driving the inductor current, HS switch 320 being open in the second phases). Circuit 40 re-creates (i.e., creates a replica of) the inductor current in the second phases. As may be observed from Figure 2B, the inductor current in the second phases has a falling (negative slope). Current emulator block 350 provides the replica inductor current in the second phases at/on node/path CSA-1 (213), as will be described below.

[0057] Circuit 41 operates to estimate and create a replica of inductor current in the first phases, since it may be difficult to accurately measure the inductor current in the first phases accurately due to the very short duration of each of the first phases. An example of such very short duration is when the duty cycle of the PWM signal is around 5%, and the period of the PWM signal is 1.6 microseconds (us). Current emulator block 350 provides the replica inductor current in the first phases also at/on node/path CSA-1 (213), as will be described below. Thus, current emulator block 350 provides the complete inductor current information in the form of replica currents (noted above) on path CSA-1.

[0058] The series connection of transistors 420 and 421 across supply node 401 (Vcc) and ground 399 is referred to herein as “output block 495”. Transistor 420 is shown as P-channel metal oxide semiconductor field effect transistors (PMOS), and transistor 421 is shown as N- channel metal oxide semiconductor field effect transistors (NMOS). Supply Vcc may be provided to SPSA-1 (as well as the other SPSes) by phase controller 210, or be generated in VRM 199in a known way.

[0059] Circuit 40 of current emulator block 350 is shown containing amplifier 450, switches 480 and 485, and capacitors 430 and 435. For clarity, LS switch 330 is also shown, although it would typically not be part of circuit 40. Label 399 represents a ground connection.

[0060] Amplifier 450 receives the voltage across LS switch 330 in the second phases, and provides an amplified output voltage as an output. Amplifier 450 is shown as a fully differential amplifier merely as an example. Other amplifier types and topologies can also be used instead. In an embodiment, amplifier 450 is a fully differential amplifier with gain determined by a feedback network (not shown, but for examples using two pairs of resistors as is well known in the art) that would be used to operate amplifier 450 in closed-loop mode. In the embodiment, fully differential amplifier receives the voltage across LS switch 330 across the (-) input terminal connected to path 335 and the (+) input terminal connected to ground 399. Fully differential amplifier 450 provides a corresponding amplified difference as output voltage across terminals 458 (+) and 459 (-).

[0061] LS switch 330 is switched ON (and is therefore conductive) by signal ‘en-LS’ (313 of Figure 3) in (and for the duration of) the second phase only. Thus, the current (IL) through inductor 225 A- 1 is sensed by circuit 40 by measuring/obtaining the voltage across the LS switch 330 in the second phase. For example, if the LS switch has a 2.5 milli Ohm resistance Ron and is sourcing an inductor current of 40A, then the voltage across LS switch 330 will be lOOmV. Sensing the voltage across the LS switch 330 is a lossless method of sensing the current. However, other techniques for obtaining a measure of the magnitude of inductor current in the second phases can also be used, as would be apparent to one skilled in the arts upon reading this disclosure.

[0062] The combined operations of circuit 40 and output block 495 in the second phase is now described with combined reference to Figure 4 and Figure 5.

[0063] (A) Second Phase:

[0064] In operation, LS switch 330 is switched ON by control input en-LS (313) at the start of the second phase (e.g., time instants t21, t23 and t25 in Figure 2B, and also t52 in Figure 5). It is noted that in the interest of simplicity, the blanking interval (T-LSBLNK) (t52-t53) of Figure 5 is not shown (or is assumed zero) in Figure 2B. LS switch 330 is switched OFF at the start of the immediately next first phase (e.g., t22, t24 of Figure 2B or t54 of Figure 5). Switches 480 and 485 are closed for the duration of T-LS2 (Figure 5) by signal en\-LSBLNK, and are open otherwise.

[0065] Control signals en\-LSBLNK and en-LSBLNK may be binary signals, and generated by a control circuit (not shown), but which may be contained in current emulator block 350. The generation of such control signals and the circuitry for such generation can be done in a known way. Control signal en\-LSBLNK is the logical inverse of en-LSBLNK. Control signal en- LSBLNK is operational (e.g., logic high) to switch-ON (i.e., close) the corresponding switch only for the interval T-LSBLNK.

[0066] It is noted here that T-LSBLNK is an interval in which amplifier 450 is ON (staring from, the start of T-LSBLNK), but whose outputs are not yet settled and correctly reflecting the input. This occurs due to the bandwidth (BW) of differential amplifier 450 being finite. Therefore, amplifier 450 may need some time from being switched ON (e.g., at the start of T-LS) till it reaches steady-state operation and generates outputs correctly. The duration of T-LSBLNK may be set by a designer/user based on the BW of differential amplifier 450. Output on CSA-1 is disabled for the duration of T-LSBLNK to prevent unsettled/transient output from being provided on it. Control signal en\-LSBLNK causes each of switches 480 and 485 to be closed at the end of the blanking phase, and to be opened at the end of the corresponding second phase, the switches remaining closed for the duration from the end of the blanking phase to the end of the corresponding second phase.

[0067] Therefore, in the second phase, voltage 458 and 459 respectively cause transistors 420 and 421 to source and sink respective currents based on the specific magnitudes of voltages 458 and 459 and therefore the input voltage to the amplifier. Thus, output block 495 effectively operates as a voltage to current converter. As a result, a difference current (denoted by Ics) between the current sourced by transistor 420 and the current sunk by transistor 421 is provided on path 213 (CSA-1). The difference current is a replica (scaled or actual) of the inductor current in the second phase (or more specifically for the portion T-LS2 of the second phase.

[0068] Additionally, capacitors 430 and 435 would charge/discharge depending on voltages on path 458 and 459 respectively, and at the end of the second phase (e.g., t54 in Figure 5) would each have a voltage across them representative of (or corresponding to) the difference current on path 213 at the end of the second phase. In other words, capacitors 430 and 435 enable to store (or hold) the ‘information’ (in this two voltages) representative of the inductor current at the end of the second phase (e.g., t54). Such ‘valley hold’ capability of circuit 40 is required since the immediately following first phase, and circuit 41 that estimates the inductor current in the first phase requires this initial condition.

[0069] Referring now to Figure 5, the measured and recreated (and optionally scaled down) inductor current in the second phase is shown in interval t53-t54, and is assumed to be the same at each time point of all cycles 1-6. Cycles 1 through 6 occur sequentially in time, with cycle 1 being the first. That is, cycle2 immediately follows cycle 1, cycle3 immediately follows cycle2, etc.

[0070] As noted above, the inductor current during the first phases have to be estimated/re- created (at least for small ON durations of HS switch 320). The manner in which such estimation/re-creation is done according to aspects of the present disclosure is described next.

[0071] (B) First Phase:

[0072] Circuit 41 of current emulator block 350 operates to create a replica of inductor current in the first phases without sensing or measuring the inductor current in the first phases, and is shown containing low-side current-to-voltage (LS-I2V) converter 470A and high-side current-to- voltage (LS-I2V) converter 470B, switches 482 and 484, capacitors 437 and 438, comparator 465, up/down (UP/DN) charge pump driver (CP driver) 460 and charge pump 490. Charge pump 490 is in turn shown containing current source 440 and current sink 445, capacitor 446, NMOS transistor 419 and switch 486. 401 represents a power supply terminal (Vcc), having a voltage of the order of 3 V to 5V as an example. In Figure 5, points 522 represent the peak value of inductor current in each corresponding cycle.

[0073] LS-I2V converter 470A receives, on input path 471 A, a scaled version of the emulated inductor current Ics (provided on path 213). The scaling factor is noted as ‘k’, and is typically (but not necessarily) less than 1. LS-I2V converter 470A converts the scaled current input to a corresponding voltage provided as an output.

[0074] HS-I2V converter 470B receives, on input path 471B, the scaled version of the emulated inductor current Ics (provided on path 213). The scaling factor is ‘k’ as for LS-I2V 470A. HS- I2V converter 470B converts the scaled current input to a corresponding voltage provided as an output.

[0075] Switch 484 is controlled by control signal en-HS. Control signal en-HS has a logic value that causes switch 484 to be closed for the duration of the first phase (e.g., t51 -52 of Figure 5) or t20-t21 of Figure 2B, and open otherwise. Switch 482 is controlled by control signal en- LSBLNK. Control signal en-LSBLNK has a logic value that causes switch 482 to be closed for the duration of the blanking interval T-LSBLNK (shown in Figure 5), and open otherwise.

[0076] The operation of switch 482 charges capacitor 438 to a voltage (V-ILS-PK (466)) representing the peak value of the inductor current (points 522 at t53 of Figure 5). The operation of switch 484 charges capacitor 437 to a voltage (V-IHS-PK 467) representing the value of inductor current at the end of each first phase (t52 in Figure 5). During each of the T-LSBLNK intervals in the cycles shown in Figure 5, the current magnitude into/out of node CSA-1 remains unchanged.

[0077] Comparator 465 is coupled to each of paths 466 (+ terminal) and 467 (- terminal), and generates an output on path 468 that is of one polarity (e.g., positive) if V-ILS-PK is greater than V-IHS-PK, and of the opposite polarity (e.g., negative) if V-ILS-PK is lesser than V-IHS-PK. Comparator 465 can be implemented to output 468 of other types also, such as for example logic one and logic zero.

[0078] UP/DN CP driver 460 represents a charge pump driver. UP/DN CP driver 460 activates current source 440 if the present output of comparator 465 on path 468 is positive, and activates current sink 445 if the present output of comparator 465 on path 468 is negative. The operation of UP/DN CP driver 460 is such that only one of 440 and 445 is ON in a given time interval. Switch 486 is controlled by signal en-HS, which causes switch 486 to be closed in the first phases (e.g., T-HS of Figure 5), and open otherwise. [0079] In operation, current emulator block 350 iteratively operates circuit 41 to arrive at the correct inductor current waveform during the first phases, as illustrated by cycles 1-6 (Figure 5), which may be regarded as the iterations. As may be observed, circuit 41 contains a loop that is iteratively operated until the correct inductor current waveform is obtained. Each first phase starts with the inductor current equal to the valley current at the end of the immediately previous second phase (of the immediately previous cycle) due to the operation of the ‘valley hold’ mechanism described above.

[0080] The goal of the loop formed by circuit 41 is to adjust the current through transistor 419 till the current through transistor 419 and capacitor 430 matches the slope of the inductor current. Current through NMOS 419 is set to 0 initially (first cycle - cyclel noted below). Comparator 465 and CP driver 460 generate the necessary UP/DN pulses to increase the gate voltage of transistor 419, until the steady-state current through transistor 419 and capacitor 430 matches the slope of the actual inductor current represented by line 510.

[0081] The operation of the loop is now illustrated with combined reference to Figures 4 and 5.

[0082] In the first cycle (cyclel) circuit 41 sets the estimated inductor current waveform (520) to zero by disabling current source 440 and current sink 445. As a result, the voltage across capacitor 446 is zero (or at least not sufficient to switch-ON transistor 419). Hence, NMOS 419 is OFF and does not affect output block 495 since transistor 420 is OFF. Estimated inductor current 520 has a slope of zero, the actual inductor current in the first phase being represented by 510.

[0083] In the next iteration, starting at the beginning of cycle2, comparator 465 compares the voltages at nodes 466 and 467, which would respectively correspond to points 522 and 521. Since the voltage on node 466 is greater, comparator 465 generates a signal on path 468 to cause driver 460 to switch ON current source 440 (UP operation) for a small duration (for example, ~5 nano seconds(ns)), thereby charging capacitor 446. Current sink 445 is OFF for this duration. Hence, NMOS 419 is ON and pulls the gate of transistor 420 towards ground to an extent determined by the voltage on capacitor 446. As a result, capacitor 430 charges through switch 486 and current through NMOS 419. Therefore, current through PMOS transistor 420 is increased (as compared with the current in cyclel) since voltage at gate terminal of PMOS 420 progressively reduces. The current through NMOS transistor 421 remains the same as before. Therefore, the difference current at CSA-1 (213) represented by emulated inductor current 530 has a larger slope than in cycle 1. Therefore, the difference between current values at points 522 and 531 is less than that between current values at points 522 and 521.

[0084] In the next iteration, starting at the beginning of cycle3, comparator 465 compares the voltages at nodes 466 and 467, which would respectively correspond to points 522 and 531. Since the voltage on node 466 is greater, comparator 465 generates a signal on path 468 to cause driver 460 to switch ON current source 440 (UP operation) for a small duration (for example, ~5 nano seconds(ns)), thereby further charging capacitor 446. Current sink 445 is OFF for this duration. Hence, NMOS 419 is ON and pulls the gate of transistor 420 towards ground to an extent determined by the voltage on capacitor 446 (which is now greater than that in cycle2). As a result, capacitor 430 charges through switch 486 and current through NMOS 419. Therefore, current through PMOS 420 is increased further (as compared with the current in cycle2) since voltage at gate terminal of PMOS 420 progressively reduces further. The current through transistor 421 remains the same as before. Therefore, the difference current at CSA-1 (213) represented by emulated inductor current 540 has a larger slope than in cycle2. Therefore, the difference between current values at points 522 and 541 is less than that between current values at points 522 and 531.

[0085] In a manner similar to that described above with respect to cycles 1, 2 and 3, circuit 41 operates to incrementally increase the inductor current in the first phase of each cycle. Thus, inductor currents 550, 560 and 570 are shown respectively having higher slopes. At the start of each of cycles 4, 5 and 6, circuit 41 would compare the voltages/currents represented by points 551, 561 and 571 respectively with that represented by points 522. In Figure 5, the iteration converges in cycled with voltage/current represented by point 571 equalling that represented by point 522. Therefore, 570 represents the correct inductor current (although it may be a scaled version depending on the magnitude of ‘k’) in the first phase. The scaling factor ‘k’ is fixed and is known to phase controller 210. Thereafter, the inductor current in the following phases (i.e., after cycled) will toggle alternately above and below point 571 (also 522) in each cycle based on the charge pump ripple.

[0086] It is noted here that if amplifier 450 has a sufficiently high BW, then duration T- LSBLNK could be smaller or zero. In such case, T-LS2 would equal T-LS and switch 482 would be closed for the duration of T-LS. When duration T-LSBLNK equals zero, then circuit 41 would have to be modified appropriately (in place of LS-I2V 470A, switch 482 and capacitor 438) so as to get an estimate of voltage at point 522. Comparator 465 would then operate as described above to compare such voltage with the correspond voltages at t52 (which would now be the same as t53) to drive the rest of the loop as noted above.

[0087] Phase controller 210 would operate to process the emulated inductor current waveform provided via node CSA-1 for purposes noted above. The other SPSes of Figure 2A, as well as their current emulator blocks, would operate in a manner similar to that noted above with respect to SPS 220-1 and current emulator block 350.

[0088] 6. Conclusion [0089] References throughout this specification to “one embodiment”, “an embodiment”, or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment”, “in an embodiment” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0090] While in the illustrations of Figures 1, 2 A, 3 and 4, although terminals/nodes are shown with direct connections to (i.e., “connected to”) various other terminals, it should be appreciated that additional components (as suited for the specific environment) may also be present in the path, and accordingly the connections may be viewed as being “electrically coupled” to the same connected terminals.

[0091] It should be appreciated that the specific type of transistors (such as NMOS, PMOS, etc.) noted above are merely by way of illustration. However, alternative embodiments using different configurations and transistors will be apparent to one skilled in the relevant arts by reading the disclosure provided herein. For example, the NMOS transistors may be replaced with PMOS (P-type MOS) transistors, while also interchanging the connections to power and ground terminals.

[0092] Accordingly, in the instant application, the power and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) terminals of transistors (though which a current path is provided when turned on and an open path is provided when turned off) are termed as current terminals, and the gate (base) terminal is termed as a control terminal.

[0093] While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the abovedescribed embodiments, but should be defined only in accordance with the following claims and their equivalents.