AND METHODS

FIELD

[0001] Various embodiments generally relate to communications and wireless communications.

BACKGROUND

[0002] The requirements and expectations for devices, such as radio frequency (RF) devices, are ever increasing. For example, both higher reliability and higher throughput can be required for new designs.

[0003] Designing devices that meet the increased requirements and

expectations can be problematic. The device designs grow ever larger and complex. The design process becomes ever more challenging.

[0004] One technique to develop devices and related circuitry is to use circuit simulation. This avoids requiring to physically build circuits prior to testing.

[0005] However, circuit simulation can also be problematic. The simulation may not reflect real world implementations and hardware.

[0006] What is needed are techniques to facilitate device design systems and methods using circuit simulation and/or emulation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Fig. 1 is a diagram illustrating an architecture in a WiFi/ RF system in accordance with one or more embodiments.

[0008] Fig. 2 is a diagram illustrating a timeline for various circuitry block development and design 200 for a RF system in accordance with one or more embodiments. [0009] Fig. 3 is a diagram illustrating a method for designing radio frequency

(RF) and/or mixed signal (MS) blocks for a communication system in accordance with some embodiments.

[0010] FIG. 4 is a flow diagram illustrating a method for generating a netlist based on a RF and/or MS design in accordance with some embodiment.

[0011] Fig. 5 is a diagram illustrating an arrangement of a system for performing circuit design in accordance with some embodiments.

DETAILED DESCRIPTION

[0012] The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. The same reference numbers may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of various embodiments. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the various embodiments may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the various embodiments with unnecessary detail.

[0009] Generally, a WiFi system includes a baseband portion/circuitry and a radio frequency (RF) portion/circuitry. The baseband circuitry is typically configured to generate baseband data, which includes data, user data, and the like. The RF circuitry is typically configured to receive the baseband data or signals and process those received signals to generate an RF signal for transmission. Further, the RF circuitry is generally configured reception and down-conversion and/or down-modulation to baseband.

[0010] The RF circuitry typically includes various parts or components, such as mixers, modulators, demodulators, synthesizers, oscillators signal generators, and the like. [0011] The RF circuitry generally utilizes firmware for its operation.

[0012] The design of the RF circuitry and the RF firmware can be problematic. Typically, the RF circuitry is developed prior to designing the RF firmware. As a result, there can be deficiencies in the RF circuitry that are not identified until firmware development. Unfortunately, these deficiencies are typically only found after the RF circuitry has been developed. Thus modification of the RF circuitry can be difficult or not possible.

[0013] One or more embodiments are included that facilitate RF chip/circuitry development and RF firmware development. These embodiments include concurrent design of the RF firmware and the RF circuitry and can avoid other challenges with post RF chip firmware development.

[0014] Fig. 1 is a diagram illustrating an example WiFi system 100 in accordance with one or more embodiments. The system 100 is provided for illustrative purposes and it is appreciated that suitable variations are contemplated.

[0015] The WiFi system 100 includes a baseband chip 102 and an RF chip 104.

The baseband 102 and the RF chip 104 are connected via an interface and/or signal lines 106.

[0016] The system 100 can be at least partially designed, simulated, verified and the like using the included techniques.

[0017] The baseband chip 102 is configured to generate baseband signals. These signals can include a variety of data/information, such as user data, application data, and the like. The baseband chip 102 generates a baseband signal 106, which can be in an analog or digital format. Additionally, the baseband chip can receive a signal (received baseband signal) from the RF chip 104.

[0018] The RF chip 104 is configured to generate an RF signal 108 from the baseband signal 106. The RF signal can be transmitted by one or more antenna. The RF chip 104 is also configured to receive an RF signal and demodulate the received RF signal and generate the received baseband signal.

[0019] The RF chip 104 includes transmitter circuitry, receiver circuitry, modulation circuitry, demodulation circuitry and the like.

[0020] The system 100 can be compatible with one or more WiFi or wireless standards.

[0021] Firmware can be developed for the system 100 using one or more of the below examples. In particular, the firmware (FW) is for the RF chip 104. [0022] The development includes an emulatable netlist provided to a development system, which can serve as a baseline for mapping a behavioral model of the RF chip 104 to digital hardware. The development also includes development of one or more application programmable interfaces (API). The APIs can program the RF chip 104 into a selected state/ mode, such as an idle state, a receiving mode, transmitting mode, debug mode, and the like.

[0023] The development can incorporate application programmable interfaces (APIs), RF APIs, programming of register bits and the like and the emulating the APIs on an emulation platform or hardware emulation platform. Some examples of suitable emulation platforms include FPGA . It is appreciated that the development can be performed before implementing the RF circuitry 104 into silicon.

[0012] Fig. 2 is a diagram illustrating example timelines for various circuitry block development and design 200 for a WiFi communication system in

accordance with one or more embodiments. The timelines for development 200 is provided for illustrative purposes and it is appreciated that suitable variations are contemplated.

[0013] Time is shown progressing and increasing from left to right as shown in Fig. 2.

[0014] The development 200, in one example, is for a wireless communication system that includes an RF design/block and an MS design/block in one example.

The RF design is for RF circuitry that handles radio frequency operations included, but not limited to, generating signals for transmission, modulating signals, up- mixing and/or down-mixing signals with other signals (carrier signals),

demodulation, analog to digital conversion, digital to analog conversion, and the like. The mixed signal design is for MS circuitry that can perform mixing, unmixing and the like.

[0015] Generally, the development 200 includes a design/development phase 212, design production phase 214 and an evaluation and testing phase 216. The design phase 212 is where the blocks/circuitry for RF and MS are initially

designed. Generally, they are designed to meet various performance parameters, specifications, standards, power requirements, and the like.

[0016] In addition to designing/developing the RF and MS blocks, firmware is also developed and designed for the wireless systems, such as WiFi. The

firmware can include non-transitory instructions executed by one or more processors that is performed by circuitry of wireless systems, including the RF and MS blocks.

[0017] In one approach (A) as shown at 202, firmware (FW) and software (SW) verification is performed at the evaluation and testing phase 216A. Here, the RF and MS blocks are designed and developed at design phase 212A. The RF and MS design is produced and/or fabricated at a design production phase 214A.

Then, the design is evaluated, simulated, tested, and the like at evaluation phase 216A.

[0018] The firmware, in approach A, is not developed and/or verified until the evaluation phase 216A as shown at 208.

[0019] In a second approach (B) as shown at 204, firmware (FW) and software (SW) verification is performed during the RF and MS development phase 212B instead of waiting until evaluation phase 216B. The RF and MS design is produced and/or fabricated at a design production phase 214B. Then, the design is evaluated, simulated, tested, and the like at evaluation phase 216B.

[0020] It is appreciated that firmware can be considered a special type of software which runs on a processor core which is typically embedded into a digital (signal) processing block with a specific purpose, e.g. a WIFI communication module which is connected via a standardized interface like PCI-E to a PC, or a Home Gateway, Set Top Box, Network Router. The digital block with the embedded processor typically connects to the analog world via analog and RF frontend blocks for the purpose of sensoring, data transmission, and the like.

[0021] The hardware that operates using the firmware is different from general purpose CPUs/DSPs. For example, firmware using hardware, such as embedded processor cores, have limited instruction sets, limited memory resources, and the firmware only takes care to initialize, configure and operate the hardware blocks of that module and establish the communication to the standardized interface, such that the operating system (in case of a PC or work station) or a firmware of higher level running on a more powerful host controller (like in a gateway, router or set top box) can operate the module.

[0022] The development phase 212B can include RF and MS development and firmware development. Similarly, the design phase 214B and the evaluation phase 216B can also include RF, MS and firmware development. The design phase 212B can generate or result in a circuit design for the RF and MS circuitry. [0023] The design production phase 214B converts the design phase generated circuit design into one or more hardware circuitry. The hardware circuitry can include mixers, amplifiers, modulators and the like. The hardware circuitry is matched to the design or functionality of the design generated at the development phase 212B. The design production phase 214B generates one or more integrated circuits that support or perform the design. In one example, the design production phase 214B includes the silicon or prints to silicon. The generated circuits can be considered final or near final.

[0024] It is noted that the design production phase 214B generates a design that includes RF circuitry, MS circuitry and firmware. The design can be fabricated, emulated and/or simulated.

[0025] The evaluation testing phase 216B evaluates the hardware circuitry generated by the design production phase 214B. The evaluation testing phase 216B can identify errors and/or improvements. However modification of the hardware circuitry at this point can be costly and complex. For example, modification could require modification of the design from the development phase 212B and re-generating or re-developing hardware circuitry at the design production phase 214B.

[0026] One or more models are provided during the development phase 212B. Generation of these models, which includes a final model (314 or 316) are described below. The one or more models can provide application programming interfaces (APIs) and the like that facilitate performance of the development phase 212B.

[0027] Fig. 3 is a diagram illustrating a method 300 for designing radio frequency (RF) and/or mixed signal (MS) blocks for a communication/wireless system in accordance with one or more embodiments.

[0028] The method 300 is described in terms of blocks/acts that can be performed using one or more processors, circuitry, development tools and the like.

[0029] A RF and/or MS circuit for development and design is identified or obtained at block 302. The circuit can be divided into three sets of design components:

[0030] Low Level (LL) analog parts or blocks 304, such as analog devices and circuits used for current and supply distribution and the like. [0031] High Level (HL) analog building blocks 306, such as analog filters, amplifiers, and the like.

[0032] Digital building blocks 308, such as macros, registers, control logic, top level routing and the like.

[0033] LL 304 and HL 306 blocks can be distinguished in terms of the complexity of a suitable behavioral model. By its nature, LL and HL analog building blocks cannot be converted directly into a digital netlist. A netiist is a description of the connectivity of an electronic circuit. In one example, a netiist consists of a list of the electronic components in a circuit and a list of the nodes they are connected to.

[0034] In order to generate such a netiist, appropriate models of those building blocks are written or generated. This can be done in any hardware description language (HDL), e.g. System Verilog (SV). Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed- signal circuits, as well as in the design of genetic circuits.

[0035] Models for LL building blocks 304, referred to as LL Models are written and/or generated and describe simple or very simple functionality (e.g. analog switches, supply generation, and the like). Manual Verilog Coding 310 can be used to generate the LL Models.

[0036] HL building block models, referred to as HL models, generally require more effort/coding that the LL models, particularly if modeling of analog behavior is required/used. In this case, another approach 312 is useful/used:

[0037] For system design and simulation of RF and/or MS circuits, dedicated models (HL models), written in a high-level (system) language like MATLAB, System-C and the like are used. Existing models can be used and converted, automatically in one example, into a synthesizable HDL code. For the later use of those models in an emulation environment, real type data, typically used for representing analog signals (voltages or currents) can be converted into fixed point representation (digital bus with defined bit width). Within this conversion of existing models, accuracy and resolution can be compromised. Generally, this does not limit the achieved quality of RF and/or MS HL models. [0038] In another example, unique HL models are created for each HL block/circuitry.

[0039] In one example, the LL and/or HL models are based on or use register transfer level (RTL).

[0040] It is appreciated that low-level (LL) blocks and corresponding LL models can be blocks with an input-to-output relation, or where the behavioral model of a more complex analog block is simplified to a trivial level. In one example, the LL block is where an output=input for e.g. an analog level-shifter where the level/supply domain change from input to output is irrelevant for the functionality. Generally, low-level blocks are functional blocks and without signal processing blocks. In a high-level system simulation or emulation, these LL blocks may not be modelled. Thus, a description of the block behavior in some high-level description language does not exist a-priori. Examples for low-level blocks are switches, level shifters, summing nodes (to avoid the conflict in digital netlists of multiple input signals connected to just one output), multiplexers, LDOs, etc.

[0041] High-level blocks and corresponding HL models are typically signal processing blocks, i.e. blocks in the regular TX or RX path, or some auxiliary path. Models for such blocks may exist already (pre-exist) in a high-level description language because one uses them for high-level system simulations. However, the pre-existing models tyipically are suitable for conversion to synthesizeable coe because they are too complex. With some simplification, simpler HL models - still in the high-level language - can be devised and/or generate which are then automatically converted to a synthesizable description. Typically, some

impairments of such blocks are also modelled in the HL model to e.g. allow to verify firmware loops that calibrate for the given impairment. Examples of such high-level blocks would be RF or baseband amplifiers, analog buffers, up- conversion and down-conversion mixers, filters, ADCs, DACs, etc.

[0042] It is appreciated that there can be blocks and corresponding models that overlap between HL and LL Thus, there can be blocks that can be modeled use HL models or LL models (direction into a synthesizable language.

[0043] A gate level (GL) netlist 314 is generated using the LL and HL models, such as after a schematic freeze is achieved. The GL netlist can be generated directly out of the digital building blocks and top level routing (block interconnects). In the same netlist, a RTL netlist of the entire available LL and HL models can be generated as well. A GL netlist can be a fitted design before it’s converter to a programming file. The GL netlist can include all of the logic and delays of the final system and allows use of a test bench from the simulation testing to test the final design

[0044] A netlist, in one example, includes a description of the connectivity of an electronic circuit or design. A netlist can include a list of electronic components in a circuit and a list of the nodes they are connected to.

[0045] It is appreciated that analog signals are/can be represented by digital buses. Since analog building block inputs and outputs as well as the

corresponding interconnects are single wire types (as drawn in schematic and written in corresponding models), a netlist formatter, such as netlister, can replace the single wire types by digital buses. For this purpose, the netlister was enhanced which generates a GL netlist comprising the LL and HL analog models and takes care of the bottom-up hierarchal datatype propagation.

[0046] Together with the previously generated GL and RTL netlist, a final synthesizable GL netlist of the entire system 316 can be generated by passing or using a logical synthesis tool. This final netlist is ready for digital simulation 318 (functional verification) and/or emulation 320 on a target. The entire system, in one example, is a communication system/circuity that includes the RF and/or MS circuits.

[0047] The described methodology 300 provides a single source (analog

models, schematics) approach to the final emulate-able netlist.

[0048] FIG. 4 is a flow diagram illustrating a method 400 for generating a netlist based on a RF and/or MS design in accordance with some embodiment. The method 400 can be performed using circuitry, a control unit and the like. In one example, a control unit having one or more processors is used to perform the method 400.

[0049] The method 200 can be referenced for additional description of the method 400.

[0050] The method 400 begins at 402, wherein a circuit design is provided. The circuit design includes RF designs, MS designs, analog circuit designs and the like.

[0051] The circuit design allocated or segmented into various building blocks at 404. The various building blocks include analog building blocks, such as low level (LL) building blocks and high level (HL) building blocks. The LL building blocks include parts for current, supply distribution, and the like.

[0052] The various building blocks can also include digital building blocks, such as macros, registers, control logic, top level routing and the like.

[0053] LL models are generated based on the LL building blocks, HL models are generated based on the HL building blocks and digital models are generated based on the digital building blocks at 406. In one example, Verilog Coding is used to generate the models. Verilog is a standardized hardware description language (HDL).

[0054] The HL models, the LL models, and the digital models are combined at 408 to form an overall model or netlist. The netlist can be an RTL and/or GL netlist. In one example, a netlist formatter or netlister can be used to generate the netlist based on the models.

[0055] The overall model or netlist is processed at 410 to generate a final model or final netlist. In one example, the final synthesizeable GL netlist for a system is generated by passing or using logical synthesis tool of or with the overall model or netlist from 408.

[0056] The final model or final netlist can be used for digital simulation or

verification at 412. In one example, the verification can be performed in

accordance with the approach 104, with FW/SW verification. The final model or netlist can also be used for emulation on a target.

[0057] Fig. 5 is a diagram illustrating an arrangement of a system 500 for performing circuit design in accordance with some embodiments. The system 500 is provided for illustrative purposes and it is appreciated that suitable variations of the system 500 are contemplated.

[0058] The system 500 can be used to perform the development 100, approach 204, the method 200, the method 300 and the like.

[0059] The system 500 includes design circuitry 502 and simulation circuitry 504.

[0060] The design circuitry 502 includes one or more processors configured to execute instructions from a memory to perform the development 100, the method 200 and the method 300 and variations thereof. The circuitry 502 can also utilize one or more interfaces including input interfaces and output interfaces. [0061] The design circuitry 502 receives input, such as a circuit design. In one example, the circuit design includes an RF design and/or a MS design. The design circuitry 502 is configured to generate building block models based on the circuit design. The design circuitry 502 is also configured to generate a final model or final netlist, as described above, such as using the method 200. The circuitry 502 is shown with outputs at 510 and 508, however it is appreciated that other outputs are contemplated.

[0062] The output 508, also referred to as a model output, provides high level and/or low level models and can include a final model or final netlist. The model output 508 can be provided in the form of Matlab models and the like. The models simulate the dynamic operation of associated blocks.

[0063] The output 510 is a generic output for information. The information can include and/or be provided for monitoring the model generation, environmental variable, various parameters, indicating modeling progress and the like.

[0064] The simulation circuitry 504 includes one or more processors configured to execute instructions from a memory to perform at least a portion of the development 100, the method 200 and the method 300 and variations thereof. The circuitry 504 can also utilize one or more interfaces including input interfaces and output interfaces.

[0065] It is appreciated that the design/development circuitry 502 and the emulation circuitry 504 can exist on a single chip, circuitry and the like. Alternatively, the development circuitry 502 and the emulation circuitry 504 can also be located on separate circuitry and/or chips.

[0060] The simulation circuitry 504 is configured to simulate and/or emulate the circuit design and/or an overall circuit design using the final model or final netlist

[0061] As utilized above and herein, terms“component,”“system,”“interface,” and the like are intended to refer to a computer-related entity, hardware, software (e.g., in execution), and/or firmware. For example, a component can be a processor, a process running on a processor, a controller, an object, an executable, a program, a storage device, and/or a computer with a processing device. By way of illustration, an application running on a server and the server can also be a component. One or more components can reside within a process, and a component can be localized on one computer and/or distributed between two or more computers. A set of elements or a set of other components can be described herein, in which the term“set” can be interpreted as one or more. [0062] Further, these components can execute from various computer readable storage media having various data structures stored thereon such as with a module, for example. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network, such as, the Internet, a local area network, a wide area network, or similar network with other systems via the signal).

[0063] As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, in which the electric or electronic circuitry can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts; the electronic components can include one or more processors therein to execute software and/or firmware that confer(s), at least in part, the functionality of the electronic components.

[0064] Use of the word exemplary is intended to present concepts in a concrete fashion. As used in this application, the term“or” is intended to mean an inclusive“or” rather than an exclusive“or”. That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then“X employs A or B” is satisfied under any of the foregoing instances. In addition, the articles“a” and“an” as used in this application and the appended claims should generally be construed to mean“one or more” unless specified otherwise or clear from context to be directed to a singular form. Furthermore, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term

"comprising".

[0065] As used herein, the term“circuitry” may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware componentsthat provide the described functionality. In some embodiments, the circuitry may be implemented in, or functions associated with the circuitry may be implemented by, one or more software or firmware modules. In some embodiments, circuitry may include logic, at least partially operable in hardware.

[0066] As it employed in the subject specification, the term“processor” can refer to substantially any computing processing unit or device including, but not limited to including, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology;

parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit, a digital signal processor, a field programmable gate array, a programmable logic controller, a complex programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions and/or processes described herein. Processors can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of mobile devices. A processor may also be implemented as a combination of computing processing units.

[0067] In the subject specification, terms such as“store,”“data store,” data storage,” “database,” and substantially any other information storage component relevant to operation and functionality of a component and/or process, refer to“memory

components,” or entities embodied in a“memory,” or components including the memory. It is noted that the memory components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.

[0068] By way of illustration, and not limitation, nonvolatile memory, for example, can be included in a memory, non-volatile memory (see below), disk storage (see below), and memory storage (see below). Further, nonvolatile memory can be included in read only memory, programmable read only memory, electrically programmable read only memory, electrically erasable programmable read only memory, or flash memory. Volatile memory can include random access memory, which acts as external cache memory. By way of illustration and not limitation, random access memory is available in many forms such as synchronous random access memory, dynamic random access memory, synchronous dynamic random access memory, double data rate synchronous dynamic random access memory, enhanced synchronous dynamic random access memory, Synchlink dynamic random access memory, and direct Rambus random access memory. Additionally, the disclosed memory components of systems or methods herein are intended to include, without being limited to including, these and any other suitable types of memory.

[0069] Examples can include subject matter such as a method, means for performing acts or blocks of the method, at least one machine-readable medium including instructions that, when performed by a machine cause the machine to perform acts of the method or of an apparatus or system for concurrent communication using multiple communication technologies according to embodiments and examples described herein.

[0070] Example 1 is an apparatus for generating a circuit models. The apparatus includes circuitry that has a memory and one or more processors. The one or more processors are configured to segment a design into a plurality of building blocks; model the plurality of building blocks to generate a plurality of block models; combine the block models into a composite model; and process or synthesize the composite model into a final model.

[0071] Example 2 includes the subject matter of Example 1 , including or omitting optional elements, wherein at least a portion of the block models are generated using higher level blocks and then converting the higher level blocks to a synthesizeable language.

[0072] Example 3 includes the subject matter of any of Examples 1 -2, including or omitting optional elements, wherein the final model includes modeling of radio frequency circuitry.

[0073] Example 4 includes the subject matter of any of Examples 1 -3, including or omitting optional elements, wherein suitable operation of the final model if verified using emulation.

[0074] Example 5 includes the subject matter of any of Examples 1 -4, including or omitting optional elements, wherein the emulation is performed on a field programmable gate array (FPGA) equipped circuitry.

[0075] Example 6 includes the subject matter of any of Examples 1 -5, including or omitting optional elements, wherein the plurality of block models are based on preexisting models having similar and varied functionality.

[0076] Example 7 includes the subject matter of any of Examples 1 -6, including or omitting optional elements, wherein the plurality of block models include high level (HL) models, low level (LL) models and the final model includes the HL models, LL models and digital sub-blocks/circuitry.

[0077] Example 8 includes the subject matter of any of Examples 1 -7, including or omitting optional elements, wherein the design includes a firmware design.

[0078] Example 9 includes the subject matter of any of Examples 1 -8, including or omitting optional elements, wherein the design includes a mixed signal (MS) design.

[0079] Example 10 includes the subject matter of any of Examples 1 -9, including or omitting optional elements, wherein at least a portion of the blocks are based on Matlab.

[0080] Example 1 1 includes the subject matter of any of Examples 1 -10, including or omitting optional elements, wherein the final model is generated as an output of a design phase.

[0081] Example 12 is an apparatus for verifying operation of radio frequency (RF) and mixed signal (MS) circuitry. The apparatus can include circuitry that has a memory and one or more processors. The one or more processors are configured to obtain a design for the RF and MS circuitry; generate high level analog blocks and low level analog blocks for the design; generate high level models for the high level analog blocks and low level models for the low level analog blocks; combine the high level models and the low level models into a netlist; and synthesize the netlist into a final model prior to design production.

[0082] Example 13 includes the subject matter of Example 12, including or omitting optional elements, wherein at least a portion of the block models are generated using higher level blocks and then converting the higher level blocks to a synthesizeable language.

[0083] Example 14 includes the subject matter of any of Examples 12-13, including or omitting optional elements, wherein the low level analog blocks include current distribution circuitry, signal distribution circuitry and supply distribution circuitry.

[0084] Example 15 includes the subject matter of any of Examples 12-14, including or omitting optional elements, wherein the high level analog blocks include filters and amplifiers.

[0085] Example 16 includes the subject matter of any of Examples 12-15, including or omitting optional elements, further comprising generating digital building blocks for the design, wherein the digital building blocks include registers and control logic.

[0086] Example 17 includes the subject matter of any of Examples 12-16, including or omitting optional elements, further comprising emulation circuitry configured to emulate operation of the final model and wherein the one or more processors are configured to verify operation of the final model based on output from the emulation circuitry.

[0087] Example 18 is a method for generating a final netlist based model. The method includes segmenting or allocating the circuit design into a plurality of blocks, wherein the plurality of blocks include low level blocks and high level blocks; modeling the high level blocks to generate one or more high level models; modeling the low level blocks to generate one or more low level models; combining the high level models and the low level models into a single netlist based model; and verifying operation of the single netlist based model using simulation and emulation prior to design production.

[0088] Example 19 includes the subject matter of Example 18, including or omitting optional elements, wherein the circuit design is RF and/or MS design(s).

[0089] Example 20 includes the subject matter of any of Examples 18-19, including or omitting optional elements, further comprising emulating operation of the single netlist based model using hardware emulation.

[0090] Example 21 includes the subject matter of any of Examples 18-20, including or omitting optional elements, wherein the design production includes a production start of a chip for of the circuit design.

[0091] Example 22 includes the subject matter of any of Examples 18-21 , including or omitting optional elements, wherein modeling the high level blocks uses Matlab modeling and converting the Matlab modeling into verilog.

[0092] It is to be understood that aspects described herein can be implemented by hardware, software, firmware, or any combination thereof. When implemented in software, functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media or a computer readable storage device can be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD- ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other tangible and/or non-transitory medium, that can be used to carry or store desired information or executable instructions. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

Combinations of the above should also be included within the scope of computer- readable media.

[0093] Various illustrative logics, logical blocks, modules, and circuits described in connection with aspects disclosed herein can be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other

programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform functions described herein. A general-purpose processor can be a microprocessor, but, in the alternative, processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Additionally, at least one processor can comprise one or more modules operable to perform one or more of the s and/or actions described herein.

[0094] For a software implementation, techniques described herein can be implemented with modules (e.g., procedures, functions, and so on) that perform functions described herein. Software codes can be stored in memory units and executed by processors. Memory unit can be implemented within processor or external to processor, in which case memory unit can be communicatively coupled to processor through various means as is known in the art. Further, at least one processor can include one or more modules operable to perform functions described herein.

[0095] Techniques described herein can be used for various wireless

communication systems such as CDMA, TDMA, FDMA, OFDMA, SC-FDMA and other systems. The terms“system” and“network” are often used interchangeably. A CDMA system can implement a radio technology such as Universal Terrestrial Radio Access (UTRA), CDMA1800, etc. UTRA includes Wideband-CDMA (W-CDMA) and other variants of CDMA. Further, CDMA1800 covers IS-1800, IS-95 and IS-856 standards. A TDMA system can implement a radio technology such as Global System for Mobile Communications (GSM). An OFDMA system can implement a radio technology such as Evolved UTRA (E-UTRA), Ultra Mobile Broadband (UMB), IEEE 802.1 1 (Wi-Fi),

IEEE 802.16 (WiMAX), IEEE 802.18, Flash-OFDM, etc. UTRA and E-UTRA are part of Universal Mobile Telecommunication System (UMTS). 3GPP Long Term Evolution (LTE) is a release of UMTS that uses E-UTRA, which employs OFDMA on downlink and SC-FDMA on uplink. UTRA, E-UTRA, UMTS, LTE and GSM are described in documents from an organization named“3rd Generation Partnership Project” (3GPP). Additionally, CDMA1800 and UMB are described in documents from an organization named“3rd Generation Partnership Project 2” (3GPP2). The techniques can also be used with new radio (NR) 5G, also from the 3GPP organization. Further, such wireless communication systems can additionally include peer-to-peer (e.g., mobile-to-mobile) ad hoc network systems often using unpaired unlicensed spectrums, 802. xx wireless LAN, BLUETOOTH and any other short- or long- range, wireless communication techniques.

[0096] Single carrier frequency division multiple access (SC-FDMA), which utilizes single carrier modulation and frequency domain equalization is a technique that can be utilized with the disclosed aspects. SC-FDMA has similar performance and essentially a similar overall complexity as those of OFDMA system. SC-FDMA signal has lower peak-to-average power ratio (PAPR) because of its inherent single carrier structure. SC-FDMA can be utilized in uplink communications where lower PAPR can benefit a mobile terminal in terms of transmit power efficiency.

[0097] Moreover, various aspects or features described herein can be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques. The term "article of manufacture" as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. For example, computer-readable media can include but are not limited to magnetic storage devices {e.g., hard disk, floppy disk, magnetic strips, etc.), optical disks {e.g., compact disk (CD), digital versatile disk (DVD), etc.), smart cards, and flash memory devices {e.g., EPROM, card, stick, key drive, etc.). Additionally, various storage media described herein can represent one or more devices and/or other machine-readable media for storing information. The term“machine-readable medium” can include, without being limited to, wireless channels and various other media capable of storing, containing, and/or carrying instruction(s) and/or data. Additionally, a computer program product can include a computer readable medium having one or more instructions or codes operable to cause a computer to perform functions described herein.

[0098] Communications media embody computer-readable instructions, data structures, program modules or other structured or unstructured data in a data signal such as a modulated data signal, e.g., a carrier wave or other transport mechanism, and includes any information delivery or transport media. The term“modulated data signal” or signals refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in one or more signals. By way of example, and not limitation, communication media include wired media, such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.

[0099] Further, the actions of a method or algorithm described in connection with aspects disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or a combination thereof. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium can be coupled to processor, such that processor can read information from, and write information to, storage medium. In the alternative, storage medium can be integral to processor. Further, in some aspects, processor and storage medium can reside in an ASIC. Additionally,

ASIC can reside in a user terminal. In the alternative, processor and storage medium can reside as discrete components in a user terminal. Additionally, in some aspects, the s and/or actions of a method or algorithm can reside as one or any combination or set of codes and/or instructions on a machine-readable medium and/or computer readable medium, which can be incorporated into a computer program product.

[00100] The above description of illustrated embodiments of the subject disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as those skilled in the relevant art can recognize. [00101] In this regard, while the disclosed subject matter has been described in connection with various embodiments and corresponding Figures, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below.

[00102] In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms

(including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.