Title:
AN EMULATION SYSTEM HAVING A EFFICIENT EMULATION SIGNAL ROUTING ARCHITECTURE
Document Type and Number:
WIPO Patent Application WO2001031516
Kind Code:
A3
Abstract:
An emulation system having an efficient I/O pin utilization architecture is disclosed. The emulation system includes a number of reconfigurable logic chips and circuit design mapping software that operates to map a circuit design onto the reconfigurable logic chips to realize and emulate the circuit design. Each logic chip includes a number of buffered I/O pins. Each buffered I/O pin has associated multiplexing circuitry that operates to time multiplex input/output of multiple emulation signals through the buffered I/O pin. The circuit design mapping software operates to interconnect allocated logic resources. All emulation signal fan outs are confined within the logic chips, and output through the buffered I/O pins in a time multiplexed manner, employing multiple signal routing timing domains. Additionally/alternatively, emulation signal routing between logic chips of the same logic board are also confined to their direct connections to provide deterministic timing delay within the logic board.
Inventors:
REBLEWSKI FREDERIC
Application Number:
PCT/US2000/019744
Publication Date:
January 17, 2002
Filing Date:
July 19, 2000
Export Citation:
Assignee:
MENTOR GRAPHICS CORP (US)
International Classes:
G06F15/78; G06F17/50; H03K19/00; (IPC1-7): G06F17/50
Foreign References:
| US5960191A | 1999-09-28 | |||
| US5761484A | 1998-06-02 |
Other References:
LI J ET AL: "ROUTABILITY IMPROVEMENT USING DYNAMIC INTERCONNECT ARCHITECTURE", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,US,IEEE INC. NEW YORK, vol. 6, no. 3, 1 September 1998 (1998-09-01), pages 498 - 501, XP000782324, ISSN: 1063-8210
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