DESCRIPTION

ENCODER, DECODER, AND TELEVISION RECEIVER TECHNICAL FIELD

[0001]

One embodiment of the present invention disclosed in the specification, the drawings, and the claims (hereinafter referred to as "the specification and the like") relates to an encoder, a decoder, and a television receiver. Note that one embodiment of the present invention is not limited to the above technical fields.

BACKGROUND ART

[0002]

A basic current source circuit of a CMOS circuit can include a current mirror. A current source circuit (source current source) can be formed using a current mirror circuit including p-channel transistors; a current sink circuit (sink current source) can be formed using a current mirror circuit including n-channel transistors.

[0003]

For example, Patent Document 1 discloses a current amplifier circuit which can selectively output a source current that is set in a PMOS current mirror circuit or a sink current that is set in an NMOS current mirror circuit and whose output current level can be changed in accordance with an input signal.

[0004]

A variety of semiconductor devices that take advantage of an extremely low off-state current of a transistor whose channel formation region includes an oxide semiconductor

(hereinafter, the transistor is referred to as a metal oxide semiconductor transistor or an OS transistor) have been proposed. For example, Patent Document 2 discloses a transmitter and a receiver of a broadcast system which include an OS transistor.

[Reference]

[Patent Document]

[0005]

[Patent Document 1] Japanese Published Patent Application No. 2014-26390

[Patent Document 2] United States Patent Application Publication No. 2016/0295152 DISCLOSURE OF INVENTION [0006]

An object of one embodiment of the present invention is to reduce the circuit area, to reduce power consumption, to enable power gating, or the like.

[0007]

Note that the description of a plurality of objects does not mutually preclude the existence. One embodiment of the present invention does not necessarily achieve all the objects listed above. Objects other than those listed above are apparent from the description of this specification and the like, and such objects could be objects of one embodiment of the present invention.

[0008]

(1) One embodiment of the present invention is a decoder that decompresses image data. The decoder includes an inverse discrete cosine transform circuit. The inverse discrete cosine transform circuit includes a multiplier circuit. The multiplier circuit includes an arithmetic circuit that multiplies a first current and a second current, a current generator that generates the first current, and a digital-analog converter that generates a reference current by analog-converting digital data. The current generator includes a current mirror circuit including a first transistor and a second transistor, a third transistor, a first memory circuit, a second memory circuit, a switch, and an output terminal for outputting the first current. A first voltage stored in the first memory circuit is input to a gate of the second transistor. A second voltage stored in the second memory circuit is input to a gate of the third transistor. A third voltage is input to a first terminal of the first transistor and a first terminal of the second transistor. A fourth voltage is input to a first terminal of the third transistor. The reference current is input to a second terminal of the first transistor. A second terminal of the second transistor and a second terminal of the third transistor are electrically connected to each other. The switch controls electrical connection between the second terminal of the second transistor and the output terminal.

[0009]

(2) One embodiment of the present invention is an encoder that compresses image data. The encoder includes a discrete cosine transform circuit. The discrete cosine transform circuit includes a multiplier circuit. The multiplier circuit includes an arithmetic circuit that multiplies a first current and a second current, a current generator that generates the first current, and a digital-analog converter that generates a reference current by analog-converting digital data. The current generator includes a current mirror circuit including a first transistor and a second transistor, a third transistor, a first memory circuit, a second memory circuit, a switch, and an output terminal for outputting the first current. A first voltage stored in the first memory circuit is input to a gate of the second transistor. A second voltage stored in the second memory circuit is input to a gate of the third transistor. A third voltage is input to a first terminal of the first transistor and a first terminal of the second transistor. A fourth voltage is input to a first terminal of the third transistor. The reference current is input to a second terminal of the first transistor. A second terminal of the second transistor and a second terminal of the third transistor are electrically connected to each other. The switch controls electrical connection between the second terminal of the second transistor and the output terminal.

[0010]

(3) The first memory circuit according to (1) or (2) includes a first capacitor and a fourth transistor. The first capacitor is electrically connected to the gate of the second transistor.

The second memory circuit includes a second capacitor and a fifth transistor. The second capacitor is electrically connected to a gate of the third transistor. The gate of the second transistor is brought into an electrically floating state by the fourth transistor. The gate of the third transistor is brought into an electrically floating state by the fifth transistor. A channel formation region of the fourth transistor and a channel formation region of the fifth transistor each include an oxide semiconductor.

[0011]

(4) One embodiment of the present invention is a television receiver including the decoder according to (1).

[0012]

In this specification and the like, ordinal numbers such as "first", "second", and "third" may be used to show the order. Furthermore, ordinal numbers may be used to avoid confusion among components but do not limit the number or the order of components. For example, it is possible to replace "first" with "second" or "third" in the description of one embodiment of the invention.

[0013]

In this specification, terms for explaining arrangement, such as "over" and "under", are sometimes used for convenience to describe the positional relation between components with reference to drawings. The positional relation between components is changed as appropriate in accordance with the direction in which the components are described. Thus, the positional relation is not limited by a term used in the specification and can be described with another term as appropriate depending on the circumstances.

[0014]

In this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, and means a circuit including a semiconductor element (e.g., a transistor, a diode, or a photodiode), a device including the circuit, and the like. The semiconductor device also means any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component including a chip in a package are examples of semiconductor devices. Moreover, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, and the like themselves might be semiconductor devices, or might each include a semiconductor device.

[0015]

In this specification and the like, a description " and Y are connected" means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, without being limited to a predetermined connection relation, for example, a connection relation other than that shown in a drawing or text is also possible. X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

[0016]

A transistor has three terminals: a gate, a source, and a drain. The gate is a control terminal for controlling the on/off state of the transistor. Two terminals functioning as a source and a drain are input/output terminals of the transistor. Functions of the input/output terminals of the transistor depend on the type (n-type or p-type) and the levels of voltages applied to the terminals, and one of the two terminals serves as a source and the other serves as a drain. Therefore, in this specification and the like, the terms "source" and "drain" can be used to denote the drain and the source, respectively. In this specification and the like, the two terminals other than the gate may also be referred to as a first terminal and a second terminal or as a third terminal and a fourth terminal.

[0017]

A node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on the circuit configuration, the device structure, or the like. Furthermore, a terminal, a wiring, or the like can be referred to as a node.

[0018]

A voltage usually refers to a potential difference between a given potential and a reference potential (e.g., a ground potential (G D) or a source potential). Thus, a voltage can be referred to as a potential. Note that a potential has a relative value. Accordingly, GND does not necessarily mean 0 V.

[0019]

In this specification and the like, the terms "film" and "layer" can be interchanged with each other depending on the case or circumstances. For example, in some cases, the term "conductive film" can be used instead of the term "conductive layer", and the term "insulating layer" can be used instead of the term "insulating film".

[0020]

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, one embodiment of the present invention is not limited to such a scale. Note that the drawings schematically show ideal examples, and one embodiment of the present invention is not limited to a shape or a value shown in the drawings. For example, variation in signal, voltage, or current due to noise or difference in timing can be included.

[0021]

According to one embodiment of the present invention, the circuit area can be reduced, power consumption can be reduced, or power gating can be performed, for example.

[0022]

The description of the plurality of effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects described above. In one embodiment of the present invention, an object and an effect other than those described above and a novel feature will be apparent from the description of the specification and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0023]

FIG. 1 is a block diagram illustrating a structure example of a broadcast system.

FIG. 2 is a schematic view illustrating an example of data transmission in a broadcast system.

FIGS. 3 A to 3D are schematic views illustrating examples of a receiver.

FIG. 4 illustrates a structure example of an image distribution system in the medical field.

FIG. 5 is a block diagram illustrating a structure example of an encoder.

FIG. 6 is a block diagram illustrating a structure example of a decoder.

FIG. 7A is a block diagram illustrating a configuration example of a multiplier circuit and FIG. 7B is a circuit diagram illustrating a configuration example of a current generator.

FIGS. 8A to 8E are circuit diagrams illustrating an operation example of the current generator illustrated in FIG. 7B.

FIG. 9 is a timing chart showing an operation example of the multiplier circuit illustrated in FIG. 7 A. FIG. 10 is a circuit diagram illustrating a configuration example of a multiplier circuit.

FIG. 11 is a circuit diagram illustrating a configuration example of a multiplier circuit.

FIG. 12 is a timing chart showing an operation example of the multiplier circuit illustrated in FIG. 11.

FIG. 13 is a circuit diagram illustrating a configuration example of a multiplier circuit. FIG. 14 is a circuit diagram illustrating a configuration example of a multiplier circuit. FIG. 15 is a circuit diagram illustrating a configuration example of a multiplier circuit. FIG. 16 is a cross-sectional view illustrating a configuration example of a multiplier circuit.

FIG. 17 is a cross-sectional view illustrating a structure example of an OS transistor. FIG. 18 is a cross-sectional view illustrating a structure example of an OS transistor. FIG. 19 is a cross-sectional view illustrating a structure example of an OS transistor. FIG. 20 is a cross-sectional view illustrating a structure example of an OS transistor. BEST MODE FOR CARRYING OUT THE INVENTION

[0024]

Embodiments of the present invention will be described below. Note that one embodiment of the present invention is not limited to the following description. It will be readily appreciated by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be construed as being limited to the description of the embodiments below.

[0025]

Any of the embodiments described below can be combined as appropriate. When a plurality of structure examples (including a manufacturing method example, an operating method example, a usage example, and the like) are shown in one embodiment, any of the structure examples can be combined with each other or combined with one or more structure examples described in the other embodiment as appropriate.

[0026]

In the drawings, the same elements, elements having similar functions, elements formed of the same material, elements formed at the same time, or the like are sometimes denoted by the same reference numerals, and description thereof is not repeated in some cases.

[0027]

Even when a block diagram illustrates one circuit block for performing processing, a plurality of circuit blocks may be actually provided to perform the processing. Such a case is in the category of one embodiment of the present invention. Even when a block diagram illustrates a plurality of circuit blocks with different functions, one circuit block may be actually provided to have a plurality of functions. Such a case is also in the category of one embodiment of the present invention.

[0028]

(Embodiment 1)

In this embodiment, a broadcast system, a semiconductor device which constructs the broadcast system, and the like are described.

[0029]

«Broadcast system»

FIG. 1 is a block diagram schematically illustrating a structure example of a broadcast system. A broadcast system 100 illustrated in FIG. 1 includes a camera 110, a transmitter 115, a receiver 120, and a display device 125. The camera 110 includes an image sensor 111 and an image processor 112. The transmitter 115 includes an encoder 116 and a modulator 117. The receiver 120 includes a demodulator 121 and a decoder 122. The display device 125 includes an image processor 126 and a display portion 127.

[0030]

When the camera 110 is capable of taking an 8K video, the image sensor 111 includes a sufficient number of pixels to capture an 8K color image. For example, when each pixel includes one red (R) subpixel, two green (G) subpixels, and one blue (B) subpixel, the image sensor 111 includes at least 7680 x 4320 x 4 [R, G + G, and B] pixels. When the camera 110 is capable of taking a 4K video, the image sensor 111 includes at least 3840 x 2160 x 4 pixels, and when the camera 110 is capable of taking a 2K video, the image sensor 111 includes at least 1920 x 1080 x 4 pixels.

[0031]

The image sensor 111 outputs Raw data 150. The image processor 112 performs image processing (e.g., noise removal or interpolation) on the Raw data 150 and generates image data 151. The image data 151 is output to the transmitter 115.

[0032]

The transmitter 115 processes the image data 151 and generates a broadcast signal

(carrier wave) 153 that accords with a broadcast band. To reduce the amount of data to be transmitted, the encoder 116 generates encoded data 152 by processing the image data 151. The encoder 116 performs processing such as encoding of the image data 151, addition of broadcast control data (e.g., authentication data) to the image data 151, encryption, or scrambling (data rearrangement for spread spectrum). [0033]

The modulator 117 performs IQ modulation (quadrature amplitude modulation) on the encoded data 152 to generate and output the broadcast signal 153. The broadcast signal 153 is a composite signal including data on an I (identical phase) component and a Q (quadrature phase) component. A TV broadcast station plays a role in obtaining the image data 151 and supplying the broadcast signal 153.

[0034]

The receiver 120 receives the broadcast signal 153. The receiver 120 has a function of converting the broadcast signal 153 into image data 154 that can be displayed on the display device 125. The demodulator 121 demodulates the broadcast signal 153 and decomposes it into two analog signals: an I signal and a Q signal.

[0035]

The decoder 122 has a function of converting the I signal and the Q signal into a digital signal. The decoder 122 executes various processing on the digital signal and generates a data stream. This processing includes frame separation, decryption of a low density parity check (LDPC) code, separation of broadcast control data, descrambling, and the like. The decoder 122 decodes the data stream and generates the image data 154.

[0036]

The image data 154 is input to the image processor 126 of the display device 125. The image processor 126 processes the image data 154 and generates a data signal 155 that can be input to the display portion 127. Examples of the processing by the image processor 126 include image processing (gamma processing) and digital-analog conversion. When receiving the data signal 155, the display portion 127 displays an image. In the case where the display portion 127 displays a high-resolution image, the number of pixels of the display portion 127 is preferably, for example, 8K (7680 x 4320), 4K (3840 x 2160), 2K (1920 x 1080), or IK (1280 x 720).

[0037]

FIG. 2 schematically illustrates data transmission in the broadcast system. FIG. 2 illustrates a path in which a radio wave (a broadcast signal) transmitted from a broadcast station 161 is delivered to a television receiver 160 (a TV 160) of every household. The TV 160 is provided with the receiver 120 and the display device 125.

[0038]

As examples of an artificial satellite 162, a communication satellite (CS) and a broadcast satellite (BS) can be given. As examples of an antenna 164, a BS- 110° CS antenna and a CS antenna can be given. As examples of an antenna 165, an ultra-high frequency (UHF) antenna can be given.

[0039]

Radio waves 166A and 166B are broadcast signals for a satellite broadcast. The artificial satellite 162 transmits the radio wave 166B toward the ground when receiving the radio wave 166 A. The antenna 164 of every household receives the radio wave 166B, and a satellite TV broadcast can be watched on the TV 160. Alternatively, the radio wave 166B is received by an antenna of another broadcast station, and a receiver in the broadcast station processes the radio wave 166B into a signal that can be transmitted to an optical cable. The broadcast station transmits the broadcast signal to the TV 160 of every household using an optical cable network. Radio waves 167A and 167B are broadcast signals for a terrestrial broadcast. A radio wave tower 163 amplifies the received radio wave 167 A and transmits it as the radio wave 167B. A terrestrial TV broadcast can be watched on the TV 160 of every household when the antenna 165 receives the radio wave 167B.

[0040]

FIGS. 3 A to 3D each illustrate an example in which a TV broadcast can be watched using a receiver independent from the TV 160. A receiver 171 may be provided outside the TV 160 (FIG. 3 A). Data may be transmitted and received between the antennas 164 and 165 and the TV 160 via wireless devices 172 and 173 (FIG. 3B). In this case, the wireless device 172 or 173 functions as a receiver. The wireless device 173 may be incorporated in the TV 160 (FIG. 3C).

[0041]

The size of a receiver can be reduced so that it can be portable. A receiver 174 illustrated in FIG. 3D includes a connector portion 175. If a display device and an electronic device such as an information terminal (e.g., a personal computer, a smartphone, a mobile phone, or a tablet terminal) include a terminal capable of being connected to the connector portion 175, they can be used to watch a satellite broadcast or a terrestrial broadcast.

[0042]

An image distribution system of this embodiment is not limited to a system for a TV broadcast. Image data to be distributed may be either moving image data or still image data.

[0043]

For example, image data 141 of the camera 110 may be distributed via a high-speed IP network. The distribution system of the image data 141 can be used in, for example, the medical field for remote diagnosis and remote treatment. For accurate image diagnosis and medical practice, an image used for medical practice is required to have a high definition, and the distribution system of the image data that can be displayed on a high-resolution display device (8K, 4K, or 2K) is required. FIG. 4 schematically illustrates an emergency medical system using the distribution system of the image data.

[0044]

A high-speed network 185 performs communication between an emergency transportation vehicle (an ambulance) 180 and a medical institution 181 and between the medical institution 181 and a medical institution 182. The ambulance 180 is equipped with a camera 190, an encoder 191, and a communication device 192.

[0045]

A patient taken to the medical institution 181 is photographed with the camera 190. Image data 156 obtained with the camera 190 can be transmitted in an uncompressed state by the communication device 192, so that the high-resolution image data 156 can be transmitted to the medical institution 181 with a short delay because no time is required for compression of the image data 156. In the case where the high-speed network 185 cannot be used for the communication between the ambulance 180 and the medical institution 181, the image data can be encoded with the encoder 191 and encoded image data 157 can be transmitted.

[0046]

In the medical institution 181, a communication device 195 receives the image data transmitted from the ambulance 180. When the received image data is uncompressed data, the data is transmitted and displayed on a display device 197 via the communication device 195. When the image data is compressed data, the data is expanded with a decoder 196 and then transmitted and displayed on the display device 197. Judging from the image on the display device 197, doctors instruct crews of the ambulance 180 or staff members in the medical institution 181 who treat the patient. The doctors can check the condition of the patient in detail in the medical institution 181 while the patient is taken by the ambulance because the distribution system in FIG. 4 can transmit a high-definition image. Therefore, the doctors can instruct the ambulance crews or the staff members appropriately in a short time, resulting in improvement of a lifesaving rate of patients.

[0047]

The communication of image data between the medical institution 181 and the medical institution 182 can be performed in the same way. A medical image obtained from an image diagnostic device (such as CT or MRI) of the medical institution 181 can be transmitted to the medical institution 182. Here, the ambulance 180 is given as an example of the means to transport patients; however, an aircraft such as a helicopter or a vessel may be used.

[0048]

In the broadcast system 100 in FIG. 1, the decoder 122 can be combined with dedicated IC or processor (e.g., GPU or CPU), for example. The decoder 122 can be integrated into one dedicated IC chip. Alternatively, some or all dedicated ICs can be configured with a programmable logic device (e.g., an FPGA). The same applies to the encoder 116. Specific structure examples of the encoder and the decoder are described below.

[0049]

«Encoder»

An encoder 201 illustrated in FIG. 5 can perform image compression in accordance with H.265/HEVC.

[0050]

The encoder 201 includes a block divider 210, a subtractor circuit 211, a discrete cosine transform (DCT) circuit 212, a quantization circuit 213, an entropy coding circuit 214, a header adding circuit 215, an inverse quantization circuit 216, an inverse discrete cosine transform (IDCT) circuit 217, an adder circuit 218, an inter-frame prediction circuit 221, an intra-frame prediction circuit 222, and a frame memory 223.

[0051]

The block divider 210 divides image data into a plurality of blocks that are formed by data of pixels arranged in a square. Such a block is a unit of each processing in the encoder 201 and is called a coding tree unit (CTU).

[0052]

The subtractor circuit 211 compares a CTU before coding and a reference CTU. The

DCT circuit 212 has a function of performing discrete cosine transform on the CTU. The quantization circuit 213 has a function of performing a quantization processing on the CTU subjected to discrete cosine transform. The entropy coding circuit 214 performs an entropy coding processing on the CTU subjected to the quantization processing. The CTU subjected to the entropy coding processing is integrated into one image data in the header adding circuit 215. The image data is given comparison data in the header adding circuit 215.

[0053]

The inverse quantization circuit 216 performs inverse quantization processing on the CTU subjected to the quantization processing. The IDCT circuit 217 performs inverse discrete cosine transform on the CTU subjected to the inverse quantization processing. The adder circuit 218 combines information on difference calculated in the inter-frame prediction circuit 221 or information on difference calculated in the intra-frame prediction circuit 222 with the CTU subjected to the inverse discrete cosine transform, and generates a reference CTU. The frame memory 223 stores the reference CTU.

[0054] The inter-frame prediction circuit 221 calculates difference between a value predicted from the already transmitted CTU and an actual CTU value which corresponds to a pixel in the same area as that of the CTU, between frames. The intra-frame prediction circuit 222 has a function of calculating difference between a value predicted from the adjacent CTU and a value of a CTU actually input in one frame.

[0055]

«Decoder»

A decoder 203 illustrated in FIG. 6 can perform image decompression in accordance with H.265/HEVC.

[0056]

The decoder 203 includes a header decoding circuit 230, an entropy decoding circuit 231, an inverse quantization circuit 232, an IDCT circuit 233, an adder circuit 234, a loop filter 235, an inter-frame prediction circuit 241, an intra-frame prediction circuit 242, and a frame memory 243.

[0057]

A signal processing circuit 229 converts analog signals (an I signal and a Q signal) output from a demodulator to a digital signal and corrects an error.

[0058]

The header decoding circuit 230 decodes a header of output data of the signal processing circuit 229 and extracts image data from the output data on the basis of the header. The entropy decoding circuit 231 performs entropy decoding on the image data. The inverse quantization circuit 232 performs inverse quantization processing on the image data subjected to the entropy decoding. The IDCT circuit 233 performs inverse discrete cosine transform on the image data subjected to the inverse quantization processing. The adder circuit 234 combines information on difference calculated in the inter-frame prediction circuit 241 or information on difference calculated in the intra-frame prediction circuit 242 with the image data subjected to the inverse discrete cosine transform.

[0059]

The image data combined in the adder circuit 234 is subjected to noise removal by the loop filter 235, output from the decoder 203, and stored in the frame memory 243. On the basis of the image data stored in the frame memory 243, the inter-frame prediction circuit 241 and the intra-frame prediction circuit 242 each obtain difference information.

[0060]

DCT and IDCT are performed in part of an algorithm of image compression, and IDCT is performed in part of an algorithm of image decompression. DCT and IDCT simply show an inverse relationship between data to be converted and converted data, and can be achieved by equivalent operations.

[0061]

For example, a two-dimensional discrete cosine transform (2D-DCT) is calculated by Formula ( ). In Formula ( I), C, X, and Z are each a square matrix. In general, the number of elements in the rows and columns of the matrix C is a power of 2. The same applies to the matrices X and Z. The matrix X is a matrix whose elements are image data to be processed. The matrix C is a DCT matrix whose elements are coefficients. The matrix Z is a DCT coefficient matrix whose elements are coefficients obtained by DCT. For example, in the case of 2D-DCT (4 x 4), Formula ( I) is expressed by Formula (J2). In Formula (J2), a, b, and c are each a positive real number. In the standard "MPEG-H HEVC", 2D-DCT is performed on blocks with different sizes (4 x 4, 8 x 8, 16 x 16, and 32 x 32) in part of a data compression algorithm.

[0062]

[Formula 1]

Z - CXC ^T (/l)

? ₌

[0063]

A matrix operation of Formula (J2) can be represented by a product-sum operation. That is, the IDCT circuit of the decoder includes a product-sum operation circuit. For example, by combining a multiplication operation portion that performs multiplication with an accumulation operation portion that accumulates outputs of the multiplication operation portion, a product-sum operation circuit can be obtained. The multiplier circuit included in the multiplication operation portion is described below.

[0064]

«Multiplier circuit 300»

A multiplier circuit 300 illustrated in FIG. 7A includes a multiplier circuit 310, a digital-analog converter (DAC) 31 1, and a current generator 321.

[0065]

The multiplier circuit 310 multiplies a current IX input to a terminal PI by a current IY input to a terminal P2 to output a current IXY (= IX x IY) from a terminal P3. The current IY may be a source current or a sink current. For example, the current IY corresponding to a source current may have a positive value, and the current IY corresponding to a sink current may have a negative value. The same applies to the current IX.

[0066]

The current IX is data to be processed and an element in the matrix X in Formula (J2). The current IY is a DCT coefficient and an element in the matrix C in Formula (f∑).

[0067]

In the example in FIG. 7 A, a current-mode multiplier circuit is used for an arithmetic circuit of the multiplier circuit 300; in the case where a voltage is input to the terminal PI, a multiplier circuit having a function of multiplying an input voltage (VX) by an input current (IY) may be used for the arithmetic circuit.

[0068]

The DAC 31 1 converts N-bit digital data (N is an integer greater than or equal to 1) to an analog current. Here, the DAC 31 1 analog-converts data DIN[N-1 :0] and generates a current IREF 1. The current IREF 1 is a reference current used by the current generator 321. The current generator 321 generates the current IY corresponding to the current IREF1. Thus, whether the current IY is a sink current or a source current and the value of the current IY are determined by the data DIN[N-1 :0].

[0069]

The signal CME1 is a control signal of the DAC 31 1. In the examples of FIGS. 7A and 7B, when the signal CME1 is at "H" (high level), the DAC 31 1 is activated and generates the current IREF 1. When the signal CME1 is at "L" (low level), the DAC 31 1 is inactivated and stops generation of the current IREF 1.

[0070]

<Current generator 321>

FIG. 7B illustrates a circuit configuration example of the current generator 321. The current generator 321 includes a terminal INI 1, a terminal OUT1 1, nodes Nl and N2, an analog switch 25, transistors MO l, M02, MP1, MP2, MP4, and MN3, and capacitors C I and C2. The current IREF 1 is input from the DAC 31 1 to the terminal IN1 1. The current IY generated by the current generator 321 is output from the terminal OUT1 1. Signals CME1, OE, OEB, CMP1, and CMN1 are input to the current generator 321 as command signals.

[0071]

The current generator 321 is electrically connected to a power supply line supplied with a voltage VDD (hereinafter referred to as a VDD line), a power supply line supplied with a voltage VSS (hereinafter referred to as a VSS line), and a power supply line supplied with a voltage VBG (hereinafter referred to as a VBG line). The voltages VDD and VSS are a high power supply voltage and a low power supply voltage, respectively, of the current generator 321.

[0072]

A current mirror circuit 20 is composed of the transistors MP1 and MP2. The node Nl is an input node of the current mirror circuit 20 and is electrically connected to the terminal INI 1. The node N2 is an output node of the current mirror circuit 20.

[0073]

In the current mirror circuit 20, the transistor MP1 is a monitor transistor (also referred to as a reference transistor), and the transistor MP2 is an output transistor (also referred to as a copier transistor). The voltage VDD is input to sources of the transistors MP1 and MP2. A drain of the transistor MP1 is the node Nl . A drain of the transistor MP2, which is the node N2, is electrically connected to a drain of the transistor MN3 and is also electrically connected to the terminal OUT 11 via the analog switch 25. The on/off state of the analog switch 25 is controlled by the signals OE and OEB. The signals OE and OEB are output enable signals, and the signal OEB is an inverted signal of the signal OE.

[0074]

In the example in FIG. 7B, the current mirror circuit 20 is formed using a p-channel transistor; thus, the current IREF1 is a sink current. The current IREF1 flows through the node Nl, so that a current which copies the current IREF1 flows to the node N2.

[0075]

The transistor MOl and the capacitor CI form a memory circuit 21. The memory circuit 21 is a circuit for storing a gate voltage of the transistor MP2. A gate of the transistor MOl is supplied with the signal CMP1, and a back gate thereof is electrically connected to the VBG line.

[0076]

The transistor M02 and the capacitor C2 form a memory circuit 22. The memory circuit 22 is a circuit for storing a gate voltage of the transistor MN3. A gate of the transistor M02 is supplied with the signal CMNl, and a back gate thereof is electrically connected to the VBG line.

[0077]

The transistors MOl and M02 are OS transistors with an extremely low off-state current. Thus, the memory circuit 21 can retain a gate voltage of the transistor MP2 for a long period, and the memory circuit 22 can retain a gate voltage of the transistor MN3 for a long time. Furthermore, the threshold voltages of the transistors MOl and M02 are controlled by the voltage VBG, which leads to improvement in retention characteristics of the memory circuits 21 and 22. [0078]

In the example in FIG. 7B, a fixed voltage is input to the back gates of the transistors MOl and M02, and the fixed voltages input to the back gates of the transistors MOl and M02 may be different. Alternatively, voltages input to the back gates of the transistors MOl and M02 may change depending on the state of the memory circuit 21. Further alternatively, the transistor MOl may be an OS transistor with no back gate. The same applies to the transistor M02.

[0079]

The current mirror circuit 20 and the transistor MN3 are basic elements of the current generator 321. Since the current mirror circuit 20 is formed using a p-channel transistor, the current mirror circuit 20 functions as a current source circuit (source current source), and the current generator 321 can generate both a source current and a sink current. An operation example of the current generator 321 is described below with reference to FIGS. 8A to 8E.

[0080]

«Example of operation method of current generator 321»

An example of an operation method of the current generator 321 is described. The current generator 321 has at least the following three operation modes.

[Al]: A mode of storing data on a current IS _NKI which flows through the transistor MN3 when a current IA _I is input to the terminal INI 1.

[A2]: A mode of storing data on a current I _SRC1 which flows through the transistor MP2 when a current IA ₂ is input to the terminal INI 1.

[A3]: A mode of outputting the current IY from the terminal OUT11.

[0081]

The mode Al can be referred to as a current storage mode. By being executed in the mode Al, the current generator 321 is configured such that the current IS _NKI flows through the transistor MP2; therefore, the mode Al can also be referred to as a configuration mode. In the mode Al, configuration data of the current generator 321 is stored in the memory circuit 22.

[0082]

The mode A2 can also be referred to as a current storage mode or a configuration mode. The mode A2 is a mode for configuring the current generator 321 such that the current IS _R C _I flows through the transistor MP2. In the mode A2, configuration data of the current generator 321 is stored in the memory circuit 21.

[0083]

The mode A3 is an output mode. The current IY depends on the configuration data stored in the memory circuits 21 and 22. In other words, the configuration data determines the current value of the current IY and whether the current IY is a sink current or a source current.

[0084]

FIGS. 8A to 8E are circuit diagrams illustrating an operation example of the current generator 321. For easy understanding, the analog switch 25 and the transistors MP4, MOl, and M02 are shown by circuit symbols of a switch in FIGS. 8A to 8E.

[0085]

(Mode Al)

FIGS. 8A and 8B illustrate the mode Al . IA _I and ISN _KI each denote a current. IA _I is an input current of the current generator 321 and a reference current of the current mirror circuit 20. IS _NKI is an output current of the current mirror circuit 20.

[0086]

First, the signal OE at "L" and the signals OEB, CME1, CMP1, and CMN1 at "FT are input. The analog switch 25 and the transistor MP4 are off, and the transistors MOl and M02 are on. Next, IA _I is input to the terminal INI 1 as the current IREF1 (FIG. 8A).

[0087]

When IA _I flows between the source and the drain of the transistor MP1, the gate voltage of the transistor MP1 becomes V _P A _I , and the gate voltage of the transistor MP2 also becomes VpAi- ISN _KI which corresponds to the gate-source voltage (V _P A _I - VDD) of the transistor MP2 flows between the source and the drain thereof. The current value of IS _NKI is proportional to that of IA _I , where the proportionality coefficient depends on the element size (the channel length and the channel width) of each of the transistors MPl and MP2. Specifically, IS _NKI and IA _I have the following relation:

ISN _KI = (βρ2 βρι)ΐΑΐ, where βρι denotes the channel width of the transistor MPl/the channel length of the transistor MPl, and βρ ₂ denotes the channel width of the transistor MP2/the channel length of the transistor MP2.

[0088]

The drain-source current (hereinafter drain current) of the transistor MN3 is equal to the drain current of the transistor MP2, that is, IS _NKI - The gate voltage of the transistor MN3 supplied with ISNKI is VQN3- [0089]

Next, the signal CMN1 is set at "L" to turn off the transistor M02. Consequently, the gate of the transistor MN3 is brought into an electrically floating state, so that the gate voltage V _GN3 of the transistor MN3 is held by the capacitor C2 (FIG. 8B).

[0090]

(Mode A2) FIGS. 8C and 8D illustrate the mode A2. The mode A2 follows the mode Al . IA ₂ is input to the terminal INI 1 as IREF1 (FIG. 8C).

[0091]

When IA2 is input, the gate voltage of each of the transistors MP1 and MP2 becomes V _P A2, and the current mirror circuit 20 outputs IS _R C _I - IS _R C _I and IA ₂ have the following relation:

IsRCl = (βρ2 βρΐ)ΐΑ2·

[0092]

Next, the transistor MOl is turned off by the signal CMP1 at "L" so that the gate voltage of the transistor MP2 is retained. The gate of the transistor MP2 is brought into an electrically floating state, so that the gate voltage V _P A2 of the transistor MP2 is held by the capacitor CI (FIG. 8D).

[0093]

(Mode A3)

FIG. 8E illustrates the mode A3. When the current IY is output from the terminal OUT11, input of the current IREF1 to the terminal INI 1 is stopped. To achieve this, the signal CME1 at "L" is input to the DAC 311 to stop generation of the current IREF 1. Since the signal CME1 is at "L", the transistor MP4 is turned on, so that the voltage of the node Nl is fixed at VDD.

[0094]

When the DAC 311 is inactive, the voltage of the node Nl is unstable. The transistor

MP4 is provided to fix the voltage of the node Nl when the DAC 311 is inactive. The transistor MP4 may be provided as needed. For example, the transistor MP4 is not necessarily provided if the DAC 311 has a circuit configuration in which the voltage of the output terminal in an inactive state can be fixed.

[0095]

The signal OE and the signal OEB are set at "H" and "L", respectively, to turn on the analog switch 25. Thus, the current IY is output from the terminal OUT11. Since the gate voltage of the transistor MN3 is VG _N 3, IS _NKI flows between the source and the drain of the transistor MN3. Since the gate voltage of the transistor MP2 is V _P A2, IS _R C _I flows between the source and the drain of the transistor MP2. Thus, the current IY equals to IS _R C _I - IS _NKI - The current IY is a source current when IS _R C _I is higher than IS _NKI and is a sink current when IS _R C _I is lower than ISN _KI - [0096]

By setting the value of the input current (IA _I ) of the current generator 321 in the mode Al and the value of the input current (IA ₂ ) of the current generator 321 in the mode A2, the value of the current IY can be set and whether the current IY is a sink current or a source current can be selected. As described above, the current generator 321 is a programmable circuit configured to operate in the modes Al and A2 to output a desired current.

[0097]

Even when the DAC 311 is in a stopping state, the current generator 321 can output the current IY. That is, the power consumption of the multiplier circuit 300 in operation can be reduced. Moreover, the current generator 321 can retain the gate voltages of the transistors MP2 and MN3 for a long time without being supplied with the voltage VDD or the voltage VSS. Therefore, the voltage VDD may be supplied to the current generator 321 only when the current IY needs to be output. Accordingly, the supply of the voltage VDD or the supply of the voltage VDD and the voltage VSS can be stopped by power gating of the current generator 321 when the DAC 311 is inactive. In this manner, the standby power of the current generator 321 can be effectively reduced.

[0098]

«Operation example of multiplier circuit 300»

An operation example of the multiplier circuit 300 is described with reference to FIG. 9. In FIG. 9, Tl and the like each denote a period, and VDD represents a change in voltage of the VDD line connected to the current generator 321. Here, an example of power gating of the current generator 321 is shown. A power gating period is denoted by T6. To perform power gating, for example, a power switch which controls the voltage supply to the VDD line may be provided. In a period in which the signal OE is at "L", the terminal OUT 11 has a high impedance (Hi-Z).

[0099]

(Tl : Mode Al)

The operation mode of the current generator 321 in Tl is the mode Al . By being executed in the mode Al, the current generator 321 stores the value of IS _NKI - Specifically, the gate voltage VG _N3 of the transistor MN3 at the time when the current mirror circuit 20 outputs ISN _KI is stored in the memory circuit 22.

[0100]

First, the current generator 321 is configured to be able to output IS _NKI - The signals

CMP1 and CMN1 are set at "H" to turn on the transistors M02 and MOl . Furthermore, the signal CMEl is set at "H" to activate the DAC 311. Data DAI for setting the value of IS _NKI is input to the DAC 311. The DAC 311 outputs IA _I having a value corresponding to that of the data DAI to the current generator 321. The current mirror circuit 20 outputs IS _NKI which is proportional to IA _I . [0101]

The data DAI is input to the DAC 311 for a predetermined period of time. Before the input of the data DAI is stopped, the signal CMN1 is set at "L" to turn off the transistor M02. Consequently, the memory circuit 22 is set in a non-selected state to retain the gate voltage V G _N3 of the transistor MN3.

[0102]

(T2: Mode A2)

After the mode Al, the mode A2 is executed, in which the value of IS _R C _I is stored in the current generator 321. Specifically, the gate voltage V _P A ₂ of the transistor MP2 at the time when the current mirror circuit 20 outputs IS _R C _I is stored in the memory circuit 31.

[0103]

Data DA2 is input to the DAC 311. The DAC 311 outputs IA ₂ having a value corresponding to that of the data DA2. The current mirror circuit 20 outputs IS _R C _I which is proportional to ΙΑ ₂ · The data DA2 is input to the DAC 311 for a predetermined period of time. Before the input of the data DA2 is stopped, the signal CMP1 is set at the L level to turn off the transistor MOl . Consequently, the memory circuit 21 is set in a non-selected state to retain the gate voltage V _P A ₂ of the transistor MP2.

[0104]

The input of the data DA2 is stopped, and the signal CME1 is set at "L". The DAC 311 becomes inactive. The transistor MP4 is turned on, so that the voltage of the node Nl is fixed to the voltage VDD.

[0105]

(T3 : Standby Mode)

The operation mode of the current generator 321 in T3 is a standby mode. In T3, a command signal can be received. The current generator 321 is in the standby state. In the memory circuit 21, the gate voltage V _P A ₂ is held by the capacitor CI . In the memory circuit 22, the gate voltage VG _N3 is held by the capacitor C2.

[0106]

The operation modes in T5 and T7 are also the standby mode, in which the memory circuit 21 and the memory circuit 22 retain the gate voltage V _P A ₂ and the gate voltage VG _N3 , respectively.

[0107]

(T4: Mode A3 (output mode))

The operation mode of the current generator 321 in T4 is an output mode (the mode A3), in which IOUT is output. The signal OE is set at the H level to turn on the analog switch 25. When Is _R ci is higher than IS _NKI , the current generator 321 outputs a source current (+Ia) from the terminal OUT11. When I _SRC1 is lower than IS _NKI , the current generator 321 outputs a sink current (-la) from the terminal OUT11. The following equations are satisfied: +Ia = + | IS _R C _I -

ISNKI I and -la = - | ISRCI - ISNKI I _·

[0108]

Since the current generator 321 can output the current IY even when a reference current is not input to the current generator 321, the power consumption of the current generator 321 in operation can be suppressed.

[0109]

(T5: Standby mode)

By setting the signal OE at "L" to turn off the analog switch 25, the current generator 321 returns to the standby state.

[0110]

(T6: Power gating)

Power gating of the current generator 321 is performed in T6. The power switch is turned off to stop the supply of the voltage VDD to the VDD line. The voltage of the VDD line decreases; therefore, neither IS _R C _I nor IS _NKI flows in the current generator 321. The power gating of the current generator 321 can reduce the standby power of the current generator 321 of the multiplier circuit 300. The supply of a power supply voltage to the DAC 311 may also be stopped in T6. Thus, the standby power of the multiplier circuit 300 can be reduced more effectively.

[0111]

(T7: Resumption of power supply and standby mode)

By turning on the power switch, the VDD line is charged to resume the voltage VDD. The current mirror circuit 20 is supplied with the voltage VDD, so that the current generator 321 is brought into the standby state.

[0112]

(T8: Mode A3 (output mode))

By setting the signal OE at "H" to turn on the analog switch 25, the current generator 321 resumes the output of the source current (+Ia) or the sink current (-la) from the terminal OUT11.

[0113]

The transistors MOl and M02, each of which is an OS transistor, can suppress the leakage of charge from the capacitors CI and C2. Accordingly, the current IY which maintains the value in T4 can be output from the terminal OUT 11 again without rewriting data in the memory circuits 21 and 22. In other words, the modes Al and A2 may be executed again only when the current IY needs to be changed. Thus, the power consumption of the multiplier circuit 300 can be reduced.

[0114]

In the current generator 321, a PMOS current mirror circuit is provided. Thus, a switch circuit for selecting a current mirror circuit to which a reference current is input or a switch circuit for selecting a current mirror circuit which outputs a current is unnecessary, so that the number of elements in the multiplier circuit 300 and the number of wirings can be reduced. Consequently, the size and power consumption of the multiplier circuit 300 can be reduced. As described in Embodiment 2, the size of the multiplier circuit 300 can be further reduced by stacking the memory circuits 21 and 22 over a region in which the current mirror circuit 20 and the transistors MN3 and MP4 are formed.

[0115]

By using the multiplier circuit 300 for the IDCT circuit 233, the area of the decoder 203 can be reduced. This is because the IDCT circuit 233 can perform an operation using the analog current (IY) generated by the current generator 321 and thus have a small circuit size, whereas a general IDCT circuit is formed using only a digital circuit.

[0116]

Similarly, by using the multiplier circuit 300 for the DCT circuit 212 and/or the IDCT circuit 217, the area of the encoder 201 can be reduced.

[0117]

Since the current generator 321 is a programmable circuit, the multiplier circuit 300 can inactivate a circuit which is unnecessary for the operation; thus, the power consumption of the multiplier circuit 300 can be reduced. As a result, the current consumption of the encoder 201 and the decoder 203 can be reduced. Furthermore, power gating of the current generator 321 can be performed, so that the standby power of the encoder 201 and the decoder 203 can be reduced.

[0118]

Next, another configuration example of the multiplier circuit is described. The multiplier circuit and the multiplier circuit 300 can have similar functions and similar effects.

[0119]

«Multiplier circuit 301»

A multiplier circuit 301 illustrated in FIG. 10 is a modification example of the multiplier circuit 300 and includes a current generator 322 instead of the current generator 321. The multiplier circuit 301 can operate in accordance with a timing chart in FIG. 9. [0120]

The current generator 322 is a modification example of the current generator 321. The current generator 321 is different from the current generator 322 in the circuit configuration of the memory circuit for storing the gate voltage of the transistor MP2. A memory circuit 23 in FIG. 10 is a memory circuit corresponding to the memory circuit 21 in FIG. 7B.

[0121]

The memory circuit 23 includes a transistor M03 and a capacitor C3. A first terminal of the capacitor C3 is electrically connected to gates of the transistors MP1 and MP2, and a second terminal of the capacitor C3 is electrically connected to the VDD line. The transistor M03 is a path transistor which controls the electrical connection between the gate and a drain of the transistor MP1. When the transistor M03 is on, the transistor MP1 is diode-connected and the current mirror circuit 20 is activated. The on/off of the transistor M03 is controlled by the signal CMP1. The transistor M03 is an OS transistor having a back gate, which is electrically connected to the VBG line.

[0122]

«Multiplier circuit 302»

A multiplier circuit 302 illustrated in FIG. 11 includes the multiplier circuit 310, a DAC 312, and a current generator 323.

[0123]

The DAC 312, like the DAC 311, is a circuit that converts N-bit digital data to an analog current. Here, the DAC 312 analog-converts data DIN[N-1 :0] and generates a current IREF2. The current IREF2 is a reference current used by the current generator 322. The current IREF2 is a source current which flows from an output of the DAC 312.

[0124]

The signal CME2 is a command signal of the DAC 312. The signal CME2 determines whether to activate or inactivate the DAC 312.

[0125]

The current generator 323 is a modification example of the current generator 321, and includes transistors having conductivity types opposite to those of the transistors MP1, MP2, MP4, and MN3 in the current generator 321. The current generator 323 includes transistors MNl, MN2, MN4, MP3, M04, and M05, capacitors C4 and C5, and an analog switch 35. The current generator 323 is electrically connected to the VDD line and the VSS line. Signals CMEB2, CMN2, CMP2, OE, and OEB are input to the current generator 323.

[0126]

The transistors MNl and MN2 form a current mirror circuit 30. The transistor MNl is a monitor transistor, and the transistor MN2 is an output transistor. VSS is input to sources of the transistors MN1 and MN2. A node N4 and a node N5 are an input node and an output node, respectively, of the current mirror circuit 30. Since the current mirror circuit 30 is formed using an n-channel transistor, the current IREF2 (reference current) input to the node N4 is a source current.

[0127]

The transistor M04 and the capacitor C4 form the memory circuit 31. The memory circuit 31 is a circuit for storing a gate voltage of the transistor MN2. A gate of the transistor M04 is supplied with the signal CMN2, and a back gate thereof is electrically connected to the VBG line.

[0128]

The transistor MO 5 and the capacitor C5 form a memory circuit 32. The memory circuit 32 is a circuit for storing a gate voltage of the transistor MP3. A gate of the transistor M05 is supplied with the signal CMP2, and a back gate thereof is electrically connected to the VBG line.

[0129]

Like the transistor MOl, the transistors M04 and M05 are OS transistors.

[0130]

The transistor MN4 is provided to fix the voltage of the node N4 when the DAC 312 is inactive. The transistor MN4 may be provided as needed. The signal CMEB2 is an inverted signal of the signal CME2 and controls the on/off of the transistor MN4. Here, when the signal CME2 is at "L", the DAC 312 is inactivated and the transistor MN4 is turned on. Note that the signal CMEB2 can also be generated inside the current generator 323. For example, an inverter circuit to which the signal CME2 is input may be provided in the current generator 323, and an output of the inverter circuit may be input to a gate of the transistor MN4.

[0131]

The signals OE and OEB control the on/off of the analog switch 35. When the signal OE is at "H" and the signal OEB is at "L", the current generator 323 outputs the current IY; whether the current IY is a source current or a sink current and the value of the current IY are determined by the voltages held by the memory circuits 31 and 32.

[0132]

«Operation example of multiplier circuit 302»

An operation example of the multiplier circuit 302 is described with reference to FIG.

12.

[0133] (Tl : Mode Al)

In Tl, the current generator 323 operates in the mode Al and stores the value of a current I _S RC2- [0134]

The signals CMN2 and CMP2 are set at "H" to turn on the transistors M04 and M05.

The signal CME2 is set at "H" to activate the DAC 312. Data DB 1 for setting the value of the current IS _R C ₂ is input to the DAC 312. The DAC 312 outputs the current IREF2 having a value corresponding to that of the data DB1. Here, the current IREF2 in Tl is denoted by the current I _BI . The current mirror circuit 30 outputs the current IS _R C ₂ which is proportional to the current IBI.

[0135]

The data DB1 is input to the DAC 312 for a predetermined period of time. Before the input of the data DB 1 is stopped, the signal CMP2 is set at "L" to turn off the transistor M05. Consequently, the memory circuit 32 is set in a non-selected state, and the gate voltage V Q _P3 of the transistor MP3 when the current mirror circuit 30 outputs the current IS _R C ₂ is held by the capacitor C5.

[0136]

(T2: Mode A2)

Next, the mode A2 is executed, in which the value of the current IS _NK2 is stored in the current generator 323.

[0137]

Data DB2 is input to the DAC 312. The DAC 312 outputs the current IREF2 having a value corresponding to that of the data DB2. Here, the current IREF2 in T2 is denoted by the current I _B2 . The current mirror circuit 30 outputs the current IS _NK2 which is proportional to the current I _B2 . The data DB2 is input to the DAC 312 for a predetermined period of time. Before the input of the data DB2 is stopped, the signal CMN2 is set at "L" to turn off the transistor M04. Consequently, the memory circuit 31 is set in a non-selected state to retain the gate voltage V _N A ₂ of the transistor MN2 when the current mirror circuit 30 outputs the current IS _NK2 - [0138]

The input of the data DB2 is stopped and the signal CME2 is set at "L", so that the DAC

312 becomes inactive. The transistor MN4 is turned on, so that the voltage of the node N4 is fixed to the voltage VSS.

[0139]

(T3 : Standby mode)

The current generator 323 is in the standby state in T3. In the memory circuit 31, the gate voltage V _N A ₂ is held by the capacitor C4. In the memory circuit 32, the gate voltage VQ _P3 is held by the capacitor C5.

[0140]

(T4: Mode A3 (output mode))

In T4, the current generator 323 outputs the current IY. The signal OE is set at "H" to turn on the analog switch 35. When IS _R C ₂ is higher than IS _NK2 , the current IY is a source current (+Ib). When IS _R C ₂ is lower than IS _NK2 , the current IY is a sink current (-lb). The following equations are satisfied: +Ib = + 1 ISRC2 - ISNK2 I and -lb = - | ISRC2 - ISNK2 I · Since the current generator 323 can output the current IY even when the current IREF2 is not input to the current mirror circuit 30, the power consumption of the current generator 323 can be suppressed.

[0141]

(T5-T8)

The operation of the multiplier circuit 302 in T5 to T8 is similar to the operation of the multiplier circuit 300 in T5 to T8; therefore, refer to its description.

[0142]

«Multiplier circuit 303»

A multiplier circuit 303 illustrated in FIG. 13 is a modification example of the multiplier circuit 302 and includes a current generator 324 instead of the current generator 323. The multiplier circuit 303 can operate in accordance with a timing chart in FIG. 12.

[0143]

The current generator 323 is different from the current generator 324 in the circuit configuration of the memory circuit for storing the gate voltage of the transistor MN2.

[0144]

The memory circuit 33 includes a transistor M06 and a capacitor C6. A first terminal of the capacitor C6 is electrically connected to gates of the transistors MN1 and MN2, and a second terminal of the capacitor C6 is electrically connected to the VSS line. The on/off of the transistor M06 is controlled by the signal CMN2. The transistor M06 is an OS transistor having a back gate, which is electrically connected to the VBG line. The transistor M06 is a path transistor which controls the electrical connection between the gate and a drain of the transistor MNl . The transistor MNl is diode-connected when the transistor M06 is on and the current mirror circuit 30 is activated.

[0145]

«Multiplier circuit 304»

A multiplier circuit 304 illustrated in FIG. 14 is a modification example of the multiplier circuit 300 and includes a current generator 325 instead of the current generator 321. The multiplier circuit 304 can operate in accordance with the timing chart in FIG. 9.

[0146]

The current generator 325 includes three memory circuits 21, three memory circuits 22, three current mirror circuits 20 which are cathcode-connected, three transistors MN3 which are cathcode-connected, and the analog switch 25.

[0147]

In the case where the transistors MP1, MP2, and MN3 do not have favorable saturation characteristics, it is preferable that a plurality of current mirror circuits 20 be cathcode-connected and a plurality of transistors MN3 be cathcode-connected as in the current generator 325 illustrated in FIG. 14.

[0148]

The circuit configuration of the current generator 322 in the multiplier circuit 301 can be modified to be that of the current generator 325.

[0149]

«Multiplier circuit 305»

A multiplier circuit 305 illustrated in FIG. 15 is a modification example of the multiplier circuit 303 and includes a current generator 326 instead of the current generator 324. The multiplier circuit 305 can operate in accordance with the timing chart in FIG. 12.

[0150]

The current generator 326 includes three memory circuits 32, three memory circuits 33, three current mirror circuits 30 which are cathcode-connected, three transistors MP3 which are cathcode-connected, and the analog switch 35.

[0151]

In the case where the transistors MN1, MN2, and MP3 do not have favorable saturation characteristics, it is preferable that a plurality of current mirror circuits 30 be cathcode-connected and a plurality of transistors MP3 be cathcode-connected as in the current generator 326 illustrated in FIG. 15.

[0152]

The circuit configuration of the current generator 323 in the multiplier circuit 302 can be modified to be that of the current generator 326.

[0153]

(Embodiment 2)

In this embodiment, a semiconductor device including a Si transistor and an OS transistor is described. The structure of such a semiconductor device is described here using the multiplier circuit 300 described in Embodiment 1 as an example. [0154]

«Stacked structure of multiplier circuit 300»

The structure of the multiplier circuit 300 is described with reference to FIG. 16. FIG. 16 shows the transistor MN3 and the memory circuit 22 (the transistor M02 and the capacitor C2) as a typical example. The multiplier circuit 300 includes a single crystal silicon wafer 5500 and a stack of layers LX1 to LX11. The layers LX1 to LX11 include wirings, electrodes, plugs, and the like. Note that FIG. 16 is a cross-sectional view illustrating an example of a stacked structure of the multiplier circuit 300, and not a cross-sectional view of the multiplier circuit 300 taken along a specific line.

[0155]

In the layer LX1, a Si transistor included in the multiplier circuit 300, such as the transistor MN3, is provided. A channel formation region of the Si transistor is provided in the single crystal silicon wafer 5500.

[0156]

The layer LX8 includes an OS transistor such as the transistor M02. A back gate electrode of the OS transistor is provided in the layer LX7. The OS transistor here has a structure similar to an OS transistor 5004 to be described later (see FIG. 20). The layer LX9 includes the capacitor C2. The capacitor C2 can be provided below the layer LX7.

[0157]

Next, structure examples of the OS transistor are described with reference to FIG. 17 to

FIG. 20.

[0158]

«Structure example 1 of OS transistor»

FIG. 17 illustrates a structure example of an OS transistor. A cross-sectional view of an OS transistor 5001 in a channel length direction is illustrated on the left drawing of FIG. 17, and a cross-sectional view of the OS transistor 5001 in a channel width direction is illustrated on the right drawing of FIG. 17.

[0159]

The OS transistor 5001 is formed over an insulating surface, here, over an insulating layer 5021. The OS transistor 5001 is covered with insulating layers 5028 and 5029. The OS transistor 5001 includes insulating layers 5022 to 5027 and 5030 to 5032, metal oxide layers 5011 to 5013, and conductive layers 5050 to 5054.

[0160]

Note that an insulating layer, a metal oxide layer, a conductor, and the like in a drawing may have a single-layer structure or a stacked structure. These elements can be formed by any of a variety of deposition methods such as sputtering, molecular beam epitaxy (MBE), pulsed laser ablation (PLA), chemical vapor deposition (CVD), and atomic layer deposition (ALD). Examples of CVD include plasma-enhanced CVD, thermal CVD, and metal organic CVD.

[0161]

The metal oxide layers 5011 to 5013 are collectively referred to as an oxide layer 5010.

As illustrated in FIG. 17, the oxide layer 5010 includes a portion where the metal oxide layer 5011, the metal oxide layer 5012, and the metal oxide layer 5013 are stacked in that order. When the OS transistor 5001 is on, a channel is mainly formed in the metal oxide layer 5012 of the oxide layer 5010.

[0162]

A gate electrode of the OS transistor 5001 is formed using the conductive layer 5050. A pair of electrodes that functions as a source electrode and a drain electrode of the OS transistor 5001 is formed using the conductive layers 5051 and 5052. The conductive layers 5050 to 5052 are covered with the insulating layers 5030 to 5032 that function as barrier layers. A back gate electrode of the OS transistor 5001 is formed using a stack of the conductive layers 5053 and 5054. The OS transistor 5001 does not necessarily include a back gate electrode. The same applies to an OS transistor 5002 to be described later.

[0163]

A gate insulating layer on a gate (front gate) side is formed using the insulating layer 5027. A gate insulating layer on a back gate side is formed using a stack of the insulating layers 5024 to 5026. The insulating layer 5028 is an interlayer insulating layer. The insulating layer 5029 is a barrier layer.

[0164]

The metal oxide layer 5013 covers a stack of the metal oxide layers 5011 and 5012 and the conductive layers 5051 and 5052. The insulating layer 5027 covers the metal oxide layer 5013. The conductive layers 5051 and 5052 each include a region that overlaps with the conductive layer 5050 with the metal oxide layer 5013 and the insulating layer 5027 positioned therebetween.

[0165]

Examples of a conductive material used for the conductive layers 5050 to 5054 include a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus; silicide such as nickel silicide; a metal such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium; and a metal nitride containing the above metal as its component (tantalum nitride, titanium nitride, molybdenum nitride, or tungsten nitride). A conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

[0166]

For example, the conductive layer 5050 is a single layer of tantalum nitride or tungsten.

Alternatively, in the case where the conductive layer 5050 has a two-layer structure or a three-layer structure, the following combinations can be used: aluminum and titanium; titanium nitride and titanium; titanium nitride and tungsten; tantalum nitride and tungsten; tungsten nitride and tungsten; titanium, aluminum, and titanium; titanium nitride, aluminum, and titanium; and titanium nitride, aluminum, and titanium nitride. The conductor described first is provided on the insulating layer 5027 side.

[0167]

The conductive layers 5051 and 5052 have the same layer structure. For example, in the case where the conductive layer 5051 is a single layer, any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or an alloy containing any of these metals as its main component may be used. Alternatively, in the case where the conductive layer 5051 has a two-layer structure or a three-layer structure, the following combinations can be used: titanium and aluminum; tungsten and aluminum; tungsten and copper; a copper-magnesium-aluminum alloy and copper; titanium and copper; titanium or titanium nitride, aluminum or copper, and titanium or titanium nitride; and molybdenum or molybdenum nitride, aluminum or copper, and molybdenum or molybdenum nitride. The conductor described first is provided on the insulating layer 5027 side.

[0168]

For example, it is preferable that the conductive layer 5053 be a conductive layer that has a hydrogen barrier property (e.g., a tantalum nitride layer) and that the conductive layer 5054 be a conductive layer that has higher conductivity than the conductive layer 5053 (e.g., tungsten). With such a structure, a stack of the conductive layer 5053 and the conductive layer 5054 functions as a wiring and has a function of suppressing diffusion of hydrogen into the oxide layer 5010.

[0169]

Examples of insulating materials used for the insulating layers 5021 to 5032 include aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and aluminum silicate. The insulating layers 5021 to 5030 are formed using a single-layer structure or a stacked structure of these insulating materials. The layers used for the insulating layers 5021 to 5030 may include a plurality of insulating materials.

[0170]

Note that in this specification and the like, an oxynitride refers to a substance that contains more oxygen than nitrogen, and a nitride oxide refers to a substance that contains more nitrogen than oxygen.

[0171]

In the OS transistor 5001, the oxide layer 5010 is preferably surrounded by an insulating layer with oxygen and hydrogen barrier properties (hereinafter such an insulating layer is referred to as a barrier layer). With such a structure, it is possible to suppress the release of oxygen from the oxide layer 5010 and entry of hydrogen into the oxide layer 5010; thus, the reliability and electrical characteristics of the OS transistor 5001 can be improved.

[0172]

For example, the insulating layer 5029 functions as a barrier layer and at least one of the insulating layers 5021, 5022, and 5024 functions as a barrier layer. The barrier layer can be formed using a material such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or silicon nitride. A barrier layer may be provided between the oxide layer 5010 and the conductive layer 5050. Alternatively, a metal oxide layer that has oxygen and hydrogen barrier properties may be provided as the metal oxide layer 5013.

[0173]

The insulating layer 5030 is preferably a barrier layer that prevents oxidation of the conductive layer 5050. When the insulating layer 5030 has an oxygen barrier property, oxidation of the conductive layer 5050 due to oxygen released from the insulating layer 5028 or the like can be suppressed. For example, the insulating layer 5030 can be formed using a metal oxide such as aluminum oxide.

[0174]

A structure example of the insulating layers 5021 to 5032 is described. In this example, each of the insulating layers 5021, 5022, 5025, and 5029 to 5032 functions as a barrier layer. The insulating layers 5026 to 5028 are oxide layers containing excess oxygen. The insulating layer 5021 is formed using silicon nitride. The insulating layer 5022 is formed using aluminum oxide. The insulating layer 5023 is formed using silicon oxynitride. The gate insulating layers (5024 to 5026) on the back gate side are formed using a stack of silicon oxide, aluminum oxide, and silicon oxide. The gate insulating layer (5027) on the front gate side is formed using silicon oxynitride. The interlayer insulating layer (5028) is formed using silicon oxide. The insulating layers 5029 to 5032 are formed using aluminum oxide.

[0175]

FIG. 17 illustrates an example in which the oxide layer 5010 has a three-layer structure; however, one embodiment of the present invention is not limited thereto. For example, the oxide layer 5010 can have a two-layer structure without the metal oxide layer 5011 or 5013 or may be composed of one of the metal oxide layers 5011 and 5012. Alternatively, the oxide layer 5010 may be composed of four or more metal oxide layers.

[0176]

«Structure example 2 of OS transistor»

The OS transistor 5002 in FIG. 18 is a modification example of the OS transistor 5001. A cross-sectional view of the OS transistor 5002 in a channel length direction is illustrated on the left drawing of FIG. 18, and a cross-sectional view of the OS transistor 5002 in a channel width direction is illustrated on the right drawing of FIG. 18.

[0177]

In the OS transistor 5002, top and side surfaces of a stack of the metal oxide layers 5011 and 5012 are covered with a stack of the metal oxide layer 5013 and the insulating layer 5027. Thus, the OS transistor 5002 does not necessarily include the insulating layers 5031 and 5032.

[0178]

«Structure example 3 of OS transistor»

An OS transistor 5003 in FIG. 19 is a modification example of the OS transistor 5001. The OS transistor 5003 differs from the OS transistor 5001 mainly in the structure of the gate electrode.

[0179]

The metal oxide layer 5013, the insulating layer 5027, and the conductive layer 5050 are provided in an opening portion formed in the insulating layer 5028. In other words, a gate electrode is formed in a self-aligning manner by using the opening portion of the insulating layer 5028. Thus, in the OS transistor 5002, a gate electrode (5050) does not include a region that overlaps with a source electrode or a drain electrode (5051 or 5052) with a gate insulating layer (5017) positioned therebetween. Accordingly, gate-source parasitic capacitance and gate-drain parasitic capacitance can be reduced and frequency characteristics can be improved. Furthermore, gate electrode width can be controlled by the opening portion of the insulating layer 5028; thus, it is easy to manufacture an OS transistor with short channel length.

[0180]

«Structure example 4 of OS transistor» The OS transistor 5004 in FIG. 20 is different from the OS transistor 5001 in the structures of the gate electrode and the oxide layer.

[0181]

A gate electrode (5050) of the OS transistor 5004 is covered with insulating layers 5033 and 5034.

[0182]

The OS transistor 5004 includes an oxide layer 5009 formed of the metal oxide layers 5011 and 5012. Instead of the conductive layers 5051 and 5052, low-resistance regions 5011a and 5011b are provided in the metal oxide layer 5011, and low-resistance regions 5012a and 5012b are provided in the metal oxide layer 5012. By selectively adding impurity elements (e.g., hydrogen or nitrogen) to the oxide layer 5009, the low-resistance regions 5011a, 5011b, 5012a, and 5012b can be formed.

[0183]

Adding impurity elements to the metal oxide layer causes formation of oxygen vacancies in the regions to which the impurity elements are added, and the impurity elements enter the oxygen vacancies. This increases the carrier density and thus decreases the resistance of the regions.

[0184]

A channel formation region of the OS transistor preferably includes a cloud-aligned composite metal oxide semiconductor (CAC-OS).

[0185]

The CAC-OS has a conducting function in part of a material and has an insulating function in another part of the material; as a whole, the CAC-OS functions as a semiconductor. Note that in the case where the CAC-OS or the CAC metal oxide is used in an active layer of a transistor, the conducting function is to allow electrons (or holes) serving as carriers to flow, and the insulating function is to not allow electrons serving as carriers to flow. By the complementary action of the conducting function and the insulating function, the CAC-OS can have a switching function (on/off function). In the CAC-OS, separation of the functions can maximize each function.

[0186]

The CAC-OS includes conductive regions and insulating regions. The conductive regions have the conducting function, and the insulating regions have the insulating function. In some cases, the conductive regions and the insulating regions in the material are separated at the nanoparticle level. In some cases, the conductive regions and the insulating regions are unevenly distributed in the material. The conductive regions are observed to be coupled in a cloud-like manner with their boundaries blurred in some cases.

[0187]

Furthermore, in the CAC-OS, the conductive regions and the insulating regions each have a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3 nm and are dispersed in the material in some cases.

[0188]

The CAC-OS includes components having different bandgaps. For example, the CAC-OS includes a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of such a composition, carriers mainly flow in the component having a narrow gap. The component having a narrow gap complements the component having a wide gap, and carriers also flow in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, in the case where the CAC-OS is used in a channel formation region of a transistor, high current drive capability and high field-effect mobility of the OS transistor can be obtained.

[0189]

A metal oxide semiconductor is classified into a single crystal metal oxide semiconductor and a non-single-crystal metal oxide semiconductor according to crystallinity. Examples of a non-single-crystal metal oxide semiconductor include a c-axis aligned crystalline metal oxide semiconductor (CAAC-OS), a poly crystalline metal oxide semiconductor, a nanocrystalline metal oxide semiconductor (nc-OS), and an amorphous-like metal oxide semiconductor (a-like OS).

[0190]

The channel formation region of the OS transistor preferably includes a metal oxide including a crystal part, such as a CAAC-OS or an nc-OS.

[0191]

The CAAC-OS has c-axis alignment, its nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that distortion refers to a portion where the direction of lattice arrangement changes between a region with uniform lattice arrangement and another region with uniform lattice arrangement in a region where the nanocrystals are connected.

[0192]

The shape of the nanocrystal is basically a hexagon. However, the shape is not always a regular hexagon and is a non-regular hexagon in some cases. A pentagonal lattice arrangement, a heptagonal lattice arrangement, and the like are included in the distortion in some cases. Note that a clear grain boundary cannot be observed even in the vicinity of distortion in the CAAC-OS. That is, formation of a grain boundary is inhibited due to the distortion of lattice arrangement. This is probably because the CAAC-OS can tolerate distortion owing to the low density of arrangement of oxygen atoms in the a-b plane direction, a change in interatomic bond distance by substitution of a metal element, and the like.

[0193]

The CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing an element M, zinc, and oxygen (hereinafter referred to as an (Μ,Ζη) layer) are stacked. Note that indium and the element M can be replaced with each other, and when the element M of the (Μ,Ζη) layer is replaced with indium, the layer can also be referred to as an (Ιη,Μ,Ζη) layer. When indium of the In layer is replaced with the element M, the layer can also be referred to as an (Ιη,Μ) layer.

[0194]

In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has periodic atomic arrangement. There is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

[0195]

The a-like OS has a structure between those of the nc-OS and the amorphous metal oxide semiconductor. The a-like OS has a void or a low-density region. The a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

[0196]

In this specification and the like, a CAC refers to the function or material of a metal oxide semiconductor, and a CAAC refers to the crystal structure of a metal oxide semiconductor. REFERENCE NUMERALS

[0197]

25, 35: analog switch,

20, 30: current mirror circuit,

21, 22, 23, 31, 32, 33 : memory circuit,

100: broadcast system, 110: camera, 111 : image sensor, 112: image processor, 115: transmitter, 116: encoder, 117: modulator, 120: receiver, 121 : demodulator, 122: decoder, 125: display device, 126: image processor, 127: display portion,

141, 151, 154, 156, 157: image data, 150: Raw data, 152: encoded data, 153 : broadcast signal, 155: data signal,

160: TV (television receiver), 161 : broadcast station, 162: artificial satellite,

163 : radio wave tower, 164, 165: antenna, 166A, 166B, 167A, 167B: radio wave,

171 : receiver, 172, 173 : wireless device, 174: receiver, 175: connector portion,

180: ambulance, 181, 182: medical institution, 185: high-speed network,

190: camera, 191 : encoder, 192, 195: communication device, 196: decoder, 197: display device, 201 : encoder, 203 : decoder, 210: block divider, 211 : subtractor circuit, 212: discrete cosine transform (DCT) circuit, 213 : quantization circuit, 214: entropy coding circuit, 215: header adding circuit, 216: inverse quantization circuit, 217: inverse discrete cosine transform (IDCT) circuit, 218: adder circuit, 221 : inter-frame prediction circuit, 222: intra-frame prediction circuit, 223 : frame memory, 229: signal processing circuit, 230: header decoding circuit, 231 : entropy decoding circuit, 232: inverse quantization circuit, 233 : IDCT circuit, 234: adder circuit, 235: loop filter, 241 : inter-frame prediction circuit, 242: intra-frame prediction circuit, 243 : frame memory,

300, 301, 302, 303, 304, 305, 310: multiplier circuit,

311, 312: digital-analog converter (DAC),

321, 322, 323, 324, 325, 326: current generator,

5001, 5002, 5003, 5004: OS transistor,

5009, 5010: oxide layer,

5011, 5012, 5013 : metal oxide layer,

5011a, 5011b, 5012a, 5012b: low-resistance region,

5021, 5022, 5023, 5024, 5025, 5026, 5027, 5028, 5029, 5030, 5031, 5032, 5033, 5034: insulating layer,

5050, 5051, 5052, 5053, 5054: conductive layer,

5500: single crystal silicon wafer,

CI, C2, C3, C4, C5, C6: capacitor,

MN1, MN2, MN3, MN4, MOl, M02, M03, M04, M05, M06, MP1, MP2, MP3, MP4: transistor,

N1, N2, N4, N5: node,

INI 1, OUT11, PI, P2, P3 : terminal,

CME1, CME2, CMEB2, CMN1, CMN2, CMP1, CMP2, OE, OEB: signal,

DAI, DA2, DB1, DB2, DIN[N-1 :0]: data, IA _I , IA ₂ , I _B I, IB2, IREFl, IREF2, I _SNK1 , , ISRCI, ISRC2, IX, KY, IY: current,

VBG, VDD, VSS: voltage, and

V _G N3, V _G P3, VNAI, V _N A2, VPAI, V _PA : gate voltage. This application is based on Japanese Patent Application Serial No. 2016-238959 filed with Japan Patent Office on December 9, 2016, the entire contents of which are hereby incorporated by reference.