Title:
ENCODING METHOD, DECODING METHOD, ENCODER, AND DECODER
Document Type and Number:
WIPO Patent Application WO/2012/098909
Kind Code:
A1
Abstract:
An encoding method generates a parity bit column by encoding an information sequence by means of a feed-forward LDPC convolutional code on the basis of a plurality of parity check polynomials having a code rate of (n-1)/n, then performs an interleave process and then an accumulate process. The accumulate process calculates the exclusive OR of the bit of a parity bit column after the interleave process and the bit of a parity bit column after a delayed accumulate process. Then, a code sequence configured from the information sequence and the parity bit column after the accumulate process is generated.
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Inventors:
MURAKAMI YUTAKA
Application Number:
PCT/JP2012/000354
Publication Date:
July 26, 2012
Filing Date:
January 20, 2012
Export Citation:
Assignee:
PANASONIC CORP (JP)
MURAKAMI YUTAKA
MURAKAMI YUTAKA
International Classes:
H03M13/19
Foreign References:
| JP2009246926A | 2009-10-22 | |||
| JP2009077391A | 2009-04-09 |
Other References:
YUTAKA MURAKAMI ET AL.: "LDPC Convolutional Codes Based on Parity Check Polynomial", IEICE TECHNICAL REPORT, RCS, RADIO COMMUNICATION SYSTEMS, vol. 108, no. 61, 22 May 2008 (2008-05-22), pages 75 - 79, XP008147297
STEPHEN BATES ET AL.: "Termination Sequence Generation Circuits for Low-Density Parity- Check Convolutional Codes", CIRCUITS AND SYSTEMS I: REGULAR PAPERS, IEEE TRANSACTIONS ON, vol. 53, no. ISS.9, 18 September 2006 (2006-09-18), pages 1909 - 1917, XP055010515, DOI: doi:10.1109/TCSI.2006.880313
STEPHEN BATES ET AL.: "Termination Sequence Generation Circuits for Low-Density Parity- Check Convolutional Codes", CIRCUITS AND SYSTEMS I: REGULAR PAPERS, IEEE TRANSACTIONS ON, vol. 53, no. ISS.9, 18 September 2006 (2006-09-18), pages 1909 - 1917, XP055010515, DOI: doi:10.1109/TCSI.2006.880313
Attorney, Agent or Firm:
NAKAJIMA, Shiro et al. (JP)
Shiro Nakajima (JP)
Shiro Nakajima (JP)
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