TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, endurance and switching yield improvement in RRAM (Resistive Random Access Memory) devices.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Embedded memory with non-volatile memory devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. Resistive memory, such as resistive random-access memory (RRAM or ReRAM), generally includes a two-terminal device in which a comparatively insulating switching layer or medium is positioned between two conductive electrodes. RRAM devices typically includes one transistor (IT) along with one resistor (1R), resulting in 1T-1R, where the transistor (IT) is used as an access device for reading and/or writing operations, while the resistor (1R) acts as a memristor to store the memory state. RRAM can change between two different states: a high-resistance state (HRS), which may be representative of an off or 0 state; and a low-resistance state (LRS), which may be representative of an on or 1 state. In RRAM, the transition from the HRS to the LRS is normally called“set”, while the reversed transition is named“reset”. . Filamentary RRAM requires an initial forming process whereby a high voltage stress (known as a forming voltage) is applied to the device such that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path. Interfacial RRAM does not require such an initial forming process.

A large collection of memory cells forms a key component of non-volatile embedded memory. However, with scaling of memory devices, the technical challenges of assembling a vast number of memory cells presents formidable roadblocks to commercialization of this technology today. Reliability is a primary concern for RRAM devices. Long term repeated switching, or cycling endurance measured as the number of set/reset cycles at failure, degrades over usage, particularly for RRAM having a single switching layer of a high-K dielectric.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 A illustrates a state of the art resistive random access memory (RRAM) device.

Figures 1B and 1C are diagrams illustrating an improved 1T-1R RRAM memory device in accordance with the embodiments disclosed herein.

Figure 2 is a graph illustrating improvement in endurance yield and robustness of RRAM devices having primary and secondary switching dielectric layers compared to a single switching dielectric filmstack over changing SET/RESET conditions.

Figure 3 is a diagram comparing reset voltages of a conventional RRAM filmstack to RRAM filmstacks of the present embodiments.

Figure 4 is a graph showing device forming resistance versus forming voltage of a conventional RRAM filmstack compared to RRAM filmstacks of the present embodiments.

Figure 5 illustrates a process of forming an IC structure including a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, in accordance with some embodiments of the present disclosure.

Figures 6A and 6B are top views of a wafer and dice that include one or more embedded non-volatile memory structures such as a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer.

Figure 7 illustrates a block diagram of an electronic system, in accordance with an embodiment of the present disclosure.

Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly.

Figure 9 illustrates a computing device in accordance with one implementation of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

RRAM memory devices having improved endurance and switching yield are described.

In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as“upper”, “lower”,“above”,“below,”“bottom,” and“top” refer to directions in the drawings to which reference is made. Terms such as“front”,“back”,“rear”, and“side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to front-end-of-line (FEOL)

semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL)

semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modem IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

Disclosed embodiments relate to a resistive random access memory (RRAM) device having improved endurance and switching yield through the addition of a secondary switching layer below a primary dielectric layer in a filmstack comprising the RRAM device. The secondary switching layer enables a large improvement in endurance cycling over other filmstacks, allowing manufacturers to meet high-volume manufacturing (HVM) targets for RRAM devices. Such techniques may be particularly useful an embedded non-volatile memory (eNVM) applications

Non-volatile memory devices such as a resistive random access memory (RRAM) device depend on a phenomenon of resistance switching to store information. The RRAM device typically include one transistor (1T) along with one resistor (1R), resulting in 1T-1R

configuration, where the transistor (IT) is used as an access device for reading and/or writing operations, while the resistor (1R) acts as a memristor to store the memory state. The non volatile memory device functions as a variable resistor where the resistance of the device may switch between a high resistance state and a low resistance state.

To provide context, Figure 1 A illustrates a state of the art resistive random access memory (RRAM) device. The RRAM device 100 generally comprises a two-terminal device in which a RRAM 102 is in series with a transistor 104. The RRAM device 100 comprises a filmstack of top and bottom conductive electrodes 106 and 110, with an optional oxygen exchange layer 108 and an insulating switching layer 110 between conductive electrodes 106 and 110. Filamentary RRAM requires an initial forming process whereby a high voltage stress (known as a forming voltage) is applied to the device such that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path. Interfacial RRAM does not require such an initial forming process. The RRAM device 100 can change between two different states: a high-resistance state (HRS), which may be representative of an off or 0 state; and a low-resistance state (LRS), which may be representative of an on or 1 state.

Typically, a reset process is used to switch the RRAM device to from the LRS to the HRS using a reset voltage, and a set process is used to switch the RRAM device from the HRS to the LRS using a set voltage. Long term repeated switching degrades over usage, limiting the cycling endurance, which is measured as the number of set/reset cycles at failure. This is particularly true for an RRAM having a single switching layer 110 comprising a high-K dielectric.

Filmstack modifications have been previously proposed to improve endurance of the RRAM, such as by changing the dielectric material of the switching layer 110, or adding a secondary dielectric layer on top of the switching layer 110. However, none of these proposed film stacks have enabled a large improvement in endurance cycling that allow manufacturers to meet high-volume manufacturing (HVM) targets.

In accordance with one or more embodiments described herein, non-planar BEOL- compatible RRAM devices are fabricated by adding a secondary switching or dielectric layer under the primary switching or dielectric layer. A RRAM fabricated using such an architecture may exhibit an increase in cycling endurance and switching yield. Applications of such systems may include, but are not limited to, back end (BEOL) logic, memory, and embedded memory applications.

Figures 1B and 1C are diagrams illustrating an improved 1T-1R RRAM memory device in accordance with the embodiments disclosed herein. Figure 1B is a schematic diagram of the 1T-1R RRAM memory device and Figure 1C is an angled 3D view of the 1T-1R RRAM memory device where like components have like reference numerals. In this example embodiments, an integrated circuit structure includes a RRAM device 200 in a one transistor one resistor (1T-1R) configuration, where transistor 204 comprises an access transistor and filmstack 202 comprises the resistor. In embodiments, the transistor 204 may include a substrate 218, a source 220, a gate 222, and a drain 224, as shown in Figure 1C. The filmstack 202 includes a bottom electrode 214 coupled to the transistor 204, a secondary switching dielectric layer 212 formed on the bottom electrode 214, a primary switching dielectric layer 212 formed on the secondary switching dielectric layer 212, an oxygen exchange layer (OEL) 208 formed on the primary switching dielectric layer 210, and a top electrode 206 formed on the oxygen exchange layer 208. The bottom electrode 214 of the RRAM 202 may be coupled to either the source 220 or the drain 224 of transistor 204 through an interconnect 216, as shown in Figures 1B and 1C.

According to the embodiments disclosed herein, the RRAM device 200 is provided with the secondary switching dielectric layer 212, which comprises titanium oxide (e.g., Ti02) formed between the primary switching dielectric layer 210 and the bottom electrode 214. In one embodiment, the secondary switching dielectric layer 212 has a thickness of approximately 1-2 nm. Adding a secondary switching dielectric layer 212 of titanium oxide beneath the primary switching dielectric layer 210, as opposed to on top of the primary switching dielectric layer 210, improves endurance cycling yield and enables a lower switching voltage.

The improvement in endurance cycling is attributable not only to locating the secondary switching dielectric layer 212 under the primary switching dielectric layer 210, but also in the combination of materials selected for the filmstack 202. In one embodiment, one or both of the top and bottom electrodes 206, 214 comprise titanium nitride (TiN). In some embodiments, the OEL 208 may be used to provide a more stable switching mechanism for RRAM 202. In one embodiment, the OEL 208 comprises tantalum (Ta), while in other embodiments, the OEL 208 may comprise at least one of hafnium (Hf); titanium (Ti); and tantalum (Ta). In some embodiments, the OEL 208 may have a thickness of approximately 10-20 nm. In some embodiments, the presence of the OEL 208 may be optional.

In one embodiment the primary switching dielectric layer 210 comprises a high-K material, such as tantalum oxide. In one specific embodiment, the primary switching dielectric layer 210 may comprise tantalum pentoxide (Ta205). In some embodiments, the primary switching dielectric layer 210 may have a thickness of approximately 3.5-5.5 nm.

According to one aspect of the disclosure, there are two embodiments for providing the secondary switching dielectric layer 212 of titanium oxide. In a first embodiment, the secondary switching dielectric layer 212 is formed through atomic layer deposition (ALD) of the titanium oxide on the bottom electrode 214, followed by ALD of the primary switching dielectric layer 210 on the secondary switching dielectric layer 212. In this embodiment, the secondary switching dielectric layer 212 may have a thickness of approximately 1-2 nm.

In a second embodiment, the secondary switching dielectric layer 212 is formed through physical vapor deposition (PVD) of tantalum oxide (e.g., Ta205) in an oxidizing environment on the titanium nitride (TiN) bottom electrode 214. In this embodiment, the TiN bottom electrode 214 is partially oxidized to form the secondary switching dielectric layer 212 that comprises at least one of titanium oxide (e.g., Ti02) and titanium oxynitride (TiON).

As described further below, addition the titanium oxide or titanium oxynitride secondary switching dielectric layer 212 under the primary switching dielectric layer 210 of the RRAM filmstack 202 lowers a reset voltage of the memory device by approximately .5 - .1 volts and improves endurance to 1E5 switching cycles.

Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF- SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate a 1T-1R RRAM cell having a titanium oxide secondary switching dielectric layer 212 under a tantalum oxide (TaOx) primary switching dielectric layer 210. Numerous variations and configurations will be apparent in light of this disclosure.

Note, the RRAM filmstacks 202 in the present disclosure are primarily depicted and described herein in the context of a planar stack. However, in some embodiments, the techniques can be used to form filmstacks including a non-planar configuration, such as a U-shaped configuration where one or more of the layers of the filmstack generally have a U shape, to provide one example non-planar configuration. Note that the RRAM cell is primarily depicted and described herein in the context of a 1T-1R configuration including a titanium oxide secondary switching dielectric layer 212 under a tantalum oxide (TaOx) primary switching dielectric layer 210, for ease of description; however, the present disclosure is not intended to be limited to any quantity of transistors, memristor stacks, or RRAM cells, unless otherwise stated. For instance, in some embodiments, multiple RRAM cells as described herein may be used in a memory array, such as in a non-volatile random-access memory (NVRAM) array, for example.

Further still, the access transistor 204 is primarily described and depicted in the context of metal-oxide-semiconductor field-effect transistors (MOSFETs); however, the present disclosure is not intended to be so limited. For example, in some embodiments, the transistors may be tunnel field-effect transistors (TFETs) or any other suitable transistor configuration, as will be apparent in light of the present disclosure. Further, the access transistors in the present disclosure are primarily described and depicted in the context of planar transistor configurations. However, in some embodiments, the techniques can be used to form access transistors including a non-planar configuration, such as finned or finFET configurations (e.g., including a dual-gate or tri-gate configuration) or gate-all-around configurations (e.g., including one or more nanowires or nanoribbons). In some embodiments, the techniques may be used to benefit devices of varying scales, such as transistor devices having critical dimensions in the micrometer range or in the nanometer range (e.g., transistors formed at the 32, 22, 14, 10, 7, or 5 nm process nodes, or beyond).

Continuing with the example RRAM device structure of Figures 1B and 1C, the transistor 204 is formed first followed by the filmstack 202, such that transistor 204 is in series with filmstack 202. In these example embodiments, the filmstack 202 may include a bottom electrode 214, secondary switching dielectric layer 212, primary switching dielectric layer 210, an OEL 208, and top electrode 206. The layers of filmstack 202 may be formed using any suitable techniques. In some embodiments, the processing techniques may include a low thermal budget (e.g., less than 500, 450, 400, 350, or 300 °C), as the processing may occur during back end processing in the interconnect stack.

The filmstack 202 may be formed in the back-end or back-end-of-line (BEOL) portion of the integrated circuit (IC) structure processing, as compared to transistor 204, which may be formed in the front-end or front-end-of-line (FEOL) portion of the IC structure processing. Such back-end processing, in these example embodiments, includes the formation of metallization layers above the transistor 204 as well as the formation of filmstack 202 in the metallization layers. The metallization layers include an interlayer dielectric (ILD) material (not shown) and interconnect features, such as interconnect 216. In one embodiment, interconnect 216 is formed in metallization layer 1 (Ml), while the filmstack 202 is formed in at least metallization layer 2 (M2).

Figure 2 is a graph illustrating improvement in endurance yield and robustness of RRAM devices having primary and secondary switching dielectric layers compared to a single switching dielectric filmstack over changing reset/set conditions. The y-axis of the graph shows endurance yield % of different RRAM configurations over various reset and set voltages shown on the x- axis. For each reset/set voltage, the RRAM devices are switched over a various number of cycles. The three columns in the graph represent three different reset/set voltages, respectively, for different switching conditions. In one embodiment, the three different reset/set voltages are - 4.99V/+3.2V, -4.99V/+3.8V, and -4.5V / +3.8V, respectively. Improved endurance yield (triangles) is plotted for RRAM devices with primary and secondary switching dielectric layers provided by the PVD process (top section) and the ALD process (middle section) versus RRAM devices having a primary switching dielectric only (bottom section).

At reset/set voltages of -4.99V/+3.2V shown the first column, the endurance yield percentage does not significantly vary between the RRAM with the primary switching dielectric layer only and the RRAMs with both types PVD and ALD primary and secondary switching dielectric layers. At reset/set voltages of -4.99V/+3.8V shown the second column, the endurance yield percentage begins to drop with an increasing number of cycles to approximately 80-90% for a primary switching dielectric layer only, but for both types PVD and ALD primary and secondary switching dielectric layers, the endurance yield percentage is between 85-90%. The largest difference occurs at reset/set voltages of -4.5V/+3.8V shown the third column, where the endurance yield percentage increases by approximately 10-15% for both PVD and ALD primary and secondary switching dielectric layers compared to the endurance yield of the single primary switching dielectric layer.

Figure 3 is a diagram comparing reset voltages of a conventional RAM filmstack to RRAM filmstacks of the present embodiments. In this particular example, box plots of five filmstacks are compared, where all five filmstacks have the same configuration for the top BE (l2nm TiN), OEL layer(s) (lOnm TaN and lOnm Ta), and high-K primary switching dielectric layer (4nm Ta205). Different configurations of the bottom secondary switching dielectric shown in the columns are as follows: None, 5 nm Ti02 via ALD, 1 nm Ti02 via ALD, 1.5 nm Ti02 via ALD, and TiOx via PVD. Voltage Reset on the y-axis represents the voltage required to open up the device and switch the device from a 1 to 0. The box plots show that adding a secondary switching dielectric layer of 1 to 1.5 nm of Ti02 via ALD under the high-K primary dielectric layer leads to a filmstack with substantially the same Reset voltage (e.g., .7 to .75 v) as adding a secondary switching dielectric layer via PVD.

Figure 4 is a graph showing device forming resistance versus forming voltage of a conventional RRAM filmstack to RRAM filmstacks of the present embodiments. The forming voltage is shown on the y-axis, while the forming resistance is shown on the x-axis. The dark circles represent no bottom secondary switching dielectric; the“x’s” represent 1.5 nm of Ti02 via ALD; the triangles represent 1 nm of Ti02 via ALD; and the clear circles represent Ta205 via PVD on TiN. The graph shows that the resistance of the dielectric stack and the voltage needed to form a filament converge as the secondary switching dielectric Ti02 is added via ALD under the primary switching dielectric Ta205, matching properties of a filmstack of the primary switching dielectric Ta205 on TiN via PVD. As shown, adding the secondary switching dielectric Ti02 via ALD under the primary switching dielectric Ta205 (triangles) is roughly equivalent to adding the primary switching dielectric Ta205 via PVD on TiN (clear circles).

Figure 5 illustrates a process of forming an IC structure including a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, in accordance with some embodiments of the present disclosure. The example process may begin by forming a transistor (block 500). In one embodiment, the transistor includes at least a source/drain region and a gate.

The process continues with forming a first electrode in electrical contact with the source or drain of the transistor, such as bottom electrode 214 of Figures 1B and 1C (block 502). In one embodiment, and interconnect 216 may be formed that couples the first electrode to the source or the drain of the transistor.

A secondary switching dielectric layer 212 is formed on or above (in physical contact with) the first electrode, (block 504). In one embodiment, the secondary switching dielectric layer 212 comprise a titanium oxide and has a thickness of approximately 1-2 nm. In one embodiment, the secondary switching dielectric layer is formed through atomic layer deposition of titanium oxide on the first electrode. In a second embodiment, the secondary switching dielectric layer is formed through physical vapor deposition of tantalum oxide on the first electrode (which comprises titanium nitride) to form at least one of titanium oxide and titanium oxynitride.

The process continues with forming a primary dielectric layer 210 on the secondary dielectric layer 212 (block 506). The primary switching dielectric layer 210 may comprises a high-K material, such as tantalum oxide. More specifically, the primary switching dielectric layer 210 may comprise tantalum pentoxide (Ta205). In some embodiments, the primary switching dielectric layer 210 may have a thickness of approximately 3.5-5.5 nm.

An oxygen exchange layer (OEL) 208 is optionally formed on the primary dielectric layer 210 (block 508). In one embodiment, the OEL 208 comprises tantalum (Ta), while in other embodiments, the OEL 208 may comprise at least one of hafnium (Hf); titanium (Ti); and tantalum (Ta). In some embodiments, the OEL 208 may have a thickness of approximately 10- 20 nm.

Finally, a second electrode is formed on the OEL 208, such as top electrode 206 shown in FigurelB. The example method may then continue with any additional suitable processing to form a RRAM device/cell.

In some embodiments, the filmstack 202 may be formed on a separate substrate, such as a transfer substrate, and added to the structure shown via bonding or layer stacking techniques. Note that although filmstack 202 is shown as formed above the drain 224 of the transistor 204, and thereby makes use of a vertical co-integration scheme, the present disclosure is not intended to be so limited. For instance, in some embodiments, filmstack 202 may be formed adjacent to access transistor 204 or to the side of access transistor 204, such that it is primarily formed during front-end processing, for example. However, vertical integration of filmstack 202 with access transistor 204 (such that filmstack 202 is above access transistor 100, whether directly above or generally in an area above substrate 218 that is higher in the Y direction than access transistor 204) can help decrease the overall footprint of the RRAM cell structure, as can be understood based on this disclosure. Regardless of the location or method of integrating filmstack 202 with access transistor 204, in some embodiments, access transistor 100 and filmstack 202 can be electrically connected in series to form a 1T-1R RRAM architecture.

In some embodiments, the second electrode may include at least one of: titanium nitride (TiN); tantalum nitride (TaN); copper (Cu); tungsten (W); titanium (Ti); one or more noble metals, such as ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au); and/or any other suitable material or combination of materials, as will be apparent in light of this disclosure. Note that in some embodiments, the layers in filmstack 202 need not have the same or similar widths. Further note that in the example structures of Figures 1B and 1C, first and second electrodes may be considered as bottom electrode 214 and top electrode 206; however, the present disclosure is not intended to be so limited. For instance, in an example embodiment where filmstack 202 is integrated in a horizontal manner (as opposed to the vertical manner shown in Figures 1B), then first and second electrodes and may not be considered bottom and top electrodes (and may instead be considered left and right electrodes, for example).

The integrated circuit structures described herein may be included in an electronic device. As an example of one such apparatus, Figures 6A and 6B are top views of a wafer and dice that include one or more embedded non-volatile memory structures such as a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, in accordance with one or more of the embodiments disclosed herein.

Referring to Figures 6A and 6B, a wafer 600 may be composed of semiconductor material and may include one or more dice 602 having integrated circuit (IC) structures formed on a surface of the wafer 600. Each of the dice 602 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more embedded non-volatile memory structures having a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, such as described above. After the fabrication of the semiconductor product is complete, the wafer 600 may undergo a singulation process in which each of the dice 602 is separated from one another to provide discrete“chips” of the

semiconductor product. In particular, structures that include embedded non-volatile memory structures having an independently scaled selector as disclosed herein may take the form of the wafer 600 (e.g., not singulated) or the form of the die 602 (e.g., singulated). The die 602 may include one or more embedded non-volatile memory structures based independently scaled selectors and/or supporting circuitry to route electrical signals, as well as any other IC components. In some embodiments, the wafer 600 or the die 602 may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 602. For example, a memory array formed by multiple memory devices may be formed on a same die 602 as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

Figure 7 illustrates a block diagram of an electronic system 700, in accordance with an embodiment of the present disclosure. The electronic system 700 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system 700 may include a microprocessor 702 (having a processor 704 and control unit 706), a memory device 708, and an input/output device 710 (it is to be appreciated that the electronic system 700 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system 700 has a set of instructions that define operations which are to be performed on data by the processor 704, as well as, other transactions between the processor 704, the memory device 708, and the input/output device 710. The control unit 706 coordinates the operations of the processor 704, the memory device 708 and the input/output device 710 by cycling through a set of operations that cause instructions to be retrieved from the memory device 708 and executed. The memory device 708 can include a non-volatile memory cell as described in the present description. In an embodiment, the memory device 708 is embedded in the microprocessor 702, as depicted in Figure 7. In an embodiment, the processor 704, or another component of electronic system 700, includes one or more embedded non-volatile memory structures, such as a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, such as those described herein.

Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures such as a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, in accordance with one or more of the embodiments disclosed herein.

Referring to Figure 8, an IC device assembly 800 includes components having one or more integrated circuit structures described herein. The IC device assembly 800 includes a number of components disposed on a circuit board 802 (which may be, e.g., a motherboard).

The IC device assembly 800 includes components disposed on a first face 840 of the circuit board 802 and an opposing second face 842 of the circuit board 802. Generally, components may be disposed on one or both faces 840 and 842. In particular, any suitable ones of the components of the IC device assembly 800 may include a number of embedded non-volatile memory structures such as a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, such as disclosed herein.

In some embodiments, the circuit board 802 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 802. In other embodiments, the circuit board 802 may be a non-PCB substrate.

The IC device assembly 800 illustrated in Figure 8 includes a package-on-interposer structure 836 coupled to the first face 840 of the circuit board 802 by coupling components 816. The coupling components 816 may electrically and mechanically couple the package-on- interposer structure 836 to the circuit board 802, and may include solder balls (as shown in Figure 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 836 may include an IC package 820 coupled to an interposer 804 by coupling components 818. The coupling components 818 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 816. Although a single IC package 820 is shown in Figure 8, multiple IC packages may be coupled to the interposer 804. It is to be appreciated that additional interposers may be coupled to the interposer 804. The interposer 804 may provide an intervening substrate used to bridge the circuit board 802 and the IC package 820. The IC package 820 may be or include, for example, a die (the die 702 of Figure 7B), or any other suitable component.

Generally, the interposer 804 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 804 may couple the IC package 820 (e.g., a die) to a ball grid array (BGA) of the coupling components 816 for coupling to the circuit board 802. In the embodiment illustrated in Figure 8, the IC package 820 and the circuit board 802 are attached to opposing sides of the interposer 804. In other embodiments, the IC package 820 and the circuit board 802 may be attached to a same side of the interposer 804. In some

embodiments, three or more components may be interconnected by way of the interposer 804.

The interposer 804 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 804 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 804 may include metal interconnects 810 and vias 808, including but not limited to through-silicon vias (TSVs) 806. The interposer 804 may further include embedded devices 814, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 804. The package-on-interposer structure 836 may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly 800 may include an IC package 824 coupled to the first face 840 of the circuit board 802 by coupling components 822. The coupling components 822 may take the form of any of the embodiments discussed above with reference to the coupling components 816, and the IC package 824 may take the form of any of the embodiments discussed above with reference to the IC package 820. The IC device assembly 800 illustrated in Figure 8 includes a package-on-package structure 834 coupled to the second face 842 of the circuit board 802 by coupling components 828. The package-on-package structure 834 may include an IC package 826 and an IC package 832 coupled together by coupling components 830 such that the IC package 826 is disposed between the circuit board 802 and the IC package 832. The coupling components 828 and 830 may take the form of any of the embodiments of the coupling components 816 discussed above, and the IC packages 826 and 832 may take the form of any of the embodiments of the IC package 820 discussed above. The package-on-package structure 834 may be configured in accordance with any of the package-on-package structures known in the art.

Figure 9 illustrates a computing device 900 in accordance with one implementation of the disclosure. The computing device 900 houses a board 902. The board 902 may include a number of components, including but not limited to a processor 904 and at least one

communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.

Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more embedded non-volatile memory structures having a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, in accordance with implementations of embodiments of the disclosure. The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more embedded non-volatile memory structures such as a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device 900 may contain an integrated circuit die that includes one or more embedded non-volatile memory structures such as a RRAM device having a secondary switching dielectric layer beneath a primary switching dielectric layer, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

Thus, embodiments described herein include embedded non-volatile memory structures such as a RRAM having a secondary switching dielectric layer beneath a primary switching dielectric layer.

The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example embodiment 1: A resistive random-access memory device comprises a transistor and a filmstack. The memory stack comprises a bottom electrode coupled to the transistor. A primary dielectric is formed over the bottom electrode. An oxygen exchange layer is formed on the primary dielectric. A top electrode is formed on the oxygen exchange layer. A secondary dielectric is formed between the primary dielectric and the bottom electrode to improve endurance cycling and to enable a lower switching voltage.

Example embodiment 2: The memory device of example embodiment 1, wherein the primary dielectric comprises tantalum oxide.

Example embodiment 3: The memory device of claim lor 2, wherein the primary dielectric comprises tantalum pentoxide.

Example embodiment 4: The memory device of claim 1, 2 or 3, wherein the primary dielectric has a thickness of approximately 3.5-5.5 nm.

Example embodiment 5: The memory device of claim 1, 2, 3 or 4, wherein the secondary dielectric comprises titanium oxide.

Example embodiment 6: The memory device of claim 1, 2, 3, 4 or 5, wherein the secondary dielectric has a thickness of approximately 1-2 nm.

Example embodiment 7 : The memory device of claim 1 , 2, 3 or 4, wherein the bottom electrode comprises titanium nitride and the secondary dielectric comprises at least one of titanium oxide and titanium oxynitride.

Example embodiment 8: The memory device of claim 1, 2, 3, 4, 5, 6 or 7, wherein the oxygen exchange layer has a thickness of approximately 10-20 nm.

Example embodiment 9: The memory device of claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein addition of the secondary dielectric to the filmstack lowers a reset voltage of the memory device by approximately .5 - .1 volts.

Example embodiment 10: The memory device of claim 1, 2, 3, 4, 5, 6, 7, 8 or 9, wherein the memory device increases endurance yield by approximately 5 to 15% over a single switching layer RRAM device.

Example embodiment 11 : The memory device of claim 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10, wherein the memory device comprises a resistive random-access memory (RRAM).

Example embodiment 12: A method of fabricating a memory device comprises forming a transistor. A first electrode is formed coupled to the transistor. A secondary dielectric layer is formed on the bottom electrode. A primary dielectric layer is formed on the secondary dielectric layer. And a second electrode is formed on the primary dielectric layer.

Example embodiment 13: The method of claim 12, further comprising forming the primary dielectric using tantalum oxide.

Example embodiment 14: The method of claim 12 or 13, further comprising forming the primary dielectric using tantalum pentoxide.

Example embodiment 15: The method of claim 12, 13 or 14, forming the primary dielectric to have a thickness of approximately 3.5-5.5 nm.

Example embodiment 16: The method of claim 12, 13, 14, or 15 further comprising forming the secondary dielectric layer through atomic layer deposition of titanium oxide.

Example embodiment 17: The method of claim 12, 13, or 15 further comprising:

forming the first electrode using titanium nitride; and forming the secondary dielectric layer through physical vapor deposition of tantalum oxide on the titanium nitride of the first electrode to form at least one of titanium oxide and titanium oxynitride.

Example embodiment 18: The method of claim 12, 13, 14, 15, 16 or 17 further comprising forming the secondary dielectric to have a thickness of approximately 1-2 nm.

Example embodiment 19: The method of claim 12, 13, 14, 15, 16, 17 or 18 further comprising forming an oxygen exchange layer between the primary switching layer and the second electrode to a thickness of approximately 10-20 nm.

Example embodiment 20: The method of claim 12, 13, 14, 15, 16, 17, 18 or 19 further comprising adding the secondary dielectric to the filmstack two lower a reset voltage of the method by approximately .5 - .1 volts.

Example embodiment 21 : The method of claim 12, 13, 14, 15, 16, 17, 18, 19 or 20, further comprising fabricating the memory device to endure 1E5 switching cycles.

Example embodiment 22: The method of claim 12, 13, 14, 15, 16, 17, 18, 19, 20 or 21 further comprising forming the memory device into a RRAM.

Example embodiment 23: A method of fabricating a memory device, the method comprises forming a transistor. A first electrode is formed coupled to the transistor. A secondary dielectric layer is formed on the bottom electrode. A primary dielectric layer is formed on the secondary dielectric layer. An oxygen exchange layer is formed on the primary dielectric layer. And a second electrode is formed on the oxygen exchange layer.

Example embodiment 24: The method of claim 23, further comprising forming the secondary dielectric as titanium oxide.

Example embodiment 25 : The method of claim 23 or 24, further comprising forming the secondary dielectric to have a thickness of approximately 1-2 nm.